[Patch wwwdocs] Document caveat with guard initializations for C++ on architectures without barrier instructions.

[Ramana Radhakrishnan <ramana.radhakrishnan@foss.arm.com>]

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As part of the work on PR66192 I promised a doc update at some point - 
here's that - hopefully better late than never.

I also wonder if this is worth putting into the documentation in 
addition to our release notes though I couldn't convince myself that 
standards.texi was the right place for it- any other suggestions are 
welcome.

OK ?


regards
Ramana


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Index: htdocs/gcc-6/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.html,v
retrieving revision 1.10
diff -a -u -r1.10 changes.html
--- htdocs/gcc-6/changes.html	26 May 2015 10:12:08 -0000	1.10
+++ htdocs/gcc-6/changes.html	4 Jun 2015 09:21:21 -0000
@@ -14,6 +14,20 @@
 <!-- .................................................................. -->
 <h2>Caveats</h2>
 
+    <ul>
+        <li>On bare-metal targets for architectures like ARM
+	  that have a relaxed memory model, the compiler will generate
+	  code that calls <code>__sync_synchronize</code> for thread-safety
+	  of guard accesses for statics in C++ code. In these cases,
+	  it is expected that the user will provide either a stub function to
+	  implement <code>__sync_synchronize</code> to provide a memory
+	  barrier instruction or would compile their application with
+	  <code>-fno-threadsafe-statics</code> as may be appropriate.
+	  This can be demonstrated with the example in
+	  <a href="https://gcc.gnu.org/PR66192">PR66192</a>
+	  for the <code>arm-none-eabi</code> target, with the option
+	  <code>-mcpu=arm7tdmi</code> on the command line.  </li>
+    </ul>
 
 <!-- .................................................................. -->
 <h2 id="general">General Optimizer Improvements</h2>