From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20546 invoked by alias); 2 Jul 2015 13:12:56 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 20535 invoked by uid 89); 2 Jul 2015 13:12:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.2 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 02 Jul 2015 13:12:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1D69875 for ; Thu, 2 Jul 2015 06:13:24 -0700 (PDT) Received: from e106327-lin.cambridge.arm.com (e106327-lin.cambridge.arm.com [10.2.206.124]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8764F3F23A for ; Thu, 2 Jul 2015 06:12:52 -0700 (PDT) Message-ID: <559538D3.8010302@foss.arm.com> Date: Thu, 02 Jul 2015 13:12:00 -0000 From: Matthew Wahab User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: gcc-patches Subject: [PATCH 1/4][ARM][PR target/65697][5.1] Backport stronger barriers for __sync fetch-op builtins. Content-Type: multipart/mixed; boundary="------------090507090004050704040901" X-IsSubscribed: yes X-SW-Source: 2015-07/txt/msg00129.txt.bz2 This is a multi-part message in MIME format. --------------090507090004050704040901 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 850 The __sync builtins are implemented using barriers that are too weak for ARMv8 targets, this has been fixed on trunk for the ARM back-end. Since GCC-5.1 is also generating the incorrect code, it should also be fixed. This patch backports the changes made to strengthen the barriers emitted for the __sync fetch-and-op/op-and-fetch builtins. The trunk patch submission is at https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01410.html The commit is at https://gcc.gnu.org/ml/gcc-cvs/2015-06/msg01235.html Tested the series for arm-none-linux-gnueabihf with check-gcc Ok for the branch? Matthew 2015-07-02 Matthew Wahab Backport from trunk: 2015-06-29 Matthew Wahab PR target/65697 * config/armc/arm.c (arm_split_atomic_op): For ARMv8, replace an initial acquire barrier with final barrier. --------------090507090004050704040901 Content-Type: text/x-patch; name="0001-2015-07-01-Matthew-Wahab-matthew.wahab-arm.com.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0001-2015-07-01-Matthew-Wahab-matthew.wahab-arm.com.patch" Content-length: 2083 >From e7150c85313fff08153197493db568ca8fe2778a Mon Sep 17 00:00:00 2001 From: mwahab Date: Mon, 29 Jun 2015 16:03:34 +0000 Subject: [PATCH 1/4] 2015-07-01 Matthew Wahab Backport PR target/65697 * config/armc/arm.c (arm_split_atomic_op): For ARMv8, replace an initial acquire barrier with final barrier. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225132 138bc75d-0d04-0410-961f-82ee72b054a4 Conflicts: gcc/ChangeLog Change-Id: I2074541794ecad8847ada04690cd9132a51b6404 --- gcc/config/arm/arm.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7b279c7..b36dfb0 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -27807,6 +27807,8 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, rtx_code_label *label; rtx x; + bool is_armv8_sync = arm_arch8 && is_mm_sync (model); + bool use_acquire = TARGET_HAVE_LDACQ && !(is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)); @@ -27815,6 +27817,11 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, && !(is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)); + /* For ARMv8, a load-acquire is too weak for __sync memory orders. Instead, + a full barrier is emitted after the store-release. */ + if (is_armv8_sync) + use_acquire = false; + /* Checks whether a barrier is needed and emits one accordingly. */ if (!(use_acquire || use_release)) arm_pre_atomic_barrier (model); @@ -27885,7 +27892,8 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, emit_unlikely_jump (gen_cbranchsi4 (x, cond, const0_rtx, label)); /* Checks whether a barrier is needed and emits one accordingly. */ - if (!(use_acquire || use_release)) + if (is_armv8_sync + || !(use_acquire || use_release)) arm_post_atomic_barrier (model); } -- 1.9.1 --------------090507090004050704040901--