* [PATCH 1/3] [ARM] PR63870 NEON error messages
2015-07-02 15:40 [PATCH 0/3] [ARM] PR63870 improve error messages for NEON vldN_lane/vstN_lane Charles Baylis
2015-07-02 15:40 ` [PATCH 2/3] [ARM] PR63870 NEON error messages Charles Baylis
2015-07-02 15:40 ` [PATCH 3/3] " Charles Baylis
@ 2015-07-02 15:40 ` Charles Baylis
2015-07-06 10:18 ` Alan Lawrence
2015-07-03 13:01 ` [PATCH 0/3] [ARM] PR63870 improve error messages for NEON vldN_lane/vstN_lane Alan Lawrence
3 siblings, 1 reply; 8+ messages in thread
From: Charles Baylis @ 2015-07-02 15:40 UTC (permalink / raw)
To: Ramana.Radhakrishnan, kyrylo.tkachov; +Cc: gcc-patches
gcc/ChangeLog:
<DATE> Charles Baylis <charles.baylis@linaro.org>
* config/arm/arm-builtins.c (enum arm_type_qualifiers): New enumerators
qualifier_lane_index, qualifier_struct_load_store_lane_index.
(arm_expand_neon_args): New parameter. Remove ellipsis. Handle NEON
argument qualifiers.
(arm_expand_neon_builtin): Handle NEON argument qualifiers.
* config/arm/arm-protos.h: (arm_neon_lane_bounds) New prototype.
* config/arm/arm.c (arm_neon_lane_bounds): New function.
* config/arm/arm.h (ENDIAN_LANE_N): New macro.
Change-Id: Iaa14d8736879fa53776319977eda2089f0a26647
---
gcc/config/arm/arm-builtins.c | 65 ++++++++++++++++++++++++++++++++-----------
gcc/config/arm/arm-protos.h | 4 +++
gcc/config/arm/arm.c | 20 +++++++++++++
gcc/config/arm/arm.h | 3 ++
4 files changed, 75 insertions(+), 17 deletions(-)
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index f960e0a..8f1253e 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -77,7 +77,11 @@ enum arm_type_qualifiers
/* qualifier_const_pointer | qualifier_map_mode */
qualifier_const_pointer_map_mode = 0x86,
/* Polynomial types. */
- qualifier_poly = 0x100
+ qualifier_poly = 0x100,
+ /* Lane indices - must be in range, and flipped for bigendian. */
+ qualifier_lane_index = 0x200,
+ /* Lane indices for single lane structure loads and stores. */
+ qualifier_struct_load_store_lane_index = 0x400
};
/* The qualifier_internal allows generation of a unary builtin from
@@ -1927,6 +1931,8 @@ arm_expand_unop_builtin (enum insn_code icode,
typedef enum {
NEON_ARG_COPY_TO_REG,
NEON_ARG_CONSTANT,
+ NEON_ARG_LANE_INDEX,
+ NEON_ARG_STRUCT_LOAD_STORE_LANE_INDEX,
NEON_ARG_MEMORY,
NEON_ARG_STOP
} builtin_arg;
@@ -1984,9 +1990,9 @@ neon_dereference_pointer (tree exp, tree type, machine_mode mem_mode,
/* Expand a Neon builtin. */
static rtx
arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
- int icode, int have_retval, tree exp, ...)
+ int icode, int have_retval, tree exp,
+ builtin_arg *args)
{
- va_list ap;
rtx pat;
tree arg[SIMD_MAX_BUILTIN_ARGS];
rtx op[SIMD_MAX_BUILTIN_ARGS];
@@ -2001,13 +2007,11 @@ arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
|| !(*insn_data[icode].operand[0].predicate) (target, tmode)))
target = gen_reg_rtx (tmode);
- va_start (ap, exp);
-
formals = TYPE_ARG_TYPES (TREE_TYPE (arm_builtin_decls[fcode]));
for (;;)
{
- builtin_arg thisarg = (builtin_arg) va_arg (ap, int);
+ builtin_arg thisarg = args[argc];
if (thisarg == NEON_ARG_STOP)
break;
@@ -2043,17 +2047,46 @@ arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
break;
+ case NEON_ARG_STRUCT_LOAD_STORE_LANE_INDEX:
+ gcc_assert (argc > 1);
+ if (CONST_INT_P (op[argc]))
+ {
+ arm_neon_lane_bounds (op[argc], 0,
+ GET_MODE_NUNITS (map_mode), exp);
+ /* Keep to GCC-vector-extension lane indices in the RTL. */
+ op[argc] =
+ GEN_INT (ENDIAN_LANE_N (map_mode, INTVAL (op[argc])));
+ }
+ goto constant_arg;
+
+ case NEON_ARG_LANE_INDEX:
+ /* Must be a previous operand into which this is an index. */
+ gcc_assert (argc > 0);
+ if (CONST_INT_P (op[argc]))
+ {
+ machine_mode vmode = insn_data[icode].operand[argc - 1].mode;
+ arm_neon_lane_bounds (op[argc],
+ 0, GET_MODE_NUNITS (vmode), exp);
+ /* Keep to GCC-vector-extension lane indices in the RTL. */
+ op[argc] = GEN_INT (ENDIAN_LANE_N (vmode, INTVAL (op[argc])));
+ }
+ /* Fall through - if the lane index isn't a constant then
+ the next case will error. */
case NEON_ARG_CONSTANT:
+constant_arg:
if (!(*insn_data[icode].operand[opno].predicate)
(op[argc], mode[argc]))
- error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, "
- "expected %<const int%>", argc + 1);
+ {
+ error ("%Kargument %d must be a constant immediate",
+ exp, argc + 1);
+ return const0_rtx;
+ }
break;
+
case NEON_ARG_MEMORY:
/* Check if expand failed. */
if (op[argc] == const0_rtx)
{
- va_end (ap);
return 0;
}
gcc_assert (MEM_P (op[argc]));
@@ -2076,8 +2109,6 @@ arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
}
}
- va_end (ap);
-
if (have_retval)
switch (argc)
{
@@ -2170,7 +2201,11 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
int operands_k = k - is_void;
int expr_args_k = k - 1;
- if (d->qualifiers[qualifiers_k] & qualifier_immediate)
+ if (d->qualifiers[qualifiers_k] & qualifier_lane_index)
+ args[k] = NEON_ARG_LANE_INDEX;
+ else if (d->qualifiers[qualifiers_k] & qualifier_struct_load_store_lane_index)
+ args[k] = NEON_ARG_STRUCT_LOAD_STORE_LANE_INDEX;
+ else if (d->qualifiers[qualifiers_k] & qualifier_immediate)
args[k] = NEON_ARG_CONSTANT;
else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate)
{
@@ -2195,11 +2230,7 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
the function is void, and a 1 if it is not. */
return arm_expand_neon_args
(target, d->mode, fcode, icode, !is_void, exp,
- args[1],
- args[2],
- args[3],
- args[4],
- NEON_ARG_STOP);
+ &args[1]);
}
/* Expand an expression EXP that calls a built-in function,
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 62f91ef..0b4bef5 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -343,6 +343,10 @@ extern void arm_cpu_builtins (struct cpp_reader *, int);
extern bool arm_is_constant_pool_ref (rtx);
+void arm_neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high,
+ const_tree exp);
+
+
/* Flags used to identify the presence of processor capabilities. */
/* Bit values used to identify processor capabilities. */
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index d794fc0..2cbfd64 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -29652,4 +29652,24 @@ arm_sched_fusion_priority (rtx_insn *insn, int max_pri,
*pri = tmp;
return;
}
+
+/* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
+ HIGH (exclusive). */
+void
+arm_neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high,
+ const_tree exp)
+{
+ HOST_WIDE_INT lane;
+ gcc_assert (CONST_INT_P (operand));
+ lane = INTVAL (operand);
+
+ if (lane < low || lane >= high)
+ {
+ if (exp)
+ error ("%Klane %ld out of range %ld - %ld", exp, lane, low, high - 1);
+ else
+ error ("lane %ld out of range %ld - %ld", lane, low, high - 1);
+ }
+}
+
#include "gt-arm.h"
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 373dc85..1a55ac8 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -298,6 +298,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
#define TARGET_BPABI false
#endif
+#define ENDIAN_LANE_N(mode, n) \
+ (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
+
/* Support for a compile-time default CPU, et cetera. The rules are:
--with-arch is ignored if -march or -mcpu are specified.
--with-cpu is ignored if -march or -mcpu are specified, and is overridden
--
1.9.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 0/3] [ARM] PR63870 improve error messages for NEON vldN_lane/vstN_lane
@ 2015-07-02 15:40 Charles Baylis
2015-07-02 15:40 ` [PATCH 2/3] [ARM] PR63870 NEON error messages Charles Baylis
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Charles Baylis @ 2015-07-02 15:40 UTC (permalink / raw)
To: Ramana.Radhakrishnan, kyrylo.tkachov; +Cc: gcc-patches
These patches are a port of the changes do the same thing for AArch64 (see
https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01984.html)
The first patch ports over some infrastructure, and the second converts the
vldN_lane and vstN_lane intrinsics. The changes required for vget_lane and
vset_lane will be done in a future patch.
The third patch includes the test cases from the AArch64 version, except that
the xfails for arm targets have been removed. If this series gets approved
before the AArch64 patch, I will commit the tests with xfail for aarch64
targets.
OK for trunk?
Charles Baylis (3):
[ARM] PR63870 Add qualifiers for NEON builtins
[ARM] PR63870 Mark lane indices of vldN/vstN with appropriate
qualifier
[ARM] PR63870 Add test cases
gcc/config/arm/arm-builtins.c | 69 ++++++++++++++++------
gcc/config/arm/arm-protos.h | 4 ++
gcc/config/arm/arm.c | 20 +++++++
gcc/config/arm/arm.h | 3 +
gcc/config/arm/neon.md | 49 +++++++--------
.../advsimd-intrinsics/vld2_lane_f32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2_lane_f64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld2_lane_p8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2_lane_s16_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2_lane_s32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2_lane_s64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld2_lane_s8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2_lane_u16_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2_lane_u32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2_lane_u64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld2_lane_u8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2q_lane_f32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2q_lane_f64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld2q_lane_p8_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld2q_lane_s16_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2q_lane_s32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2q_lane_s64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld2q_lane_s8_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld2q_lane_u16_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2q_lane_u32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld2q_lane_u64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld2q_lane_u8_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld3_lane_f32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3_lane_f64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld3_lane_p8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3_lane_s16_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3_lane_s32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3_lane_s64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld3_lane_s8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3_lane_u16_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3_lane_u32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3_lane_u64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld3_lane_u8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3q_lane_f32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3q_lane_f64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld3q_lane_p8_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld3q_lane_s16_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3q_lane_s32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3q_lane_s64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld3q_lane_s8_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld3q_lane_u16_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3q_lane_u32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld3q_lane_u64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld3q_lane_u8_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld4_lane_f32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4_lane_f64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld4_lane_p8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4_lane_s16_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4_lane_s32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4_lane_s64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld4_lane_s8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4_lane_u16_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4_lane_u32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4_lane_u64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld4_lane_u8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4q_lane_f32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4q_lane_f64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld4q_lane_p8_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld4q_lane_s16_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4q_lane_s32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4q_lane_s64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld4q_lane_s8_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld4q_lane_u16_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4q_lane_u32_indices_1.c | 15 +++++
.../advsimd-intrinsics/vld4q_lane_u64_indices_1.c | 16 +++++
.../advsimd-intrinsics/vld4q_lane_u8_indices_1.c | 16 +++++
.../advsimd-intrinsics/vst2_lane_f32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2_lane_f64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst2_lane_p8_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2_lane_s16_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2_lane_s32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2_lane_s64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst2_lane_s8_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2_lane_u16_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2_lane_u32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2_lane_u64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst2_lane_u8_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2q_lane_f32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2q_lane_f64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst2q_lane_p8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst2q_lane_s16_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2q_lane_s32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2q_lane_s64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst2q_lane_s8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst2q_lane_u16_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2q_lane_u32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst2q_lane_u64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst2q_lane_u8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst3_lane_f32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3_lane_f64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst3_lane_p8_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3_lane_s16_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3_lane_s32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3_lane_s64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst3_lane_s8_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3_lane_u16_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3_lane_u32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3_lane_u64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst3_lane_u8_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3q_lane_f32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3q_lane_f64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst3q_lane_p8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst3q_lane_s16_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3q_lane_s32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3q_lane_s64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst3q_lane_s8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst3q_lane_u16_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3q_lane_u32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst3q_lane_u64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst3q_lane_u8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst4_lane_f32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4_lane_f64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst4_lane_p8_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4_lane_s16_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4_lane_s32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4_lane_s64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst4_lane_s8_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4_lane_u16_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4_lane_u32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4_lane_u64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst4_lane_u8_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4q_lane_f32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4q_lane_f64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst4q_lane_p8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst4q_lane_s16_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4q_lane_s32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4q_lane_s64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst4q_lane_s8_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst4q_lane_u16_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4q_lane_u32_indices_1.c | 14 +++++
.../advsimd-intrinsics/vst4q_lane_u64_indices_1.c | 15 +++++
.../advsimd-intrinsics/vst4q_lane_u8_indices_1.c | 15 +++++
137 files changed, 2071 insertions(+), 42 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c
--
1.9.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] [ARM] PR63870 NEON error messages
2015-07-02 15:40 [PATCH 0/3] [ARM] PR63870 improve error messages for NEON vldN_lane/vstN_lane Charles Baylis
2015-07-02 15:40 ` [PATCH 2/3] [ARM] PR63870 NEON error messages Charles Baylis
@ 2015-07-02 15:40 ` Charles Baylis
2015-07-02 15:40 ` [PATCH 1/3] " Charles Baylis
2015-07-03 13:01 ` [PATCH 0/3] [ARM] PR63870 improve error messages for NEON vldN_lane/vstN_lane Alan Lawrence
3 siblings, 0 replies; 8+ messages in thread
From: Charles Baylis @ 2015-07-02 15:40 UTC (permalink / raw)
To: Ramana.Radhakrishnan, kyrylo.tkachov; +Cc: gcc-patches
gcc/testsuite/ChangeLog:
<DATE> Charles Baylis <charles.baylis@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c: New test.
Change-Id: I55478568525838da2ff05d8145e08b45e7a74a47
---
.../aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld2q_lane_f32_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld2q_lane_f64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c | 16 ++++++++++++++++
.../advsimd-intrinsics/vld2q_lane_s16_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld2q_lane_s32_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld2q_lane_s64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c | 16 ++++++++++++++++
.../advsimd-intrinsics/vld2q_lane_u16_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld2q_lane_u32_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld2q_lane_u64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld3q_lane_f32_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld3q_lane_f64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c | 16 ++++++++++++++++
.../advsimd-intrinsics/vld3q_lane_s16_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld3q_lane_s32_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld3q_lane_s64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c | 16 ++++++++++++++++
.../advsimd-intrinsics/vld3q_lane_u16_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld3q_lane_u32_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld3q_lane_u64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld4q_lane_f32_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld4q_lane_f64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c | 16 ++++++++++++++++
.../advsimd-intrinsics/vld4q_lane_s16_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld4q_lane_s32_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld4q_lane_s64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c | 16 ++++++++++++++++
.../advsimd-intrinsics/vld4q_lane_u16_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld4q_lane_u32_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vld4q_lane_u64_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c | 16 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst2q_lane_f32_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst2q_lane_f64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vst2q_lane_s16_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst2q_lane_s32_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst2q_lane_s64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vst2q_lane_u16_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst2q_lane_u32_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst2q_lane_u64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst3q_lane_f32_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst3q_lane_f64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vst3q_lane_s16_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst3q_lane_s32_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst3q_lane_s64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vst3q_lane_u16_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst3q_lane_u32_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst3q_lane_u64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c | 14 ++++++++++++++
.../aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst4q_lane_f32_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst4q_lane_f64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vst4q_lane_s16_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst4q_lane_s32_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst4q_lane_s64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c | 15 +++++++++++++++
.../advsimd-intrinsics/vst4q_lane_u16_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst4q_lane_u32_indices_1.c | 14 ++++++++++++++
.../advsimd-intrinsics/vst4q_lane_u64_indices_1.c | 15 +++++++++++++++
.../aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c | 15 +++++++++++++++
132 files changed, 1968 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c
new file mode 100644
index 0000000..d1895f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+float32x2x2_t
+f_vld2_lane_f32 (float32_t * p, float32x2x2_t v)
+{
+ float32x2x2_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld2_lane_f32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld2_lane_f32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c
new file mode 100644
index 0000000..19dd5f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float64x1x2_t
+f_vld2_lane_f64 (float64_t * p, float64x1x2_t v)
+{
+ float64x1x2_t res;
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld2_lane_f64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld2_lane_f64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c
new file mode 100644
index 0000000..df3ce8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+poly8x8x2_t
+f_vld2_lane_p8 (poly8_t * p, poly8x8x2_t v)
+{
+ poly8x8x2_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld2_lane_p8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld2_lane_p8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c
new file mode 100644
index 0000000..ad56c8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int16x4x2_t
+f_vld2_lane_s16 (int16_t * p, int16x4x2_t v)
+{
+ int16x4x2_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld2_lane_s16 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld2_lane_s16 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c
new file mode 100644
index 0000000..8b7455d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int32x2x2_t
+f_vld2_lane_s32 (int32_t * p, int32x2x2_t v)
+{
+ int32x2x2_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld2_lane_s32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld2_lane_s32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c
new file mode 100644
index 0000000..de0a2c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+int64x1x2_t
+f_vld2_lane_s64 (int64_t * p, int64x1x2_t v)
+{
+ int64x1x2_t res;
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld2_lane_s64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld2_lane_s64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c
new file mode 100644
index 0000000..ad414a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int8x8x2_t
+f_vld2_lane_s8 (int8_t * p, int8x8x2_t v)
+{
+ int8x8x2_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld2_lane_s8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld2_lane_s8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c
new file mode 100644
index 0000000..a80b54d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint16x4x2_t
+f_vld2_lane_u16 (uint16_t * p, uint16x4x2_t v)
+{
+ uint16x4x2_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld2_lane_u16 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld2_lane_u16 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c
new file mode 100644
index 0000000..76db072
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint32x2x2_t
+f_vld2_lane_u32 (uint32_t * p, uint32x2x2_t v)
+{
+ uint32x2x2_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld2_lane_u32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld2_lane_u32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c
new file mode 100644
index 0000000..3539a3f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+uint64x1x2_t
+f_vld2_lane_u64 (uint64_t * p, uint64x1x2_t v)
+{
+ uint64x1x2_t res;
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld2_lane_u64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld2_lane_u64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c
new file mode 100644
index 0000000..20e8465
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint8x8x2_t
+f_vld2_lane_u8 (uint8_t * p, uint8x8x2_t v)
+{
+ uint8x8x2_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld2_lane_u8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld2_lane_u8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c
new file mode 100644
index 0000000..0c3c947
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+float32x4x2_t
+f_vld2q_lane_f32 (float32_t * p, float32x4x2_t v)
+{
+ float32x4x2_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld2q_lane_f32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld2q_lane_f32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c
new file mode 100644
index 0000000..5d2eb2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float64x2x2_t
+f_vld2q_lane_f64 (float64_t * p, float64x2x2_t v)
+{
+ float64x2x2_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld2q_lane_f64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld2q_lane_f64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c
new file mode 100644
index 0000000..b48aca4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+poly8x16x2_t
+f_vld2q_lane_p8 (poly8_t * p, poly8x16x2_t v)
+{
+ poly8x16x2_t res;
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld2q_lane_p8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld2q_lane_p8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c
new file mode 100644
index 0000000..c3062c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int16x8x2_t
+f_vld2q_lane_s16 (int16_t * p, int16x8x2_t v)
+{
+ int16x8x2_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld2q_lane_s16 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld2q_lane_s16 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c
new file mode 100644
index 0000000..bfb4f0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int32x4x2_t
+f_vld2q_lane_s32 (int32_t * p, int32x4x2_t v)
+{
+ int32x4x2_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld2q_lane_s32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld2q_lane_s32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c
new file mode 100644
index 0000000..84d453a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+int64x2x2_t
+f_vld2q_lane_s64 (int64_t * p, int64x2x2_t v)
+{
+ int64x2x2_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld2q_lane_s64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld2q_lane_s64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c
new file mode 100644
index 0000000..ec37d1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+int8x16x2_t
+f_vld2q_lane_s8 (int8_t * p, int8x16x2_t v)
+{
+ int8x16x2_t res;
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld2q_lane_s8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld2q_lane_s8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c
new file mode 100644
index 0000000..3588131
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint16x8x2_t
+f_vld2q_lane_u16 (uint16_t * p, uint16x8x2_t v)
+{
+ uint16x8x2_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld2q_lane_u16 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld2q_lane_u16 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c
new file mode 100644
index 0000000..7f27214
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint32x4x2_t
+f_vld2q_lane_u32 (uint32_t * p, uint32x4x2_t v)
+{
+ uint32x4x2_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld2q_lane_u32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld2q_lane_u32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c
new file mode 100644
index 0000000..828f7d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+uint64x2x2_t
+f_vld2q_lane_u64 (uint64_t * p, uint64x2x2_t v)
+{
+ uint64x2x2_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld2q_lane_u64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld2q_lane_u64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c
new file mode 100644
index 0000000..08fe749
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+uint8x16x2_t
+f_vld2q_lane_u8 (uint8_t * p, uint8x16x2_t v)
+{
+ uint8x16x2_t res;
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld2q_lane_u8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld2q_lane_u8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c
new file mode 100644
index 0000000..6d13e2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+float32x2x3_t
+f_vld3_lane_f32 (float32_t * p, float32x2x3_t v)
+{
+ float32x2x3_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld3_lane_f32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld3_lane_f32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c
new file mode 100644
index 0000000..63d5551
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float64x1x3_t
+f_vld3_lane_f64 (float64_t * p, float64x1x3_t v)
+{
+ float64x1x3_t res;
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld3_lane_f64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld3_lane_f64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c
new file mode 100644
index 0000000..a6a9666
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+poly8x8x3_t
+f_vld3_lane_p8 (poly8_t * p, poly8x8x3_t v)
+{
+ poly8x8x3_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld3_lane_p8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld3_lane_p8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c
new file mode 100644
index 0000000..69fd90d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int16x4x3_t
+f_vld3_lane_s16 (int16_t * p, int16x4x3_t v)
+{
+ int16x4x3_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld3_lane_s16 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld3_lane_s16 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c
new file mode 100644
index 0000000..01816e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int32x2x3_t
+f_vld3_lane_s32 (int32_t * p, int32x2x3_t v)
+{
+ int32x2x3_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld3_lane_s32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld3_lane_s32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c
new file mode 100644
index 0000000..f2a6dbd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+int64x1x3_t
+f_vld3_lane_s64 (int64_t * p, int64x1x3_t v)
+{
+ int64x1x3_t res;
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld3_lane_s64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld3_lane_s64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c
new file mode 100644
index 0000000..5d5f845
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int8x8x3_t
+f_vld3_lane_s8 (int8_t * p, int8x8x3_t v)
+{
+ int8x8x3_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld3_lane_s8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld3_lane_s8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c
new file mode 100644
index 0000000..8be04ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint16x4x3_t
+f_vld3_lane_u16 (uint16_t * p, uint16x4x3_t v)
+{
+ uint16x4x3_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld3_lane_u16 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld3_lane_u16 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c
new file mode 100644
index 0000000..bf890d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint32x2x3_t
+f_vld3_lane_u32 (uint32_t * p, uint32x2x3_t v)
+{
+ uint32x2x3_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld3_lane_u32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld3_lane_u32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c
new file mode 100644
index 0000000..926718e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+uint64x1x3_t
+f_vld3_lane_u64 (uint64_t * p, uint64x1x3_t v)
+{
+ uint64x1x3_t res;
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld3_lane_u64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld3_lane_u64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c
new file mode 100644
index 0000000..d129bba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint8x8x3_t
+f_vld3_lane_u8 (uint8_t * p, uint8x8x3_t v)
+{
+ uint8x8x3_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld3_lane_u8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld3_lane_u8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c
new file mode 100644
index 0000000..0c276c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+float32x4x3_t
+f_vld3q_lane_f32 (float32_t * p, float32x4x3_t v)
+{
+ float32x4x3_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld3q_lane_f32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld3q_lane_f32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c
new file mode 100644
index 0000000..2c666c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float64x2x3_t
+f_vld3q_lane_f64 (float64_t * p, float64x2x3_t v)
+{
+ float64x2x3_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld3q_lane_f64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld3q_lane_f64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c
new file mode 100644
index 0000000..2041472
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+poly8x16x3_t
+f_vld3q_lane_p8 (poly8_t * p, poly8x16x3_t v)
+{
+ poly8x16x3_t res;
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld3q_lane_p8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld3q_lane_p8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c
new file mode 100644
index 0000000..7b7b2b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int16x8x3_t
+f_vld3q_lane_s16 (int16_t * p, int16x8x3_t v)
+{
+ int16x8x3_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld3q_lane_s16 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld3q_lane_s16 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c
new file mode 100644
index 0000000..c8db256
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int32x4x3_t
+f_vld3q_lane_s32 (int32_t * p, int32x4x3_t v)
+{
+ int32x4x3_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld3q_lane_s32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld3q_lane_s32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c
new file mode 100644
index 0000000..e350971
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+int64x2x3_t
+f_vld3q_lane_s64 (int64_t * p, int64x2x3_t v)
+{
+ int64x2x3_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld3q_lane_s64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld3q_lane_s64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c
new file mode 100644
index 0000000..1b1c682
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+int8x16x3_t
+f_vld3q_lane_s8 (int8_t * p, int8x16x3_t v)
+{
+ int8x16x3_t res;
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld3q_lane_s8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld3q_lane_s8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c
new file mode 100644
index 0000000..adbc42f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint16x8x3_t
+f_vld3q_lane_u16 (uint16_t * p, uint16x8x3_t v)
+{
+ uint16x8x3_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld3q_lane_u16 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld3q_lane_u16 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c
new file mode 100644
index 0000000..c79388a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint32x4x3_t
+f_vld3q_lane_u32 (uint32_t * p, uint32x4x3_t v)
+{
+ uint32x4x3_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld3q_lane_u32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld3q_lane_u32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c
new file mode 100644
index 0000000..7513140
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+uint64x2x3_t
+f_vld3q_lane_u64 (uint64_t * p, uint64x2x3_t v)
+{
+ uint64x2x3_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld3q_lane_u64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld3q_lane_u64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c
new file mode 100644
index 0000000..5fec76e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+uint8x16x3_t
+f_vld3q_lane_u8 (uint8_t * p, uint8x16x3_t v)
+{
+ uint8x16x3_t res;
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld3q_lane_u8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld3q_lane_u8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c
new file mode 100644
index 0000000..183036f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+float32x2x4_t
+f_vld4_lane_f32 (float32_t * p, float32x2x4_t v)
+{
+ float32x2x4_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld4_lane_f32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld4_lane_f32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c
new file mode 100644
index 0000000..655c27f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float64x1x4_t
+f_vld4_lane_f64 (float64_t * p, float64x1x4_t v)
+{
+ float64x1x4_t res;
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld4_lane_f64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld4_lane_f64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c
new file mode 100644
index 0000000..7bc5140
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+poly8x8x4_t
+f_vld4_lane_p8 (poly8_t * p, poly8x8x4_t v)
+{
+ poly8x8x4_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld4_lane_p8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld4_lane_p8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c
new file mode 100644
index 0000000..5881a89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int16x4x4_t
+f_vld4_lane_s16 (int16_t * p, int16x4x4_t v)
+{
+ int16x4x4_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld4_lane_s16 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld4_lane_s16 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c
new file mode 100644
index 0000000..02282d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int32x2x4_t
+f_vld4_lane_s32 (int32_t * p, int32x2x4_t v)
+{
+ int32x2x4_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld4_lane_s32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld4_lane_s32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c
new file mode 100644
index 0000000..162b5c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+int64x1x4_t
+f_vld4_lane_s64 (int64_t * p, int64x1x4_t v)
+{
+ int64x1x4_t res;
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld4_lane_s64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld4_lane_s64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c
new file mode 100644
index 0000000..4949410
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int8x8x4_t
+f_vld4_lane_s8 (int8_t * p, int8x8x4_t v)
+{
+ int8x8x4_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld4_lane_s8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld4_lane_s8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c
new file mode 100644
index 0000000..16d54e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint16x4x4_t
+f_vld4_lane_u16 (uint16_t * p, uint16x4x4_t v)
+{
+ uint16x4x4_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld4_lane_u16 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld4_lane_u16 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c
new file mode 100644
index 0000000..c65bd30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint32x2x4_t
+f_vld4_lane_u32 (uint32_t * p, uint32x2x4_t v)
+{
+ uint32x2x4_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld4_lane_u32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld4_lane_u32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c
new file mode 100644
index 0000000..e8f2884
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+uint64x1x4_t
+f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v)
+{
+ uint64x1x4_t res;
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld4_lane_u64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ res = vld4_lane_u64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c
new file mode 100644
index 0000000..cb7f487
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint8x8x4_t
+f_vld4_lane_u8 (uint8_t * p, uint8x8x4_t v)
+{
+ uint8x8x4_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld4_lane_u8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld4_lane_u8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c
new file mode 100644
index 0000000..8d7d03e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+float32x4x4_t
+f_vld4q_lane_f32 (float32_t * p, float32x4x4_t v)
+{
+ float32x4x4_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld4q_lane_f32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld4q_lane_f32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c
new file mode 100644
index 0000000..d0ce4e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float64x2x4_t
+f_vld4q_lane_f64 (float64_t * p, float64x2x4_t v)
+{
+ float64x2x4_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld4q_lane_f64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld4q_lane_f64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c
new file mode 100644
index 0000000..bb1cb31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+poly8x16x4_t
+f_vld4q_lane_p8 (poly8_t * p, poly8x16x4_t v)
+{
+ poly8x16x4_t res;
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld4q_lane_p8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld4q_lane_p8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c
new file mode 100644
index 0000000..d96fe0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int16x8x4_t
+f_vld4q_lane_s16 (int16_t * p, int16x8x4_t v)
+{
+ int16x8x4_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld4q_lane_s16 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld4q_lane_s16 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c
new file mode 100644
index 0000000..446ff43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+int32x4x4_t
+f_vld4q_lane_s32 (int32_t * p, int32x4x4_t v)
+{
+ int32x4x4_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld4q_lane_s32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld4q_lane_s32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c
new file mode 100644
index 0000000..df02f39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+int64x2x4_t
+f_vld4q_lane_s64 (int64_t * p, int64x2x4_t v)
+{
+ int64x2x4_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld4q_lane_s64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld4q_lane_s64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c
new file mode 100644
index 0000000..d7573c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+int8x16x4_t
+f_vld4q_lane_s8 (int8_t * p, int8x16x4_t v)
+{
+ int8x16x4_t res;
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld4q_lane_s8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld4q_lane_s8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c
new file mode 100644
index 0000000..05be38b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint16x8x4_t
+f_vld4q_lane_u16 (uint16_t * p, uint16x8x4_t v)
+{
+ uint16x8x4_t res;
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld4q_lane_u16 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ res = vld4q_lane_u16 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c
new file mode 100644
index 0000000..572c6d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+uint32x4x4_t
+f_vld4q_lane_u32 (uint32_t * p, uint32x4x4_t v)
+{
+ uint32x4x4_t res;
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld4q_lane_u32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ res = vld4q_lane_u32 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c
new file mode 100644
index 0000000..a6828df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+uint64x2x4_t
+f_vld4q_lane_u64 (uint64_t * p, uint64x2x4_t v)
+{
+ uint64x2x4_t res;
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld4q_lane_u64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ res = vld4q_lane_u64 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c
new file mode 100644
index 0000000..8b5eb43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+uint8x16x4_t
+f_vld4q_lane_u8 (uint8_t * p, uint8x16x4_t v)
+{
+ uint8x16x4_t res;
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld4q_lane_u8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ res = vld4q_lane_u8 (p, v, -1);
+ return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c
new file mode 100644
index 0000000..a0ea45b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2_lane_f32 (float32_t * p, float32x2x2_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst2_lane_f32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst2_lane_f32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c
new file mode 100644
index 0000000..2eca26f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst2_lane_f64 (float64_t * p, float64x1x2_t v)
+{
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst2_lane_f64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst2_lane_f64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c
new file mode 100644
index 0000000..3692d7d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2_lane_p8 (poly8_t * p, poly8x8x2_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst2_lane_p8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst2_lane_p8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c
new file mode 100644
index 0000000..94ac769
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2_lane_s16 (int16_t * p, int16x4x2_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst2_lane_s16 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst2_lane_s16 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c
new file mode 100644
index 0000000..3ef5687
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2_lane_s32 (int32_t * p, int32x2x2_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst2_lane_s32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst2_lane_s32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c
new file mode 100644
index 0000000..1e3c202
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst2_lane_s64 (int64_t * p, int64x1x2_t v)
+{
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst2_lane_s64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst2_lane_s64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c
new file mode 100644
index 0000000..a96b1b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2_lane_s8 (int8_t * p, int8x8x2_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst2_lane_s8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst2_lane_s8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c
new file mode 100644
index 0000000..970be4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2_lane_u16 (uint16_t * p, uint16x4x2_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst2_lane_u16 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst2_lane_u16 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c
new file mode 100644
index 0000000..4c8e2f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2_lane_u32 (uint32_t * p, uint32x2x2_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst2_lane_u32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst2_lane_u32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c
new file mode 100644
index 0000000..dfb0de2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst2_lane_u64 (uint64_t * p, uint64x1x2_t v)
+{
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst2_lane_u64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst2_lane_u64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c
new file mode 100644
index 0000000..4877ea2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2_lane_u8 (uint8_t * p, uint8x8x2_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst2_lane_u8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst2_lane_u8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c
new file mode 100644
index 0000000..75f7dd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2q_lane_f32 (float32_t * p, float32x4x2_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst2q_lane_f32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst2q_lane_f32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c
new file mode 100644
index 0000000..9a23056
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst2q_lane_f64 (float64_t * p, float64x2x2_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst2q_lane_f64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst2q_lane_f64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c
new file mode 100644
index 0000000..c3f2433
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst2q_lane_p8 (poly8_t * p, poly8x16x2_t v)
+{
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst2q_lane_p8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst2q_lane_p8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c
new file mode 100644
index 0000000..82ae1e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2q_lane_s16 (int16_t * p, int16x8x2_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst2q_lane_s16 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst2q_lane_s16 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c
new file mode 100644
index 0000000..27208bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2q_lane_s32 (int32_t * p, int32x4x2_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst2q_lane_s32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst2q_lane_s32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c
new file mode 100644
index 0000000..a66d55b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst2q_lane_s64 (int64_t * p, int64x2x2_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst2q_lane_s64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst2q_lane_s64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c
new file mode 100644
index 0000000..7a3338b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst2q_lane_s8 (int8_t * p, int8x16x2_t v)
+{
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst2q_lane_s8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst2q_lane_s8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c
new file mode 100644
index 0000000..999ee70
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2q_lane_u16 (uint16_t * p, uint16x8x2_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst2q_lane_u16 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst2q_lane_u16 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c
new file mode 100644
index 0000000..fd4422d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst2q_lane_u32 (uint32_t * p, uint32x4x2_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst2q_lane_u32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst2q_lane_u32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c
new file mode 100644
index 0000000..78863b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst2q_lane_u64 (uint64_t * p, uint64x2x2_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst2q_lane_u64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst2q_lane_u64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c
new file mode 100644
index 0000000..e7463e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst2q_lane_u8 (uint8_t * p, uint8x16x2_t v)
+{
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst2q_lane_u8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst2q_lane_u8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c
new file mode 100644
index 0000000..0cec880
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3_lane_f32 (float32_t * p, float32x2x3_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst3_lane_f32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst3_lane_f32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c
new file mode 100644
index 0000000..d63aa1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst3_lane_f64 (float64_t * p, float64x1x3_t v)
+{
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst3_lane_f64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst3_lane_f64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c
new file mode 100644
index 0000000..0122b75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3_lane_p8 (poly8_t * p, poly8x8x3_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst3_lane_p8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst3_lane_p8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c
new file mode 100644
index 0000000..2c57d2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3_lane_s16 (int16_t * p, int16x4x3_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst3_lane_s16 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst3_lane_s16 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c
new file mode 100644
index 0000000..c0b3a5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3_lane_s32 (int32_t * p, int32x2x3_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst3_lane_s32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst3_lane_s32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c
new file mode 100644
index 0000000..2c2d043
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst3_lane_s64 (int64_t * p, int64x1x3_t v)
+{
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst3_lane_s64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst3_lane_s64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c
new file mode 100644
index 0000000..b93d69a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3_lane_s8 (int8_t * p, int8x8x3_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst3_lane_s8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst3_lane_s8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c
new file mode 100644
index 0000000..ce6025d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3_lane_u16 (uint16_t * p, uint16x4x3_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst3_lane_u16 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst3_lane_u16 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c
new file mode 100644
index 0000000..5696034
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3_lane_u32 (uint32_t * p, uint32x2x3_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst3_lane_u32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst3_lane_u32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c
new file mode 100644
index 0000000..9a36915
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst3_lane_u64 (uint64_t * p, uint64x1x3_t v)
+{
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst3_lane_u64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst3_lane_u64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c
new file mode 100644
index 0000000..9004f3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3_lane_u8 (uint8_t * p, uint8x8x3_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst3_lane_u8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst3_lane_u8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c
new file mode 100644
index 0000000..d1ffc04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3q_lane_f32 (float32_t * p, float32x4x3_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst3q_lane_f32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst3q_lane_f32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c
new file mode 100644
index 0000000..e165f2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst3q_lane_f64 (float64_t * p, float64x2x3_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst3q_lane_f64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst3q_lane_f64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c
new file mode 100644
index 0000000..7fb3c96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst3q_lane_p8 (poly8_t * p, poly8x16x3_t v)
+{
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst3q_lane_p8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst3q_lane_p8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c
new file mode 100644
index 0000000..de8ae54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3q_lane_s16 (int16_t * p, int16x8x3_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst3q_lane_s16 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst3q_lane_s16 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c
new file mode 100644
index 0000000..6502bcf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3q_lane_s32 (int32_t * p, int32x4x3_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst3q_lane_s32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst3q_lane_s32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c
new file mode 100644
index 0000000..c6d8236
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst3q_lane_s64 (int64_t * p, int64x2x3_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst3q_lane_s64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst3q_lane_s64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c
new file mode 100644
index 0000000..2b48619
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst3q_lane_s8 (int8_t * p, int8x16x3_t v)
+{
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst3q_lane_s8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst3q_lane_s8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c
new file mode 100644
index 0000000..6d68051
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3q_lane_u16 (uint16_t * p, uint16x8x3_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst3q_lane_u16 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst3q_lane_u16 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c
new file mode 100644
index 0000000..78b28a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst3q_lane_u32 (uint32_t * p, uint32x4x3_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst3q_lane_u32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst3q_lane_u32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c
new file mode 100644
index 0000000..fe4f52e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst3q_lane_u64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst3q_lane_u64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c
new file mode 100644
index 0000000..74e49db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst3q_lane_u8 (uint8_t * p, uint8x16x3_t v)
+{
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst3q_lane_u8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst3q_lane_u8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c
new file mode 100644
index 0000000..00a8a50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4_lane_f32 (float32_t * p, float32x2x4_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst4_lane_f32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst4_lane_f32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c
new file mode 100644
index 0000000..7cb45ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst4_lane_f64 (float64_t * p, float64x1x4_t v)
+{
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst4_lane_f64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst4_lane_f64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c
new file mode 100644
index 0000000..8b7fef3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4_lane_p8 (poly8_t * p, poly8x8x4_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst4_lane_p8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst4_lane_p8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c
new file mode 100644
index 0000000..e62691c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4_lane_s16 (int16_t * p, int16x4x4_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst4_lane_s16 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst4_lane_s16 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c
new file mode 100644
index 0000000..ced39ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4_lane_s32 (int32_t * p, int32x2x4_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst4_lane_s32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst4_lane_s32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c
new file mode 100644
index 0000000..fe77b4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst4_lane_s64 (int64_t * p, int64x1x4_t v)
+{
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst4_lane_s64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst4_lane_s64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c
new file mode 100644
index 0000000..b287a59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4_lane_s8 (int8_t * p, int8x8x4_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst4_lane_s8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst4_lane_s8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c
new file mode 100644
index 0000000..2144dc4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4_lane_u16 (uint16_t * p, uint16x4x4_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst4_lane_u16 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst4_lane_u16 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c
new file mode 100644
index 0000000..576036c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4_lane_u32 (uint32_t * p, uint32x2x4_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst4_lane_u32 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst4_lane_u32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c
new file mode 100644
index 0000000..b6040b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst4_lane_u64 (uint64_t * p, uint64x1x4_t v)
+{
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst4_lane_u64 (p, v, 1);
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+ vst4_lane_u64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c
new file mode 100644
index 0000000..4ed80cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4_lane_u8 (uint8_t * p, uint8x8x4_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst4_lane_u8 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst4_lane_u8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c
new file mode 100644
index 0000000..ca01289
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4q_lane_f32 (float32_t * p, float32x4x4_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst4q_lane_f32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst4q_lane_f32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c
new file mode 100644
index 0000000..e2b7fb8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst4q_lane_f64 (float64_t * p, float64x2x4_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst4q_lane_f64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst4q_lane_f64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c
new file mode 100644
index 0000000..fb8f4ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst4q_lane_p8 (poly8_t * p, poly8x16x4_t v)
+{
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst4q_lane_p8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst4q_lane_p8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c
new file mode 100644
index 0000000..4855b73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4q_lane_s16 (int16_t * p, int16x8x4_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst4q_lane_s16 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst4q_lane_s16 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c
new file mode 100644
index 0000000..29a8a69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4q_lane_s32 (int32_t * p, int32x4x4_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst4q_lane_s32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst4q_lane_s32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c
new file mode 100644
index 0000000..297cae8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst4q_lane_s64 (int64_t * p, int64x2x4_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst4q_lane_s64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst4q_lane_s64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c
new file mode 100644
index 0000000..10c70cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst4q_lane_s8 (int8_t * p, int8x16x4_t v)
+{
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst4q_lane_s8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst4q_lane_s8 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c
new file mode 100644
index 0000000..d0063ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4q_lane_u16 (uint16_t * p, uint16x8x4_t v)
+{
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst4q_lane_u16 (p, v, 8);
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+ vst4q_lane_u16 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c
new file mode 100644
index 0000000..89b4c52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+
+void
+f_vst4q_lane_u32 (uint32_t * p, uint32x4x4_t v)
+{
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst4q_lane_u32 (p, v, 4);
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+ vst4q_lane_u32 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c
new file mode 100644
index 0000000..ba697c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst4q_lane_u64 (uint64_t * p, uint64x2x4_t v)
+{
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst4q_lane_u64 (p, v, 2);
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+ vst4q_lane_u64 (p, v, -1);
+ return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c
new file mode 100644
index 0000000..61f8ce2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c
@@ -0,0 +1,15 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+void
+f_vst4q_lane_u8 (uint8_t * p, uint8x16x4_t v)
+{
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst4q_lane_u8 (p, v, 16);
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+ vst4q_lane_u8 (p, v, -1);
+ return;
+}
--
1.9.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/3] [ARM] PR63870 NEON error messages
2015-07-02 15:40 [PATCH 0/3] [ARM] PR63870 improve error messages for NEON vldN_lane/vstN_lane Charles Baylis
@ 2015-07-02 15:40 ` Charles Baylis
2015-07-02 15:40 ` [PATCH 3/3] " Charles Baylis
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Charles Baylis @ 2015-07-02 15:40 UTC (permalink / raw)
To: Ramana.Radhakrishnan, kyrylo.tkachov; +Cc: gcc-patches
gcc/ChangeLog:
<DATE> Charles Baylis <charles.baylis@linaro.org>
* config/arm/arm-builtins.c: (arm_load1_qualifiers) Use
qualifier_struct_load_store_lane_index.
(arm_storestruct_lane_qualifiers) Likewise.
* config/arm/neon.md: (neon_vld1_lane<mode>) Reverse lane numbers for
big-endian.
(neon_vst1_lane<mode>) Likewise.
(neon_vld2_lane<mode>) Likewise.
(neon_vst2_lane<mode>) Likewise.
(neon_vld3_lane<mode>) Likewise.
(neon_vst3_lane<mode>) Likewise.
(neon_vld4_lane<mode>) Likewise.
(neon_vst4_lane<mode>) Likewise.
Change-Id: Ic39898d288701bc5b712490265be688f5620c4e2
---
gcc/config/arm/arm-builtins.c | 4 ++--
gcc/config/arm/neon.md | 49 +++++++++++++++++++++++--------------------
2 files changed, 28 insertions(+), 25 deletions(-)
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 8f1253e..b7b7b12 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -145,7 +145,7 @@ arm_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
static enum arm_type_qualifiers
arm_load1_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_const_pointer_map_mode,
- qualifier_none, qualifier_immediate };
+ qualifier_none, qualifier_struct_load_store_lane_index };
#define LOAD1LANE_QUALIFIERS (arm_load1_lane_qualifiers)
/* The first argument (return type) of a store should be void type,
@@ -164,7 +164,7 @@ arm_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
static enum arm_type_qualifiers
arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_pointer_map_mode,
- qualifier_none, qualifier_immediate };
+ qualifier_none, qualifier_struct_load_store_lane_index };
#define STORE1LANE_QUALIFIERS (arm_storestruct_lane_qualifiers)
#define v8qi_UP V8QImode
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 654d9d5..dbd5852 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -4277,8 +4277,9 @@
UNSPEC_VLD1_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
+ operands[3] = GEN_INT (lane);
if (lane < 0 || lane >= max)
error ("lane out of range");
if (max == 1)
@@ -4297,8 +4298,9 @@
UNSPEC_VLD1_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
+ operands[3] = GEN_INT (lane);
int regno = REGNO (operands[0]);
if (lane < 0 || lane >= max)
error ("lane out of range");
@@ -4383,8 +4385,9 @@
UNSPEC_VST1_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
+ operands[2] = GEN_INT (lane);
if (lane < 0 || lane >= max)
error ("lane out of range");
if (max == 1)
@@ -4403,7 +4406,7 @@
UNSPEC_VST1_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
if (lane < 0 || lane >= max)
@@ -4412,8 +4415,8 @@
{
lane -= max / 2;
regno += 2;
- operands[2] = GEN_INT (lane);
}
+ operands[2] = GEN_INT (lane);
operands[1] = gen_rtx_REG (<V_HALF>mode, regno);
if (max == 2)
return "vst1.<V_sz_elem>\t{%P1}, %A0";
@@ -4473,7 +4476,7 @@
UNSPEC_VLD2_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[0]);
rtx ops[4];
@@ -4482,7 +4485,7 @@
ops[0] = gen_rtx_REG (DImode, regno);
ops[1] = gen_rtx_REG (DImode, regno + 2);
ops[2] = operands[1];
- ops[3] = operands[3];
+ ops[3] = GEN_INT (lane);
output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
return "";
}
@@ -4498,7 +4501,7 @@
UNSPEC_VLD2_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[0]);
rtx ops[4];
@@ -4588,7 +4591,7 @@
UNSPEC_VST2_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
rtx ops[4];
@@ -4597,7 +4600,7 @@
ops[0] = operands[0];
ops[1] = gen_rtx_REG (DImode, regno);
ops[2] = gen_rtx_REG (DImode, regno + 2);
- ops[3] = operands[2];
+ ops[3] = GEN_INT (lane);
output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
return "";
}
@@ -4613,7 +4616,7 @@
UNSPEC_VST2_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
rtx ops[4];
@@ -4732,7 +4735,7 @@
UNSPEC_VLD3_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[0]);
rtx ops[5];
@@ -4742,7 +4745,7 @@
ops[1] = gen_rtx_REG (DImode, regno + 2);
ops[2] = gen_rtx_REG (DImode, regno + 4);
ops[3] = operands[1];
- ops[4] = operands[3];
+ ops[4] = GEN_INT (lane);
output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %3",
ops);
return "";
@@ -4759,7 +4762,7 @@
UNSPEC_VLD3_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[0]);
rtx ops[5];
@@ -4904,7 +4907,7 @@
UNSPEC_VST3_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
rtx ops[5];
@@ -4914,7 +4917,7 @@
ops[1] = gen_rtx_REG (DImode, regno);
ops[2] = gen_rtx_REG (DImode, regno + 2);
ops[3] = gen_rtx_REG (DImode, regno + 4);
- ops[4] = operands[2];
+ ops[4] = GEN_INT (lane);
output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %0",
ops);
return "";
@@ -4931,7 +4934,7 @@
UNSPEC_VST3_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
rtx ops[5];
@@ -5054,7 +5057,7 @@
UNSPEC_VLD4_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[0]);
rtx ops[6];
@@ -5065,7 +5068,7 @@
ops[2] = gen_rtx_REG (DImode, regno + 4);
ops[3] = gen_rtx_REG (DImode, regno + 6);
ops[4] = operands[1];
- ops[5] = operands[3];
+ ops[5] = GEN_INT (lane);
output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
ops);
return "";
@@ -5082,7 +5085,7 @@
UNSPEC_VLD4_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[0]);
rtx ops[6];
@@ -5234,7 +5237,7 @@
UNSPEC_VST4_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
rtx ops[6];
@@ -5245,7 +5248,7 @@
ops[2] = gen_rtx_REG (DImode, regno + 2);
ops[3] = gen_rtx_REG (DImode, regno + 4);
ops[4] = gen_rtx_REG (DImode, regno + 6);
- ops[5] = operands[2];
+ ops[5] = GEN_INT (lane);
output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
ops);
return "";
@@ -5262,7 +5265,7 @@
UNSPEC_VST4_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
rtx ops[6];
--
1.9.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/3] [ARM] PR63870 improve error messages for NEON vldN_lane/vstN_lane
2015-07-02 15:40 [PATCH 0/3] [ARM] PR63870 improve error messages for NEON vldN_lane/vstN_lane Charles Baylis
` (2 preceding siblings ...)
2015-07-02 15:40 ` [PATCH 1/3] " Charles Baylis
@ 2015-07-03 13:01 ` Alan Lawrence
3 siblings, 0 replies; 8+ messages in thread
From: Alan Lawrence @ 2015-07-03 13:01 UTC (permalink / raw)
To: Charles Baylis; +Cc: Ramana Radhakrishnan, Kyrylo Tkachov, gcc-patches
Charles Baylis wrote:
> These patches are a port of the changes do the same thing for AArch64 (see
> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01984.html)
>
> The first patch ports over some infrastructure, and the second converts the
> vldN_lane and vstN_lane intrinsics. The changes required for vget_lane and
> vset_lane will be done in a future patch.
>
> The third patch includes the test cases from the AArch64 version, except that
> the xfails for arm targets have been removed. If this series gets approved
> before the AArch64 patch, I will commit the tests with xfail for aarch64
> targets.
Given the large number of test cases, essentially because of test framework
limitations, does it make sense to put these in their own directory? Just a thought.
Cheers, Alan
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] [ARM] PR63870 NEON error messages
2015-07-02 15:40 ` [PATCH 1/3] " Charles Baylis
@ 2015-07-06 10:18 ` Alan Lawrence
2015-07-07 12:30 ` Alan Lawrence
2015-07-07 19:03 ` Charles Baylis
0 siblings, 2 replies; 8+ messages in thread
From: Alan Lawrence @ 2015-07-06 10:18 UTC (permalink / raw)
To: Charles Baylis; +Cc: Ramana Radhakrishnan, Kyrylo Tkachov, gcc-patches
I note some parts of this duplicate my
https://gcc.gnu.org/ml/gcc-patches/2015-01/msg01422.html , which has been pinged
a couple of times. Both Charles' patch, and my two, contain parts the other does
not...
Cheers, Alan
Charles Baylis wrote:
> gcc/ChangeLog:
>
> <DATE> Charles Baylis <charles.baylis@linaro.org>
>
> * config/arm/arm-builtins.c (enum arm_type_qualifiers): New enumerators
> qualifier_lane_index, qualifier_struct_load_store_lane_index.
> (arm_expand_neon_args): New parameter. Remove ellipsis. Handle NEON
> argument qualifiers.
> (arm_expand_neon_builtin): Handle NEON argument qualifiers.
> * config/arm/arm-protos.h: (arm_neon_lane_bounds) New prototype.
> * config/arm/arm.c (arm_neon_lane_bounds): New function.
> * config/arm/arm.h (ENDIAN_LANE_N): New macro.
>
> Change-Id: Iaa14d8736879fa53776319977eda2089f0a26647
> ---
> gcc/config/arm/arm-builtins.c | 65 ++++++++++++++++++++++++++++++++-----------
> gcc/config/arm/arm-protos.h | 4 +++
> gcc/config/arm/arm.c | 20 +++++++++++++
> gcc/config/arm/arm.h | 3 ++
> 4 files changed, 75 insertions(+), 17 deletions(-)
>
> diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
> index f960e0a..8f1253e 100644
> --- a/gcc/config/arm/arm-builtins.c
> +++ b/gcc/config/arm/arm-builtins.c
> @@ -77,7 +77,11 @@ enum arm_type_qualifiers
> /* qualifier_const_pointer | qualifier_map_mode */
> qualifier_const_pointer_map_mode = 0x86,
> /* Polynomial types. */
> - qualifier_poly = 0x100
> + qualifier_poly = 0x100,
> + /* Lane indices - must be in range, and flipped for bigendian. */
> + qualifier_lane_index = 0x200,
> + /* Lane indices for single lane structure loads and stores. */
> + qualifier_struct_load_store_lane_index = 0x400
> };
>
> /* The qualifier_internal allows generation of a unary builtin from
> @@ -1927,6 +1931,8 @@ arm_expand_unop_builtin (enum insn_code icode,
> typedef enum {
> NEON_ARG_COPY_TO_REG,
> NEON_ARG_CONSTANT,
> + NEON_ARG_LANE_INDEX,
> + NEON_ARG_STRUCT_LOAD_STORE_LANE_INDEX,
> NEON_ARG_MEMORY,
> NEON_ARG_STOP
> } builtin_arg;
> @@ -1984,9 +1990,9 @@ neon_dereference_pointer (tree exp, tree type, machine_mode mem_mode,
> /* Expand a Neon builtin. */
> static rtx
> arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
> - int icode, int have_retval, tree exp, ...)
> + int icode, int have_retval, tree exp,
> + builtin_arg *args)
> {
> - va_list ap;
> rtx pat;
> tree arg[SIMD_MAX_BUILTIN_ARGS];
> rtx op[SIMD_MAX_BUILTIN_ARGS];
> @@ -2001,13 +2007,11 @@ arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
> || !(*insn_data[icode].operand[0].predicate) (target, tmode)))
> target = gen_reg_rtx (tmode);
>
> - va_start (ap, exp);
> -
> formals = TYPE_ARG_TYPES (TREE_TYPE (arm_builtin_decls[fcode]));
>
> for (;;)
> {
> - builtin_arg thisarg = (builtin_arg) va_arg (ap, int);
> + builtin_arg thisarg = args[argc];
>
> if (thisarg == NEON_ARG_STOP)
> break;
> @@ -2043,17 +2047,46 @@ arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
> op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
> break;
>
> + case NEON_ARG_STRUCT_LOAD_STORE_LANE_INDEX:
> + gcc_assert (argc > 1);
> + if (CONST_INT_P (op[argc]))
> + {
> + arm_neon_lane_bounds (op[argc], 0,
> + GET_MODE_NUNITS (map_mode), exp);
> + /* Keep to GCC-vector-extension lane indices in the RTL. */
> + op[argc] =
> + GEN_INT (ENDIAN_LANE_N (map_mode, INTVAL (op[argc])));
> + }
> + goto constant_arg;
> +
> + case NEON_ARG_LANE_INDEX:
> + /* Must be a previous operand into which this is an index. */
> + gcc_assert (argc > 0);
> + if (CONST_INT_P (op[argc]))
> + {
> + machine_mode vmode = insn_data[icode].operand[argc - 1].mode;
> + arm_neon_lane_bounds (op[argc],
> + 0, GET_MODE_NUNITS (vmode), exp);
> + /* Keep to GCC-vector-extension lane indices in the RTL. */
> + op[argc] = GEN_INT (ENDIAN_LANE_N (vmode, INTVAL (op[argc])));
> + }
> + /* Fall through - if the lane index isn't a constant then
> + the next case will error. */
> case NEON_ARG_CONSTANT:
> +constant_arg:
> if (!(*insn_data[icode].operand[opno].predicate)
> (op[argc], mode[argc]))
> - error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, "
> - "expected %<const int%>", argc + 1);
> + {
> + error ("%Kargument %d must be a constant immediate",
> + exp, argc + 1);
> + return const0_rtx;
> + }
> break;
> +
> case NEON_ARG_MEMORY:
> /* Check if expand failed. */
> if (op[argc] == const0_rtx)
> {
> - va_end (ap);
> return 0;
> }
> gcc_assert (MEM_P (op[argc]));
> @@ -2076,8 +2109,6 @@ arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
> }
> }
>
> - va_end (ap);
> -
> if (have_retval)
> switch (argc)
> {
> @@ -2170,7 +2201,11 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
> int operands_k = k - is_void;
> int expr_args_k = k - 1;
>
> - if (d->qualifiers[qualifiers_k] & qualifier_immediate)
> + if (d->qualifiers[qualifiers_k] & qualifier_lane_index)
> + args[k] = NEON_ARG_LANE_INDEX;
> + else if (d->qualifiers[qualifiers_k] & qualifier_struct_load_store_lane_index)
> + args[k] = NEON_ARG_STRUCT_LOAD_STORE_LANE_INDEX;
> + else if (d->qualifiers[qualifiers_k] & qualifier_immediate)
> args[k] = NEON_ARG_CONSTANT;
> else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate)
> {
> @@ -2195,11 +2230,7 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
> the function is void, and a 1 if it is not. */
> return arm_expand_neon_args
> (target, d->mode, fcode, icode, !is_void, exp,
> - args[1],
> - args[2],
> - args[3],
> - args[4],
> - NEON_ARG_STOP);
> + &args[1]);
> }
>
> /* Expand an expression EXP that calls a built-in function,
> diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
> index 62f91ef..0b4bef5 100644
> --- a/gcc/config/arm/arm-protos.h
> +++ b/gcc/config/arm/arm-protos.h
> @@ -343,6 +343,10 @@ extern void arm_cpu_builtins (struct cpp_reader *, int);
>
> extern bool arm_is_constant_pool_ref (rtx);
>
> +void arm_neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high,
> + const_tree exp);
> +
> +
> /* Flags used to identify the presence of processor capabilities. */
>
> /* Bit values used to identify processor capabilities. */
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index d794fc0..2cbfd64 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -29652,4 +29652,24 @@ arm_sched_fusion_priority (rtx_insn *insn, int max_pri,
> *pri = tmp;
> return;
> }
> +
> +/* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
> + HIGH (exclusive). */
> +void
> +arm_neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high,
> + const_tree exp)
> +{
> + HOST_WIDE_INT lane;
> + gcc_assert (CONST_INT_P (operand));
> + lane = INTVAL (operand);
> +
> + if (lane < low || lane >= high)
> + {
> + if (exp)
> + error ("%Klane %ld out of range %ld - %ld", exp, lane, low, high - 1);
> + else
> + error ("lane %ld out of range %ld - %ld", lane, low, high - 1);
> + }
> +}
> +
> #include "gt-arm.h"
> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> index 373dc85..1a55ac8 100644
> --- a/gcc/config/arm/arm.h
> +++ b/gcc/config/arm/arm.h
> @@ -298,6 +298,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
> #define TARGET_BPABI false
> #endif
>
> +#define ENDIAN_LANE_N(mode, n) \
> + (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
> +
> /* Support for a compile-time default CPU, et cetera. The rules are:
> --with-arch is ignored if -march or -mcpu are specified.
> --with-cpu is ignored if -march or -mcpu are specified, and is overridden
> --
> 1.9.1
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] [ARM] PR63870 NEON error messages
2015-07-06 10:18 ` Alan Lawrence
@ 2015-07-07 12:30 ` Alan Lawrence
2015-07-07 19:03 ` Charles Baylis
1 sibling, 0 replies; 8+ messages in thread
From: Alan Lawrence @ 2015-07-07 12:30 UTC (permalink / raw)
To: Alan Lawrence
Cc: Charles Baylis, Ramana Radhakrishnan, Kyrylo Tkachov, gcc-patches
Alan Lawrence wrote:
> I note some parts of this duplicate my
> https://gcc.gnu.org/ml/gcc-patches/2015-01/msg01422.html , which has been pinged
> a couple of times. Both Charles' patch, and my two, contain parts the other does
> not...
>
> Cheers, Alan
>
> Charles Baylis wrote:
>> gcc/ChangeLog:
>>
>> <DATE> Charles Baylis <charles.baylis@linaro.org>
>>
>> * config/arm/arm-builtins.c (enum arm_type_qualifiers): New enumerators
>> qualifier_lane_index, qualifier_struct_load_store_lane_index.
>> (arm_expand_neon_args): New parameter. Remove ellipsis. Handle NEON
>> argument qualifiers.
>> (arm_expand_neon_builtin): Handle NEON argument qualifiers.
>> * config/arm/arm-protos.h: (arm_neon_lane_bounds) New prototype.
>> * config/arm/arm.c (arm_neon_lane_bounds): New function.
Further to that - the main difference/conflict between Charles' patch and mine
looks to be that I added the const_tree parameter to the existing
neon_lane_bounds method, whereas Charles' patch adds a new method
arm_neon_lane_bounds.
--Alan
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] [ARM] PR63870 NEON error messages
2015-07-06 10:18 ` Alan Lawrence
2015-07-07 12:30 ` Alan Lawrence
@ 2015-07-07 19:03 ` Charles Baylis
1 sibling, 0 replies; 8+ messages in thread
From: Charles Baylis @ 2015-07-07 19:03 UTC (permalink / raw)
To: Alan Lawrence, Kyrylo Tkachov; +Cc: Ramana Radhakrishnan, gcc-patches
On 6 July 2015 at 11:18, Alan Lawrence <alan.lawrence@arm.com> wrote:
> I note some parts of this duplicate my
> https://gcc.gnu.org/ml/gcc-patches/2015-01/msg01422.html , which has been
> pinged a couple of times. Both Charles' patch, and my two, contain parts the
> other does not...
To resolve the conflicts, I suggest that Alan's patches should be
applied as-is first, and I'll rebase mine afterwards.
...and...
> Further to that - the main difference/conflict between Charles' patch and mine
> looks to be that I added the const_tree parameter to the existing
> neon_lane_bounds method, whereas Charles' patch adds a new method
> arm_neon_lane_bounds.
... I'll clean up this duplication when I do.
^ permalink raw reply [flat|nested] 8+ messages in thread
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2015-07-02 15:40 ` [PATCH 3/3] " Charles Baylis
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2015-07-07 12:30 ` Alan Lawrence
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