From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 105210 invoked by alias); 28 Jul 2015 10:21:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 104472 invoked by uid 89); 28 Jul 2015 10:21:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 28 Jul 2015 10:21:10 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-27-PNDBWCbFT9Ks9EYXPqavag-1; Tue, 28 Jul 2015 11:21:06 +0100 Received: from [10.2.207.49] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 28 Jul 2015 11:21:05 +0100 Message-ID: <55B75791.90709@arm.com> Date: Tue, 28 Jul 2015 10:25:00 -0000 From: Szabolcs Nagy User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.8.0 MIME-Version: 1.0 To: Kyrill Tkachov , "gcc-patches@gcc.gnu.org" CC: Marcus Shawcroft , Ramana Radhakrishnan Subject: Re: Re: [PATCH][ARM] PR target/66731 Fix vnmul insn with -frounding-math References: <55B22104.4050409@arm.com> In-Reply-To: <55B22104.4050409@arm.com> X-MC-Unique: PNDBWCbFT9Ks9EYXPqavag-1 Content-Type: multipart/mixed; boundary="------------070502010204000201020109" X-IsSubscribed: yes X-SW-Source: 2015-07/txt/msg02341.txt.bz2 This is a multi-part message in MIME format. --------------070502010204000201020109 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 2529 On 24/07/15 12:27, Kyrill Tkachov wrote: > On 24/07/15 12:10, Szabolcs Nagy wrote: >> (-a)*b should not be compiled to vnmul a,b with -frounding-math. >> Added a new -(a*b) pattern for vnmul and the old one is only >> used if !flag_rounding_math. Updated the costs too. >> >> This is the ARM version of >> https://gcc.gnu.org/ml/gcc-patches/2015-07/msg00300.html >> >> Tested with arm-none-linux-gnueabihf cross compiler. >> is this OK? >> >> gcc/Changelog: >> >> 2015-07-20 Szabolcs Nagy >> >> PR target/66731 >> * config/arm/arm.md (muldf3negdf_vfp): Handle -frounding-math. >> (mulsf3negsf_vfp): Likewise. > > This entry is misleading. You disable two existing patterns > for flag_rounding_math and you add two new patterns. The > entry should reflect that. .. > Can you give the new pattern a different name to reflect that > the neg is on the outside? Something like *negmulsf3_vfp. .. > +/* { dg-options "-O2 -mfpu=3Dvfp -mfloat-abi=3Dhard" } */ > > Can you please add an explicit -fno-rounding-math here? That way we get a= hint as to > why these tests exist. Alternatively, you can rename the tests to be pr66= 731_1.c, > pr66731_2.c etc. That way in the future we'll know what issue they're tes= ting for. .. > +float > +foo_s (float a, float b) > +{ > + /* { dg-final { scan-assembler "vneg\.f32" } } */ > + /* { dg-final { scan-assembler "vmul\.f32" } } */ > + return -a * b; > +} > > I'd prefer if you just do a scan-assembler not "vnmul", which is what this > patch really fixes. Whether the midend decides to use a pair of vneg+vmul > is tangential to this patch, it's the vnmul that we're trying to avoid. [v2]: - used different names for the new patterns - fixed change log accordingly - used explicit -fno-rounding-math in tests - used scan-assembler-not "vnmul" (I havent changed the names of the tests to be consistent with the aarch64 patches but if ppl prefer pr.c name I can do that.) gcc/Changelog: 2015-07-28 Szabolcs Nagy PR target/66731 * config/arm/arm.md (negmuldf3_vfp): Add new pattern. (negmulsf3_vfp): Likewise. (muldf3negdf_vfp): Disable for -frounding-math. (mulsf3negsf_vfp): Likewise. * config/arm/arm.c (arm_new_rtx_costs): Fix NEG cost for VNMUL, fix MULT cost with -frounding-math. gcc/testsuite/Changelog: 2015-07-28 Szabolcs Nagy PR target/66731 * gcc.target/arm/vnmul-1.c: New. * gcc.target/arm/vnmul-2.c: New. * gcc.target/arm/vnmul-3.c: New. * gcc.target/arm/vnmul-4.c: New. --------------070502010204000201020109 Content-Type: text/x-patch; name=vnmul-2.diff Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="vnmul-2.diff" Content-length: 5335 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index e1bc727..797c9e5 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -10177,7 +10177,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum = rtx_code outer_code, { rtx op0 =3D XEXP (x, 0); =20 - if (GET_CODE (op0) =3D=3D NEG) + if (GET_CODE (op0) =3D=3D NEG && !flag_rounding_math) op0 =3D XEXP (op0, 0); =20 if (speed_p) @@ -10251,6 +10251,13 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum= rtx_code outer_code, if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) =3D=3D MODE_FLOAT && (mode =3D=3D SFmode || !TARGET_VFP_SINGLE)) { + if (GET_CODE (XEXP (x, 0)) =3D=3D MULT) + { + /* VNMUL. */ + *cost =3D rtx_cost (XEXP (x, 0), mode, NEG, 0, speed_p); + return true; + } + if (speed_p) *cost +=3D extra_cost->fp[mode !=3D SFmode].neg; =20 diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index f62ff79..081aab2 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -770,6 +770,17 @@ [(set (match_operand:SF 0 "s_register_operand" "=3Dt") (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t")) (match_operand:SF 2 "s_register_operand" "t")))] + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && !flag_rounding_math" + "vnmul%?.f32\\t%0, %1, %2" + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") + (set_attr "type" "fmuls")] +) + +(define_insn "*negmulsf3_vfp" + [(set (match_operand:SF 0 "s_register_operand" "=3Dt") + (neg:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t") + (match_operand:SF 2 "s_register_operand" "t"))))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "vnmul%?.f32\\t%0, %1, %2" [(set_attr "predicable" "yes") @@ -781,6 +792,18 @@ [(set (match_operand:DF 0 "s_register_operand" "=3Dw") (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w")) (match_operand:DF 2 "s_register_operand" "w")))] + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE + && !flag_rounding_math" + "vnmul%?.f64\\t%P0, %P1, %P2" + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") + (set_attr "type" "fmuld")] +) + +(define_insn "*negmuldf3_vfp" + [(set (match_operand:DF 0 "s_register_operand" "=3Dw") + (neg:DF (mult:DF (match_operand:DF 1 "s_register_operand" "w") + (match_operand:DF 2 "s_register_operand" "w"))))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vnmul%?.f64\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") diff --git a/gcc/testsuite/gcc.target/arm/vnmul-1.c b/gcc/testsuite/gcc.tar= get/arm/vnmul-1.c new file mode 100644 index 0000000..af0bebe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vnmul-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=3Dsoft" } = { "" } } */ +/* { dg-options "-O2 -fno-rounding-math -mfpu=3Dvfp -mfloat-abi=3Dhard" } = */ + +double +foo_d (double a, double b) +{ + /* { dg-final { scan-assembler "vnmul\\.f64" } } */ + return -a * b; +} + +float +foo_s (float a, float b) +{ + /* { dg-final { scan-assembler "vnmul\\.f32" } } */ + return -a * b; +} diff --git a/gcc/testsuite/gcc.target/arm/vnmul-2.c b/gcc/testsuite/gcc.tar= get/arm/vnmul-2.c new file mode 100644 index 0000000..909b2a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vnmul-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=3Dsoft" } = { "" } } */ +/* { dg-options "-O2 -frounding-math -mfpu=3Dvfp -mfloat-abi=3Dhard" } */ + +double +foo_d (double a, double b) +{ + /* { dg-final { scan-assembler-not "vnmul\\.f64" } } */ + return -a * b; +} + +float +foo_s (float a, float b) +{ + /* { dg-final { scan-assembler-not "vnmul\\.f32" } } */ + return -a * b; +} diff --git a/gcc/testsuite/gcc.target/arm/vnmul-3.c b/gcc/testsuite/gcc.tar= get/arm/vnmul-3.c new file mode 100644 index 0000000..df02882 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vnmul-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=3Dsoft" } = { "" } } */ +/* { dg-options "-O2 -fno-rounding-math -mfpu=3Dvfp -mfloat-abi=3Dhard" } = */ + +double +foo_d (double a, double b) +{ + /* { dg-final { scan-assembler "vnmul\\.f64" } } */ + return -(a * b); +} + +float +foo_s (float a, float b) +{ + /* { dg-final { scan-assembler "vnmul\\.f32" } } */ + return -(a * b); +} diff --git a/gcc/testsuite/gcc.target/arm/vnmul-4.c b/gcc/testsuite/gcc.tar= get/arm/vnmul-4.c new file mode 100644 index 0000000..670ee40 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vnmul-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=3Dsoft" } = { "" } } */ +/* { dg-options "-O2 -frounding-math -mfpu=3Dvfp -mfloat-abi=3Dhard" } */ + +double +foo_d (double a, double b) +{ + /* { dg-final { scan-assembler "vnmul\\.f64" } } */ + return -(a * b); +} + +float +foo_s (float a, float b) +{ + /* { dg-final { scan-assembler "vnmul\\.f32" } } */ + return -(a * b); +} --------------070502010204000201020109--