From: Alan Lawrence <alan.lawrence@arm.com>
To: James Greenhalgh <james.greenhalgh@arm.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH 10/15][AArch64] Implement vcvt_{,high_}f16_f32
Date: Wed, 29 Jul 2015 09:18:00 -0000 [thread overview]
Message-ID: <55B89871.2090705@arm.com> (raw)
In-Reply-To: <20150729084622.GA29098@arm.com>
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James Greenhalgh wrote:
> On Tue, Jul 28, 2015 at 12:26:09PM +0100, Alan Lawrence wrote:
>> gcc/ChangeLog:
>>
>> * config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_v2sf):
>> Reparameterize to...
>> (aarch64_float_truncate_lo_<mode>): ...this, for both V2SF and V4HF.
>> (aarch64_float_truncate_hi_v4sf): Reparameterize to...
>> (aarch64_float_truncate_hi_<Vdbl>): ...this, for both V4SF and V8HF.
>>
>> * config/aarch64/aarch64-simd-builtins.def (float_truncate_hi_): Add
>> v8hf variant.
>> (float_truncate_lo_): Use BUILTIN_VDF iterator.
>>
>> * config/aarch64/arm_neon.h (vcvt_f16_f32, vcvt_high_f16_f32): New.
>>
>> * config/aarch64/iterators.md (VDF, Vdtype): New.
>> (VWIDE, Vmwtype): Add cases for V4HF and V2SF.
>>
>
> Hi Alan,
>
> I don't see a patch attached to this one, could you repost with the intended
> patch for review please?
>
> Thanks,
> James
>
Oops, sorry, here it is. (FWIW, not changed since previous version of series.)
Thanks,
Alan
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commit 5007fafedc8469ab645edfe65fbf41f75fc74750
Author: Alan Lawrence <alan.lawrence@arm.com>
Date: Tue Dec 2 18:30:05 2014 +0000
AArch64 4/N v2: float_truncate_lo/hi
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 4dd2bc7..8bcab72 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -363,9 +363,10 @@
VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
+ VAR1 (BINOP, float_truncate_hi_, 0, v8hf)
VAR1 (UNOP, float_extend_lo_, 0, v2df)
- VAR1 (UNOP, float_truncate_lo_, 0, v2sf)
+ BUILTIN_VDF (UNOP, float_truncate_lo_, 0)
/* Implemented by aarch64_ld1<VALL_F16:mode>. */
BUILTIN_VALL_F16 (LOAD1, ld1, 0)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 5cc45ed..2dc54e1 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1726,23 +1726,23 @@
;; Float narrowing operations.
-(define_insn "aarch64_float_truncate_lo_v2sf"
- [(set (match_operand:V2SF 0 "register_operand" "=w")
- (float_truncate:V2SF
- (match_operand:V2DF 1 "register_operand" "w")))]
+(define_insn "aarch64_float_truncate_lo_<mode>"
+ [(set (match_operand:VDF 0 "register_operand" "=w")
+ (float_truncate:VDF
+ (match_operand:<VWIDE> 1 "register_operand" "w")))]
"TARGET_SIMD"
- "fcvtn\\t%0.2s, %1.2d"
+ "fcvtn\\t%0.<Vtype>, %1<Vmwtype>"
[(set_attr "type" "neon_fp_cvt_narrow_d_q")]
)
-(define_insn "aarch64_float_truncate_hi_v4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=w")
- (vec_concat:V4SF
- (match_operand:V2SF 1 "register_operand" "0")
- (float_truncate:V2SF
- (match_operand:V2DF 2 "register_operand" "w"))))]
+(define_insn "aarch64_float_truncate_hi_<Vdbl>"
+ [(set (match_operand:<VDBL> 0 "register_operand" "=w")
+ (vec_concat:<VDBL>
+ (match_operand:VDF 1 "register_operand" "0")
+ (float_truncate:VDF
+ (match_operand:<VWIDE> 2 "register_operand" "w"))))]
"TARGET_SIMD"
- "fcvtn2\\t%0.4s, %2.2d"
+ "fcvtn2\\t%0.<Vdtype>, %2<Vmwtype>"
[(set_attr "type" "neon_fp_cvt_narrow_d_q")]
)
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index d61e619..b915754 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -5726,12 +5726,8 @@ vaddlvq_u32 (uint32x4_t a)
result; \
})
-/* vcvt_f16_f32 not supported */
-
/* vcvt_f32_f16 not supported */
-/* vcvt_high_f16_f32 not supported */
-
/* vcvt_high_f32_f16 not supported */
#define vcvt_n_f32_s32(a, b) \
@@ -13098,6 +13094,18 @@ vcntq_u8 (uint8x16_t __a)
/* vcvt (double -> float). */
+__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
+vcvt_f16_f32 (float32x4_t __a)
+{
+ return __builtin_aarch64_float_truncate_lo_v4hf (__a);
+}
+
+__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
+vcvt_high_f16_f32 (float16x4_t __a, float32x4_t __b)
+{
+ return __builtin_aarch64_float_truncate_hi_v8hf (__a, __b);
+}
+
__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
vcvt_f32_f64 (float64x2_t __a)
{
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 96920cf..f6094b1 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -41,6 +41,9 @@
;; Iterator for General Purpose Float regs, inc float16_t.
(define_mode_iterator GPF_F16 [HF SF DF])
+;; Double vector modes.
+(define_mode_iterator VDF [V2SF V4HF])
+
;; Integer vector modes.
(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
@@ -452,6 +455,9 @@
(SI "V2SI") (DI "V2DI")
(DF "V2DF")])
+;; Register suffix for double-length mode.
+(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
+
;; Double modes of vector modes (lower case).
(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
(V4HF "v8hf")
@@ -485,7 +491,8 @@
(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
(V2SI "V2DI") (V16QI "V8HI")
(V8HI "V4SI") (V4SI "V2DI")
- (HI "SI") (SI "DI")]
+ (HI "SI") (SI "DI")
+ (V4HF "V4SF") (V2SF "V2DF")]
)
@@ -498,6 +505,7 @@
(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
(V2SI ".2d") (V16QI ".8h")
(V8HI ".4s") (V4SI ".2d")
+ (V4HF ".4s") (V2SF ".2d")
(SI "") (HI "")])
;; Lower part register suffixes for VQW.
next prev parent reply other threads:[~2015-07-29 9:10 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-28 11:23 [PATCH 0/15][ARM/AArch64] Add support for float16_t vectors (v3) Alan Lawrence
2015-07-28 11:24 ` [PATCH 3/15][ARM] Add V8HFmode and float16x8_t type Alan Lawrence
2015-07-29 15:12 ` Kyrill Tkachov
2015-07-28 11:24 ` [PATCH 2/15][ARM] float16x4_t intrinsics in arm_neon.h Alan Lawrence
2015-07-29 15:08 ` Kyrill Tkachov
2015-07-28 11:24 ` [PATCH 1/15][ARM] Hide existing float16 intrinsics unless we have a scalar __fp16 type Alan Lawrence
2015-07-29 14:53 ` Kyrill Tkachov
2015-08-20 13:45 ` Alan Lawrence
2015-07-28 11:25 ` [PATCH 4/15][ARM] float16x8_t intrinsics in arm_neon.h Alan Lawrence
2015-07-31 9:51 ` Kyrill Tkachov
2015-07-28 11:25 ` [PATCH 6/15][AArch64] Add basic FP16 support Alan Lawrence
2015-07-29 10:09 ` James Greenhalgh
2015-07-28 11:25 ` [PATCH 5/15][ARM] Remaining intrinsics Alan Lawrence
2015-08-04 11:12 ` Kyrill Tkachov
2015-07-28 11:26 ` [PATCH 10/15][AArch64] Implement vcvt_{,high_}f16_f32 Alan Lawrence
2015-07-29 9:10 ` James Greenhalgh
2015-07-29 9:18 ` Alan Lawrence [this message]
2015-07-29 11:39 ` James Greenhalgh
2015-07-28 11:26 ` [PATCH 7/15][ARM/AArch64 Testsuite] Add basic fp16 tests Alan Lawrence
2015-07-29 10:16 ` James Greenhalgh
2015-07-28 11:26 ` [PATCH 8/15][AArch64] Add support for float14x{4,8}_t vectors/builtins Alan Lawrence
2015-07-29 10:46 ` James Greenhalgh
2015-07-30 12:26 ` [AArch64] Remove unused VRL2/3/4 iterator values (was: Re: [PATCH 8/15][AArch64] Add support for float14x{4,8}_t vectors/builtins) Alan Lawrence
2015-07-30 13:02 ` James Greenhalgh
2015-07-30 15:13 ` [AArch64] Remove unused VRL2/3/4 iterator values Alan Lawrence
2015-07-30 16:01 ` James Greenhalgh
2015-08-04 11:01 ` [PATCH 8/15][AArch64] Add support for float16x{4,8}_t vectors/builtins Alan Lawrence
2015-08-04 11:13 ` Alan Lawrence
2015-08-17 13:19 ` James Greenhalgh
2015-07-28 11:27 ` [PATCH 14/15][ARM/AArch64 Testsuite]Add test of vcvt{,_high}_{f16_f32,f32_f16} Alan Lawrence
2015-08-25 13:28 ` Christophe Lyon
2015-08-25 14:07 ` Alan Lawrence
2015-08-25 13:59 ` [PATCH 14/15][ARM/AArch64 Testsuite]Add test of vcvt{,_high}_i{f32_f16,f16_f32} Alan Lawrence
2015-08-25 14:22 ` Christophe Lyon
2015-09-08 11:00 ` Alan Lawrence
2015-09-08 11:17 ` Kyrill Tkachov
2015-09-22 14:42 ` Marcus Shawcroft
2015-07-28 11:27 ` [PATCH 15/15][ARM] Update sourcebuild.texi with testsuite/effective-target hooks Alan Lawrence
2015-09-08 14:03 ` Alan Lawrence
2015-09-08 14:20 ` Kyrill Tkachov
2015-07-28 11:27 ` [PATCH 9/15][AArch64] vld{2,3,4}{,_lane,_dup}, vcombine, vcreate Alan Lawrence
2015-07-29 9:15 ` James Greenhalgh
2015-08-04 11:03 ` Alan Lawrence
2015-08-04 11:28 ` Alan Lawrence
2015-08-04 11:07 ` [PATCH][ARM/AArch64 Testsuite] Add float16 lane_indices tests (was: Re: [PATCH 9/15][AArch64] vld{2,3,4}{,_lane,_dup}, vcombine, vcreate) Alan Lawrence
2015-08-17 13:35 ` James Greenhalgh
2015-08-06 16:28 ` [PATCH 9/15][AArch64] vld{2,3,4}{,_lane,_dup}, vcombine, vcreate Alan Lawrence
2015-08-17 13:21 ` James Greenhalgh
2015-07-28 11:27 ` [PATCH 11/15][AArch64] vreinterpret(q?), vget_(low|high), vld1(q?)_dup Alan Lawrence
2015-07-29 13:18 ` James Greenhalgh
2015-08-24 9:19 ` Alan Lawrence
2015-09-04 10:18 ` James Greenhalgh
2015-09-07 13:10 ` [PATCH][AArch64] Improve code generation for float16 vector code Alan Lawrence
2015-09-08 8:26 ` James Greenhalgh
2015-09-08 8:26 ` James Greenhalgh
2015-09-08 12:03 ` Alan Lawrence
2015-09-08 8:33 ` [PATCH 11/15][AArch64] vreinterpret(q?), vget_(low|high), vld1(q?)_dup James Greenhalgh
2015-07-28 11:42 ` [PATCH 12/15][AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix Alan Lawrence
2015-07-29 14:08 ` James Greenhalgh
2015-08-25 11:06 ` Alan Lawrence
2015-09-04 9:54 ` James Greenhalgh
2015-07-28 11:48 ` [PATCH 13/15][ARM/AArch64 Testsuite] Add float16 tests to advsimd-intrinsics testsuite Alan Lawrence
2015-08-25 13:27 ` Christophe Lyon
2015-08-25 13:29 ` Alan Lawrence
2015-09-08 10:56 ` Alan Lawrence
2015-09-08 10:56 ` Kyrill Tkachov
2015-09-08 11:09 ` Kyrill Tkachov
2015-08-25 12:54 ` [PATCH 0/15][ARM/AArch64] Add support for float16_t vectors (v3) Alan Lawrence
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