Hi Kyrill,

On 30/07/15 17:08, Kyrill Tkachov wrote:
> Hi Renlin,
>
> On 30/07/15 16:50, Renlin Li wrote:
>> Hi all,
>>
>> This insn should match the following similar rtx pattern and remove the
>> redundant zero_extend operation if the width of zero_extract and
>> inner-size of zero_extend totally match.
>>
>> (set (zero_extract:SI (reg/i:SI 0 x0)
>>                          (const_int 8 [0x8])
>>                      (const_int 0 [0]))
>>         (zero_extend:SI (reg:QI 1 x1 [ y ])))
>>
>>
>> aarch64-none-elf regression tests Okay. Okay to commit?
>>
>> Regards,
>> Renlin
>>
>> gcc/ChangeLog:
>>
>> 2015-07-30  Renlin Li  <renlin.li@arm.com>
>>
>>        * config/aarch64/aarch64.md (combine_bfi): New pattern.
>>
>> gcc/testsuite/ChangeLog:
>>
>> 2015-07-30  Renlin Li  <renlin.li@arm.com>
>>
>>        * gcc.target/aarch64/combine-bfi.c: New.
> +(define_insn "*combine_bfi<GPI:mode><ALLX:mode>"
> +  [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r")
> +			  (match_operand 1 "const_int_operand" "n")
> +			  (match_operand 2 "const_int_operand" "n"))
> +	(zero_extend:GPI (match_operand:ALLX 3  "register_operand" "r")))]
> +  "UINTVAL (operands[1]) == <ALLX:sizen>"
> +  "bfi\\t%<w>0, %<w>3, %2, %1"
> +  [(set_attr "type" "bfm")]
> +)
>
> I notice we don't have any other patterns in aarch64 that start with combine_*.
> Would it be better to name them something like "*aarch64_bfi<GPI:mode><ALLX:mode>4" instead?
Thanks for the suggestion. I have adjust the patch accordingly.

Regards,
Renlin



gcc/ChangeLog:

2015-08-05  Renlin Li  <renlin.li@arm.com>

     * config/aarch64/aarch64.md
           (*aarch64_bfi<GPI:mode><ALLX:mode>4): New pattern.

gcc/testsuite/ChangeLog:

2015-08-05  Renlin Li  <renlin.li@arm.com>

     * gcc.target/aarch64/combine-bfi.c: New.

>
> Kyrill
>
>