From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 65047 invoked by alias); 10 Aug 2015 11:59:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 65035 invoked by uid 89); 10 Aug 2015 11:59:02 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.2 required=5.0 tests=AWL,BAYES_50,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 10 Aug 2015 11:59:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ADF7475 for ; Mon, 10 Aug 2015 04:58:58 -0700 (PDT) Received: from e106327-lin.cambridge.arm.com (e106327-lin.cambridge.arm.com [10.2.206.124]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 96C3B3F23A for ; Mon, 10 Aug 2015 04:58:59 -0700 (PDT) Message-ID: <55C89202.4030602@foss.arm.com> Date: Mon, 10 Aug 2015 11:59:00 -0000 From: Matthew Wahab User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.8.0 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org Subject: [PATCH 4/5][ARM] Use features sets for builtins. References: <55C89141.8050304@foss.arm.com> In-Reply-To: <55C89141.8050304@foss.arm.com> Content-Type: multipart/mixed; boundary="------------030604010105090204090800" X-IsSubscribed: yes X-SW-Source: 2015-08/txt/msg00452.txt.bz2 This is a multi-part message in MIME format. --------------030604010105090204090800 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 985 The ARM backend uses an unsigned long to record CPU feature flags and there are currently 31 bits in use. This series of patches replaces the single unsigned long with a representation based on an array of values. This patch updates the feature flags usage in the builtins description to be able use make of all representable flags. Tested the series for arm-none-linux-gnueabihf with native bootstrap and make check. gcc/ 2015-08-10 Matthew Wahab * config/arm/arm-builtins.c (def_mbuiltin): Test all flags in a feature set. (struct builtin_description): Replace field mask with field features. (IWMMXT_BUILTIN): Use ARM_FSET macros for feature flags. (IWMMXT2_BUILTIN): Likewise. (IWMMXT2_BUILTIN2): Likewise. (FP_BUILTIN): Likewise. (CRC32_BUILTIN): Likewise. (CRYPTO_BUILTIN): Likewise. (iwmmx_mbuiltin): Likewise. (iwmmx2_mbuiltin): Likewise. (arm_init_iwmmxt_builtins): Likewise. Also, update for change to struct builtin_description. --------------030604010105090204090800 Content-Type: text/x-patch; name="0004-Use-features-sets-for-builtins.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0004-Use-features-sets-for-builtins.patch" Content-length: 5104 >From b82186a2d9c1ae31f10827664163a486d3c7906d Mon Sep 17 00:00:00 2001 From: Matthew Wahab Date: Thu, 30 Jul 2015 15:19:39 +0100 Subject: [PATCH 4/5] Use features sets for builtins. Change-Id: I4693a011bb9a3a769c20a8ef3443f25d743b44bd --- gcc/config/arm/arm-builtins.c | 45 +++++++++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index ecc364b..64fbe7f 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -1106,10 +1106,11 @@ arm_init_neon_builtins (void) #undef NUM_DREG_TYPES #undef NUM_QREG_TYPES -#define def_mbuiltin(FLAG, NAME, TYPE, CODE) \ +#define def_mbuiltin(FLAGS, NAME, TYPE, CODE) \ do \ { \ - if (ARM_FSET_HAS_CPU1 (insn_flags, (FLAG))) \ + const arm_feature_set flags = FLAGS; \ + if (ARM_FSET_CPU_SUBSET (flags, insn_flags)) \ { \ tree bdecl; \ bdecl = add_builtin_function ((NAME), (TYPE), (CODE), \ @@ -1121,7 +1122,7 @@ arm_init_neon_builtins (void) struct builtin_description { - const unsigned long mask; + const arm_feature_set features; const enum insn_code icode; const char * const name; const enum arm_builtins code; @@ -1132,11 +1133,13 @@ struct builtin_description static const struct builtin_description bdesc_2arg[] = { #define IWMMXT_BUILTIN(code, string, builtin) \ - { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \ + { ARM_FSET_MAKE_CPU1 (FL_IWMMXT), CODE_FOR_##code, \ + "__builtin_arm_" string, \ ARM_BUILTIN_##builtin, UNKNOWN, 0 }, #define IWMMXT2_BUILTIN(code, string, builtin) \ - { FL_IWMMXT2, CODE_FOR_##code, "__builtin_arm_" string, \ + { ARM_FSET_MAKE_CPU1 (FL_IWMMXT2), CODE_FOR_##code, \ + "__builtin_arm_" string, \ ARM_BUILTIN_##builtin, UNKNOWN, 0 }, IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) @@ -1219,10 +1222,12 @@ static const struct builtin_description bdesc_2arg[] = IWMMXT_BUILTIN (iwmmxt_walignr3, "walignr3", WALIGNR3) #define IWMMXT_BUILTIN2(code, builtin) \ - { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 }, + { ARM_FSET_MAKE_CPU1 (FL_IWMMXT), CODE_FOR_##code, NULL, \ + ARM_BUILTIN_##builtin, UNKNOWN, 0 }, #define IWMMXT2_BUILTIN2(code, builtin) \ - { FL_IWMMXT2, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 }, + { ARM_FSET_MAKE_CPU2 (FL_IWMMXT2), CODE_FOR_##code, NULL, \ + ARM_BUILTIN_##builtin, UNKNOWN, 0 }, IWMMXT2_BUILTIN2 (iwmmxt_waddbhusm, WADDBHUSM) IWMMXT2_BUILTIN2 (iwmmxt_waddbhusl, WADDBHUSL) @@ -1237,7 +1242,7 @@ static const struct builtin_description bdesc_2arg[] = #define FP_BUILTIN(L, U) \ - {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \ + {ARM_FSET_EMPTY, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \ UNKNOWN, 0}, FP_BUILTIN (get_fpscr, GET_FPSCR) @@ -1245,8 +1250,8 @@ static const struct builtin_description bdesc_2arg[] = #undef FP_BUILTIN #define CRC32_BUILTIN(L, U) \ - {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \ - UNKNOWN, 0}, + {ARM_FSET_EMPTY, CODE_FOR_##L, "__builtin_arm_"#L, \ + ARM_BUILTIN_##U, UNKNOWN, 0}, CRC32_BUILTIN (crc32b, CRC32B) CRC32_BUILTIN (crc32h, CRC32H) CRC32_BUILTIN (crc32w, CRC32W) @@ -1256,9 +1261,9 @@ static const struct builtin_description bdesc_2arg[] = #undef CRC32_BUILTIN -#define CRYPTO_BUILTIN(L, U) \ - {0, CODE_FOR_crypto_##L, "__builtin_arm_crypto_"#L, ARM_BUILTIN_CRYPTO_##U, \ - UNKNOWN, 0}, +#define CRYPTO_BUILTIN(L, U) \ + {ARM_FSET_EMPTY, CODE_FOR_crypto_##L, "__builtin_arm_crypto_"#L, \ + ARM_BUILTIN_CRYPTO_##U, UNKNOWN, 0}, #undef CRYPTO1 #undef CRYPTO2 #undef CRYPTO3 @@ -1514,7 +1519,9 @@ arm_init_iwmmxt_builtins (void) machine_mode mode; tree type; - if (d->name == 0 || !(d->mask == FL_IWMMXT || d->mask == FL_IWMMXT2)) + if (d->name == 0 || + !(ARM_FSET_HAS_CPU1 (d->features, FL_IWMMXT) || + ARM_FSET_HAS_CPU1 (d->features, FL_IWMMXT2))) continue; mode = insn_data[d->icode].operand[1].mode; @@ -1538,17 +1545,17 @@ arm_init_iwmmxt_builtins (void) gcc_unreachable (); } - def_mbuiltin (d->mask, d->name, type, d->code); + def_mbuiltin (d->features, d->name, type, d->code); } /* Add the remaining MMX insns with somewhat more complicated types. */ #define iwmmx_mbuiltin(NAME, TYPE, CODE) \ - def_mbuiltin (FL_IWMMXT, "__builtin_arm_" NAME, (TYPE), \ - ARM_BUILTIN_ ## CODE) + def_mbuiltin (ARM_FSET_MAKE_CPU1 (FL_IWMMXT), "__builtin_arm_" NAME, \ + (TYPE), ARM_BUILTIN_ ## CODE) #define iwmmx2_mbuiltin(NAME, TYPE, CODE) \ - def_mbuiltin (FL_IWMMXT2, "__builtin_arm_" NAME, (TYPE), \ - ARM_BUILTIN_ ## CODE) + def_mbuiltin (ARM_FSET_MAKE_CPU1 (FL_IWMMXT2), "__builtin_arm_" NAME, \ + (TYPE), ARM_BUILTIN_ ## CODE) iwmmx_mbuiltin ("wzero", di_ftype_void, WZERO); iwmmx_mbuiltin ("setwcgr0", void_ftype_int, SETWCGR0); -- 1.9.1 --------------030604010105090204090800--