[Aarch64][1/3] Use atomic compare-and-swap instructions when available.

[Matthew Wahab <matthew.wahab@foss.arm.com>]

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ARMv8.1 adds instructions for atomic compare-and-swap with optional
memory ordering specifiers. This patch series adds the instructions to
GCC, making them available with -march=armv8.1-a or with
-march=armv8-a+lse, and using them to implement the __sync and __atomic
builtins.

This patch adds an internal TARGET_LSE macro, to check target support
for the atomic instructions.

Subsequent patches
- add and use atomic compare-and-swap instructions;
- add tests for the compare-and-swap;

Tested the series for aarch64-none-linux-gnu with native bootstrap and make
check and for aarch64-none-elf with cross-compiled check-gcc. Also tested
aarch64-none-elf with cross-compiled check-gcc on an emulator that supports
ARMv8.1.

Ok for trunk?
Matthew

2015-08-12  Matthew Wahab  <matthew.wahab@arm.com>

	* config/aarch64/aarch64.h (AARCH64_ISA_LSE): New.
	(TARGET_LSE): New.

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From 50a71e7572de7eb47c7913ae3d0984cd61f8d425 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Mon, 20 Jul 2015 12:42:52 +0100
Subject: [PATCH 1/3] Add LSE flag testing macro.

Change-Id: I4bfeb5ec617f13026fb7dcd28a9b5c7efa4c1719
---
 gcc/config/aarch64/aarch64.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 721927f..d6c7a74 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -156,6 +156,7 @@ extern unsigned aarch64_architecture_version;
 #define AARCH64_ISA_CRYPTO         (aarch64_isa_flags & AARCH64_FL_CRYPTO)
 #define AARCH64_ISA_FP             (aarch64_isa_flags & AARCH64_FL_FP)
 #define AARCH64_ISA_SIMD           (aarch64_isa_flags & AARCH64_FL_SIMD)
+#define AARCH64_ISA_LSE		   (aarch64_isa_flags & AARCH64_FL_LSE)
 
 /* Crypto is an optional extension to AdvSIMD.  */
 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
@@ -163,6 +164,9 @@ extern unsigned aarch64_architecture_version;
 /* CRC instructions that can be enabled through +crc arch extension.  */
 #define TARGET_CRC32 (AARCH64_ISA_CRC)
 
+/* Atomic instructions that can be enabled through the +lse extension.  */
+#define TARGET_LSE (AARCH64_ISA_LSE)
+
 /* Make sure this is always defined so we don't have to check for ifdefs
    but rather use normal ifs.  */
 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
-- 
1.9.1