From: Matthew Wahab <matthew.wahab@foss.arm.com>
To: gcc-patches@gcc.gnu.org
Subject: [Aarch64][3/3] Add tests for atomic compare-and-swap instructions.
Date: Wed, 12 Aug 2015 10:16:00 -0000 [thread overview]
Message-ID: <55CB1D09.1050305@foss.arm.com> (raw)
In-Reply-To: <55CB1C0D.6070405@foss.arm.com>
[-- Attachment #1: Type: text/plain, Size: 722 bytes --]
ARMv8.1 adds instructions for atomic compare-and-swap with optional
memory ordering specifiers. This patch adds tests for the
compare-and-swap instructions as two files. The first is support code to
run the test with a range of types and memory models, the second is the
test for the CAS instruction.
Tested the series for aarch64-none-linux-gnu with native bootstrap and make
check and for aarch64-none-elf with cross-compiled check-gcc. Also tested
aarch64-none-elf with cross-compiled check-gcc on an emulator that supports
ARMv8.1.
Ok for trunk?
Matthew
gcc/testsuite
2015-08-12 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/aarch64/atomic-inst-cas.c: New.
* gcc.target/aarch64/atomic-inst-ops.inc: New.
[-- Attachment #2: 0003-Add-tests-for-CAS-instruction.patch --]
[-- Type: text/x-patch, Size: 5548 bytes --]
From c72302f2a0bc4d95a0b933e54332d551295040bf Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Mon, 3 Aug 2015 18:10:37 +0100
Subject: [PATCH 3/3] Add tests for CAS instruction.
Change-Id: I42a46c2f81f1200a893620ba96323ce785873e8d
---
gcc/testsuite/gcc.target/aarch64/atomic-inst-cas.c | 61 ++++++++++++++++++++++
.../gcc.target/aarch64/atomic-inst-ops.inc | 53 +++++++++++++++++++
2 files changed, 114 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-inst-cas.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-inst-ops.inc
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-inst-cas.c b/gcc/testsuite/gcc.target/aarch64/atomic-inst-cas.c
new file mode 100644
index 0000000..f6f2892
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-inst-cas.c
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8-a+lse" } */
+
+/* Test ARMv8.1-A CAS instruction. */
+
+#include "atomic-inst-ops.inc"
+
+#define TEST TEST_TWO
+
+#define CAS_ATOMIC(FN, TY, MODEL1, MODEL2) \
+ int FNNAME (FN, TY) (TY* val, TY* foo, TY* bar) \
+ { \
+ int model_s = MODEL1; \
+ int model_f = MODEL2; \
+ /* The success memory ordering must be at least as strong as \
+ the failure memory ordering. */ \
+ if (model_s < model_f) \
+ return 0; \
+ /* Ignore invalid memory orderings. */ \
+ if (model_f == __ATOMIC_RELEASE || model_f == __ATOMIC_ACQ_REL) \
+ return 0; \
+ return __atomic_compare_exchange_n (val, foo, bar, 0, model_s, model_f); \
+ }
+
+#define CAS_ATOMIC_NORETURN(FN, TY, MODEL1, MODEL2) \
+ void FNNAME (FN, TY) (TY* val, TY* foo, TY* bar) \
+ { \
+ int model_s = MODEL1; \
+ int model_f = MODEL2; \
+ /* The success memory ordering must be at least as strong as \
+ the failure memory ordering. */ \
+ if (model_s < model_f) \
+ return; \
+ /* Ignore invalid memory orderings. */ \
+ if (model_f == __ATOMIC_RELEASE || model_f == __ATOMIC_ACQ_REL) \
+ return; \
+ __atomic_compare_exchange_n (val, foo, bar, 0, model_s, model_f); \
+ }
+
+TEST (cas_atomic, CAS_ATOMIC)
+TEST (cas_atomic_noreturn, CAS_ATOMIC_NORETURN)
+
+
+/* { dg-final { scan-assembler-times "casb\t" 4} } */
+/* { dg-final { scan-assembler-times "casab\t" 20} } */
+/* { dg-final { scan-assembler-times "caslb\t" 4} } */
+/* { dg-final { scan-assembler-times "casalb\t" 36} } */
+
+/* { dg-final { scan-assembler-times "cash\t" 4} } */
+/* { dg-final { scan-assembler-times "casah\t" 20} } */
+/* { dg-final { scan-assembler-times "caslh\t" 4} } */
+/* { dg-final { scan-assembler-times "casalh\t" 36} } */
+
+/* { dg-final { scan-assembler-times "cas\t" 8} } */
+/* { dg-final { scan-assembler-times "casa\t" 40} } */
+/* { dg-final { scan-assembler-times "casl\t" 8} } */
+/* { dg-final { scan-assembler-times "casal\t" 72} } */
+
+/* { dg-final { scan-assembler-not "ldaxr\t" } } */
+/* { dg-final { scan-assembler-not "stlxr\t" } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-inst-ops.inc b/gcc/testsuite/gcc.target/aarch64/atomic-inst-ops.inc
new file mode 100644
index 0000000..72c7e5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-inst-ops.inc
@@ -0,0 +1,53 @@
+/* Support code for atomic instruction tests. */
+
+/* Define types names without spaces. */
+typedef unsigned char uchar;
+typedef unsigned short ushort;
+typedef unsigned int uint;
+typedef long long longlong;
+typedef unsigned long long ulonglong;
+typedef __int128_t int128;
+typedef __uint128_t uint128;
+
+#define FNNAME(NAME,TY) NAME
+
+/* Expand one-model functions. */
+#define TEST_M1(NAME, FN, TY, MODEL, DUMMY) \
+ FN (test_##NAME##_##TY, TY, MODEL)
+
+/* Expand two-model functions. */
+#define TEST_M2(NAME, FN, TY, MODEL1, MODEL2) \
+ FN (test_##NAME##_##TY, TY, MODEL1, MODEL2)
+
+/* Typest to test. */
+#define TEST_TY(NAME, FN, N, MODEL1, MODEL2) \
+ TEST_M##N (NAME, FN, char, MODEL1, MODEL2) \
+ TEST_M##N (NAME, FN, uchar, MODEL1, MODEL2) \
+ TEST_M##N (NAME, FN, short, MODEL1, MODEL2) \
+ TEST_M##N (NAME, FN, ushort, MODEL1, MODEL2) \
+ TEST_M##N (NAME, FN, int, MODEL1, MODEL2) \
+ TEST_M##N (NAME, FN, uint, MODEL1, MODEL2) \
+ TEST_M##N (NAME, FN, longlong, MODEL1, MODEL2) \
+ TEST_M##N (NAME, FN, ulonglong, MODEL1, MODEL2) \
+ TEST_M##N (NAME, FN, int128, MODEL1, MODEL2) \
+ TEST_M##N (NAME, FN, uint128, MODEL1, MODEL2)
+
+/* Cross-product of models to test. */
+#define TEST_MODEL_M1(NAME, FN, N, M) \
+ TEST_TY (NAME##_relaxed, FN, N, M, __ATOMIC_RELAXED) \
+ TEST_TY (NAME##_consume, FN, N, M, __ATOMIC_CONSUME) \
+ TEST_TY (NAME##_acquire, FN, N, M, __ATOMIC_ACQUIRE) \
+ TEST_TY (NAME##_release, FN, N, M, __ATOMIC_RELEASE) \
+ TEST_TY (NAME##_acq_rel, FN, N, M, __ATOMIC_ACQ_REL) \
+ TEST_TY (NAME##_seq_cst, FN, N, M, __ATOMIC_SEQ_CST) \
+
+#define TEST_MODEL_M2(NAME, FN) \
+ TEST_MODEL_M1 (NAME##_relaxed, FN, 2, __ATOMIC_RELAXED) \
+ TEST_MODEL_M1 (NAME##_consume, FN, 2, __ATOMIC_CONSUME) \
+ TEST_MODEL_M1 (NAME##_acquire, FN, 2, __ATOMIC_ACQUIRE) \
+ TEST_MODEL_M1 (NAME##_release, FN, 2, __ATOMIC_RELEASE) \
+ TEST_MODEL_M1 (NAME##_acq_rel, FN, 2, __ATOMIC_ACQ_REL) \
+ TEST_MODEL_M1 (NAME##_seq_cst, FN, 2, __ATOMIC_SEQ_CST) \
+
+/* Expand functions for a cross-product of memory models and types. */
+#define TEST_TWO(NAME, FN) TEST_MODEL_M2 (NAME, FN)
--
1.9.1
next prev parent reply other threads:[~2015-08-12 10:16 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-12 10:12 [Aarch64][1/3] Use atomic compare-and-swap instructions when available Matthew Wahab
2015-08-12 10:15 ` [Aarch64][2/3] Use the " Matthew Wahab
2015-08-12 11:18 ` James Greenhalgh
2015-08-12 10:16 ` Matthew Wahab [this message]
2015-08-12 10:51 ` [Aarch64][3/3] Add tests for atomic compare-and-swap instructions Andrew Pinski
2015-08-12 11:13 ` Matthew Wahab
2015-08-12 11:26 ` James Greenhalgh
2015-08-12 10:42 ` [Aarch64][1/3] Use atomic compare-and-swap instructions when available James Greenhalgh
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