* [PING][PATCH][3/N] Replace the pattern GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m)
@ 2015-08-13 10:16 David Sherwood
2015-08-13 21:31 ` Jeff Law
0 siblings, 1 reply; 2+ messages in thread
From: David Sherwood @ 2015-08-13 10:16 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1859 bytes --]
Hi,
This patch follows on from
[PATCH][1/N] Change GET_MODE_INNER to always return a non-void mode
It is another tidy up, replacing the pattern
GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m). Also
replaces any calls to GET_MODE_PRECISION (GET_MODE_INNER (m)) with
GET_MODE_UNIT_PRECISION (m).
Tested:
aarch64 and aarch64_be - no regressions in gcc testsuite
x86_64 - bootstrap build, no testsuite regressions
arm-none-eabi - no regressions in gcc testsuite
Run contrib/config-list.mk - no regressions
Good to go?
Thanks,
David.
2015-08-04 David Sherwood <david.sherwood@arm.com>
gcc/
* config/arm/arm.c (neon_element_bits): Replace call to
GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m).
* config/arm/neon.md (neon_vget_lane<mode>): Likewise.
(neon_vget_laneu<mode>, neon_vset_lane<mode>): Likewise
(neon_vdup_lane<mode>): Likewise.
* config/i386/i386.c (ix86_expand_int_vcond): Likewise.
(ix86_expand_multi_arg_builtin, ix86_expand_reduc): Likewise.
(expand_vec_perm_palignr, ix86_expand_sse2_abs): Likewise.
* config/rs6000/rs6000.c (rs6000_do_expand_vec_perm): Likewise.
* config/spu/spu.c (arith_immediate_p): Likewise.
* expmed.c (store_bit_field_1, extract_bit_field_1): Likewise.
* expr.c (expand_expr_real_2): Likewise.
* optabs.c (shift_amt_for_vec_perm_mask): Likewise.
* simplify-rtx.c (simplify_immed_subreg): Likewise.
* tree-cfg.c (verify_gimple_assign_ternary): Likewise.
* tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern): Likewise.
New variable.
* fold-const.c (fold_binary_loc): Replace call to
GET_MODE_PRECISION (GET_MODE_INNER (m)) with
GET_MODE_UNIT_PRECISION (m).
[-- Attachment #2: mode_inner3.patch --]
[-- Type: application/octet-stream, Size: 11756 bytes --]
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index bcd387b..82b6078 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -12818,7 +12818,7 @@ neon_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
HOST_WIDE_INT
neon_element_bits (machine_mode mode)
{
- return GET_MODE_BITSIZE (GET_MODE_INNER (mode));
+ return GET_MODE_UNIT_BITSIZE (mode);
}
\f
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 654d9d5..e7072cd 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2674,12 +2674,12 @@
to this model. */
unsigned int elt = INTVAL (operands[2]);
unsigned int reg_nelts
- = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode));
+ = 64 / GET_MODE_UNIT_BITSIZE (<MODE>mode);
elt ^= reg_nelts - 1;
operands[2] = GEN_INT (elt);
}
- if (GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode)) == 32)
+ if (GET_MODE_UNIT_BITSIZE (<MODE>mode) == 32)
emit_insn (gen_vec_extract<mode> (operands[0], operands[1], operands[2]));
else
emit_insn (gen_neon_vget_lane<mode>_sext_internal (operands[0],
@@ -2705,12 +2705,12 @@
to this model. */
unsigned int elt = INTVAL (operands[2]);
unsigned int reg_nelts
- = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode));
+ = 64 / GET_MODE_UNIT_BITSIZE (<MODE>mode);
elt ^= reg_nelts - 1;
operands[2] = GEN_INT (elt);
}
- if (GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode)) == 32)
+ if (GET_MODE_UNIT_BITSIZE (<MODE>mode) == 32)
emit_insn (gen_vec_extract<mode> (operands[0], operands[1], operands[2]));
else
emit_insn (gen_neon_vget_lane<mode>_zext_internal (operands[0],
@@ -2764,7 +2764,7 @@
if (BYTES_BIG_ENDIAN)
{
unsigned int reg_nelts
- = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode));
+ = 64 / GET_MODE_UNIT_BITSIZE (<MODE>mode);
elt ^= reg_nelts - 1;
}
@@ -2869,7 +2869,7 @@
{
unsigned int elt = INTVAL (operands[2]);
unsigned int reg_nelts
- = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<V_double_vector_mode>mode));
+ = 64 / GET_MODE_UNIT_BITSIZE (<V_double_vector_mode>mode);
elt ^= reg_nelts - 1;
operands[2] = GEN_INT (elt);
}
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 145089e..c3d6cc2 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -21813,7 +21813,7 @@ ix86_expand_int_vcond (rtx operands[])
|| (TARGET_AVX2 && GET_MODE_SIZE (data_mode) == 32)))
{
rtx negop = operands[2 - (code == LT)];
- int shift = GET_MODE_BITSIZE (GET_MODE_INNER (data_mode)) - 1;
+ int shift = GET_MODE_UNIT_BITSIZE (data_mode) - 1;
if (negop == CONST1_RTX (data_mode))
{
rtx res = expand_simple_binop (mode, LSHIFTRT, cop0, GEN_INT (shift),
@@ -36240,7 +36240,7 @@ ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
xop_rotl:
if (CONST_INT_P (op))
{
- int mask = GET_MODE_BITSIZE (GET_MODE_INNER (tmode)) - 1;
+ int mask = GET_MODE_UNIT_BITSIZE (tmode) - 1;
op = GEN_INT (INTVAL (op) & mask);
gcc_checking_assert
(insn_data[icode].operand[i + 1].predicate (op, mode));
@@ -45647,12 +45647,12 @@ ix86_expand_reduc (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
}
for (i = GET_MODE_BITSIZE (mode);
- i > GET_MODE_BITSIZE (GET_MODE_INNER (mode));
+ i > GET_MODE_UNIT_BITSIZE (mode);
i >>= 1)
{
half = gen_reg_rtx (mode);
emit_reduc_half (half, vec, i);
- if (i == GET_MODE_BITSIZE (GET_MODE_INNER (mode)) * 2)
+ if (i == GET_MODE_UNIT_BITSIZE (mode) * 2)
dst = dest;
else
dst = gen_reg_rtx (mode);
@@ -48022,7 +48022,7 @@ expand_vec_perm_palignr (struct expand_vec_perm_d *d, bool single_insn_only_p)
return expand_vec_perm_1 (&dcopy);
}
- shift = GEN_INT (min * GET_MODE_BITSIZE (GET_MODE_INNER (d->vmode)));
+ shift = GEN_INT (min * GET_MODE_UNIT_BITSIZE (d->vmode));
if (GET_MODE_SIZE (d->vmode) == 16)
{
target = gen_reg_rtx (TImode);
@@ -50472,8 +50472,7 @@ ix86_expand_sse2_abs (rtx target, rtx input)
value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
case V4SImode:
tmp0 = expand_simple_binop (mode, ASHIFTRT, input,
- GEN_INT (GET_MODE_BITSIZE
- (GET_MODE_INNER (mode)) - 1),
+ GEN_INT (GET_MODE_UNIT_BITSIZE (mode) - 1),
NULL, 0, OPTAB_DIRECT);
tmp1 = expand_simple_binop (mode, XOR, tmp0, input,
NULL, 0, OPTAB_DIRECT);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 4c9c6b1..bcf05c2 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -31973,8 +31973,7 @@ rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
imode = vmode;
if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT)
{
- imode = GET_MODE_INNER (vmode);
- imode = mode_for_size (GET_MODE_BITSIZE (imode), MODE_INT, 0);
+ imode = mode_for_size (GET_MODE_UNIT_BITSIZE (vmode), MODE_INT, 0);
imode = mode_for_vector (imode, nelt);
}
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index f51dd43..ca76287 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -3392,7 +3392,7 @@ arith_immediate_p (rtx op, machine_mode mode,
constant_to_array (mode, op, arr);
bytes = GET_MODE_UNIT_SIZE (mode);
- mode = mode_for_size (GET_MODE_BITSIZE (GET_MODE_INNER (mode)), MODE_INT, 0);
+ mode = mode_for_size (GET_MODE_UNIT_BITSIZE (mode), MODE_INT, 0);
/* Check that bytes are repeated. */
for (i = bytes; i < 16; i += bytes)
diff --git a/gcc/expmed.c b/gcc/expmed.c
index 3c70cde..59b2919 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -680,8 +680,8 @@ store_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
&& !MEM_P (op0)
&& optab_handler (vec_set_optab, GET_MODE (op0)) != CODE_FOR_nothing
&& fieldmode == GET_MODE_INNER (GET_MODE (op0))
- && bitsize == GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
- && !(bitnum % GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
+ && bitsize == GET_MODE_UNIT_BITSIZE (GET_MODE (op0))
+ && !(bitnum % GET_MODE_UNIT_BITSIZE (GET_MODE (op0))))
{
struct expand_operand ops[3];
machine_mode outermode = GET_MODE (op0);
@@ -1491,8 +1491,8 @@ extract_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
if (VECTOR_MODE_P (GET_MODE (op0))
&& !MEM_P (op0)
&& optab_handler (vec_extract_optab, GET_MODE (op0)) != CODE_FOR_nothing
- && ((bitnum + bitsize - 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
- == bitnum / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
+ && ((bitnum + bitsize - 1) / GET_MODE_UNIT_BITSIZE (GET_MODE (op0))
+ == bitnum / GET_MODE_UNIT_BITSIZE (GET_MODE (op0))))
{
struct expand_operand ops[3];
machine_mode outermode = GET_MODE (op0);
diff --git a/gcc/expr.c b/gcc/expr.c
index 899a42c..0f3213a 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -9018,7 +9018,7 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
little-endian, or element N-1 if big-endian. So pull the scalar
result out of that element. */
int index = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (vec_mode) - 1 : 0;
- int bitsize = GET_MODE_BITSIZE (GET_MODE_INNER (vec_mode));
+ int bitsize = GET_MODE_UNIT_BITSIZE (vec_mode);
temp = extract_bit_field (temp, bitsize, bitsize * index, unsignedp,
target, mode, mode);
gcc_assert (temp);
diff --git a/gcc/fold-const.c b/gcc/fold-const.c
index 12b15f8..b2e7014 100644
--- a/gcc/fold-const.c
+++ b/gcc/fold-const.c
@@ -9503,7 +9503,7 @@ fold_binary_loc (location_t loc,
/* Only create rotates in complete modes. Other cases are not
expanded properly. */
&& (element_precision (rtype)
- == GET_MODE_PRECISION (GET_MODE_INNER (TYPE_MODE (rtype)))))
+ == GET_MODE_UNIT_PRECISION (TYPE_MODE (rtype))))
{
tree tree01, tree11;
enum tree_code code01, code11;
diff --git a/gcc/optabs.c b/gcc/optabs.c
index 0719ba2..04bea2a 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -6591,7 +6591,7 @@ static rtx
shift_amt_for_vec_perm_mask (rtx sel)
{
unsigned int i, first, nelt = GET_MODE_NUNITS (GET_MODE (sel));
- unsigned int bitsize = GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (sel)));
+ unsigned int bitsize = GET_MODE_UNIT_BITSIZE (GET_MODE (sel));
if (GET_CODE (sel) != CONST_VECTOR)
return NULL_RTX;
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 5345989..1410013 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -5465,7 +5465,7 @@ simplify_immed_subreg (machine_mode outermode, rtx op,
{
num_elem = CONST_VECTOR_NUNITS (op);
elems = &CONST_VECTOR_ELT (op, 0);
- elem_bitsize = GET_MODE_BITSIZE (GET_MODE_INNER (innermode));
+ elem_bitsize = GET_MODE_UNIT_BITSIZE (innermode);
}
else
{
diff --git a/gcc/tree-cfg.c b/gcc/tree-cfg.c
index d97b824..e2e91cb 100644
--- a/gcc/tree-cfg.c
+++ b/gcc/tree-cfg.c
@@ -4089,10 +4089,8 @@ verify_gimple_assign_ternary (gassign *stmt)
case SAD_EXPR:
if (!useless_type_conversion_p (rhs1_type, rhs2_type)
|| !useless_type_conversion_p (lhs_type, rhs3_type)
- || 2 * GET_MODE_BITSIZE (GET_MODE_INNER
- (TYPE_MODE (TREE_TYPE (rhs1_type))))
- > GET_MODE_BITSIZE (GET_MODE_INNER
- (TYPE_MODE (TREE_TYPE (lhs_type)))))
+ || 2 * GET_MODE_UNIT_BITSIZE (TYPE_MODE (TREE_TYPE (rhs1_type)))
+ > GET_MODE_UNIT_BITSIZE (TYPE_MODE (TREE_TYPE (lhs_type))))
{
error ("type mismatch in sad expression");
debug_generic_expr (lhs_type);
diff --git a/gcc/tree-vect-patterns.c b/gcc/tree-vect-patterns.c
index f034635..ef25ba1 100644
--- a/gcc/tree-vect-patterns.c
+++ b/gcc/tree-vect-patterns.c
@@ -2645,7 +2645,6 @@ vect_recog_mixed_size_cond_pattern (vec<gimple> *stmts, tree *type_in,
tree cond_expr, then_clause, else_clause;
stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt), def_stmt_info;
tree type, vectype, comp_vectype, itype = NULL_TREE, vecitype;
- machine_mode cmpmode;
gimple pattern_stmt, def_stmt;
loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_vinfo);
@@ -2707,9 +2706,11 @@ vect_recog_mixed_size_cond_pattern (vec<gimple> *stmts, tree *type_in,
itype = orig_type1;
}
- cmpmode = GET_MODE_INNER (TYPE_MODE (comp_vectype));
- if (GET_MODE_BITSIZE (TYPE_MODE (type)) == GET_MODE_BITSIZE (cmpmode))
+ HOST_WIDE_INT cmp_mode_size
+ = GET_MODE_UNIT_BITSIZE (TYPE_MODE (comp_vectype));
+
+ if (GET_MODE_BITSIZE (TYPE_MODE (type)) == cmp_mode_size)
return NULL;
vectype = get_vectype_for_scalar_type (type);
@@ -2720,11 +2721,11 @@ vect_recog_mixed_size_cond_pattern (vec<gimple> *stmts, tree *type_in,
return NULL;
if (itype == NULL_TREE)
- itype = build_nonstandard_integer_type (GET_MODE_BITSIZE (cmpmode),
+ itype = build_nonstandard_integer_type (cmp_mode_size,
TYPE_UNSIGNED (type));
if (itype == NULL_TREE
- || GET_MODE_BITSIZE (TYPE_MODE (itype)) != GET_MODE_BITSIZE (cmpmode))
+ || GET_MODE_BITSIZE (TYPE_MODE (itype)) != cmp_mode_size)
return NULL;
vecitype = get_vectype_for_scalar_type (itype);
@@ -2734,7 +2735,7 @@ vect_recog_mixed_size_cond_pattern (vec<gimple> *stmts, tree *type_in,
if (!expand_vec_cond_expr_p (vecitype, comp_vectype))
return NULL;
- if (GET_MODE_BITSIZE (TYPE_MODE (type)) > GET_MODE_BITSIZE (cmpmode))
+ if (GET_MODE_BITSIZE (TYPE_MODE (type)) > cmp_mode_size)
{
if ((TREE_CODE (then_clause) == INTEGER_CST
&& !int_fits_type_p (then_clause, itype))
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PING][PATCH][3/N] Replace the pattern GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m)
2015-08-13 10:16 [PING][PATCH][3/N] Replace the pattern GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m) David Sherwood
@ 2015-08-13 21:31 ` Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2015-08-13 21:31 UTC (permalink / raw)
To: David Sherwood, gcc-patches
On 08/13/2015 04:12 AM, David Sherwood wrote:
> Hi,
>
> This patch follows on from
>
> [PATCH][1/N] Change GET_MODE_INNER to always return a non-void mode
>
> It is another tidy up, replacing the pattern
> GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m). Also
> replaces any calls to GET_MODE_PRECISION (GET_MODE_INNER (m)) with
> GET_MODE_UNIT_PRECISION (m).
>
> Tested:
> aarch64 and aarch64_be - no regressions in gcc testsuite
> x86_64 - bootstrap build, no testsuite regressions
> arm-none-eabi - no regressions in gcc testsuite
> Run contrib/config-list.mk - no regressions
>
> Good to go?
>
> Thanks,
> David.
>
> 2015-08-04 David Sherwood <david.sherwood@arm.com>
>
> gcc/
> * config/arm/arm.c (neon_element_bits): Replace call to
> GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m).
> * config/arm/neon.md (neon_vget_lane<mode>): Likewise.
> (neon_vget_laneu<mode>, neon_vset_lane<mode>): Likewise
> (neon_vdup_lane<mode>): Likewise.
> * config/i386/i386.c (ix86_expand_int_vcond): Likewise.
> (ix86_expand_multi_arg_builtin, ix86_expand_reduc): Likewise.
> (expand_vec_perm_palignr, ix86_expand_sse2_abs): Likewise.
> * config/rs6000/rs6000.c (rs6000_do_expand_vec_perm): Likewise.
> * config/spu/spu.c (arith_immediate_p): Likewise.
> * expmed.c (store_bit_field_1, extract_bit_field_1): Likewise.
> * expr.c (expand_expr_real_2): Likewise.
> * optabs.c (shift_amt_for_vec_perm_mask): Likewise.
> * simplify-rtx.c (simplify_immed_subreg): Likewise.
> * tree-cfg.c (verify_gimple_assign_ternary): Likewise.
> * tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern): Likewise.
> New variable.
> * fold-const.c (fold_binary_loc): Replace call to
> GET_MODE_PRECISION (GET_MODE_INNER (m)) with
> GET_MODE_UNIT_PRECISION (m).
OK.
jeff
^ permalink raw reply [flat|nested] 2+ messages in thread
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2015-08-13 10:16 [PING][PATCH][3/N] Replace the pattern GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m) David Sherwood
2015-08-13 21:31 ` Jeff Law
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