[PATCH][AArch64] Use preferred aliases for CSNEG, CSINC, CSINV

[Kyrill Tkachov <kyrylo.tkachov@arm.com>]

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Hi all,

The ARMv8-A reference manual says:
"CNEG <Wd>, <Wn>, <cond>
is equivalent to
CSNEG <Wd>, <Wn>, <Wn>, invert(<cond>)
and is the preferred disassembly when Rn == Rm && cond != '111x'."

That is, when the two input registers are the same we can use the shorter CNEG mnemonic
with the inverse condition instead of the longer CSNEG instruction. Similarly for the
CSINV and CSINC instructions, they have shorter CINV and CINC forms.
This patch adjusts the output templates to emit the preferred shorter sequences when possible.

The new mnemonics are just aliases, they map down to the same instruction in the end, so there
are no performance or behaviour implications. But it does make the assembly a bit more readable
IMO, since:
"cneg    w27, w9, le"
can be simply read as "if the condition is less or equal negate w9" instead of the previous:
"csneg    w27, w9, w9, gt" where you have to remember which of the input registers is negated.


Bootstrapped and tested on aarch64-linux-gnu.
Ok for trunk?

Thanks,
Kyrill

2015-09-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/aarch64/aarch64.md (csinc3<mode>_insn): Use CINC
     mnemonic when possible.
     (*csinv3<mode>_insn): Use CINV mnemonic when possible.
     (csneg3<mode>_insn): USE CNEG mnemonic when possible.

2015-09-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * gcc.target/aarch64/abs_1.c: Update scan-assembler checks
     to allow cneg.
     * gcc.target/aarch64/cond_op_imm_1.c: Likewise.  Likewise for cinv.
     * gcc.target/aarch64/mod_2.c: Likewise.

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commit 5f2598ffa7e0d7db92163cc5e8f4f26f7d2aff5a
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Fri Aug 21 14:51:55 2015 +0100

    [AArch64] Use preferred aliases for CSNEG, CSINC, CSINV

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 77bc7cd..2e4b26c 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3090,7 +3090,12 @@ (define_insn "csinc3<mode>_insn"
 		    (const_int 1))
 	  (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))]
   ""
-  "csinc\\t%<w>0, %<w>3, %<w>2, %M1"
+  {
+    if (rtx_equal_p (operands[2], operands[3]))
+      return "cinc\\t%<w>0, %<w>2, %m1";
+    else
+      return "csinc\\t%<w>0, %<w>3, %<w>2, %M1";
+  }
   [(set_attr "type" "csel")]
 )
 
@@ -3101,7 +3106,12 @@ (define_insn "*csinv3<mode>_insn"
 	  (not:GPI (match_operand:GPI 2 "register_operand" "r"))
 	  (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))]
   ""
-  "csinv\\t%<w>0, %<w>3, %<w>2, %M1"
+  {
+    if (rtx_equal_p (operands[2], operands[3]))
+      return "cinv\\t%<w>0, %<w>2, %m1";
+    else
+      return "csinv\\t%<w>0, %<w>3, %<w>2, %M1";
+  }
   [(set_attr "type" "csel")]
 )
 
@@ -3112,7 +3122,12 @@ (define_insn "csneg3<mode>_insn"
 	  (neg:GPI (match_operand:GPI 2 "register_operand" "r"))
 	  (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))]
   ""
-  "csneg\\t%<w>0, %<w>3, %<w>2, %M1"
+  {
+    if (rtx_equal_p (operands[2], operands[3]))
+      return "cneg\\t%<w>0, %<w>2, %m1";
+    else
+      return "csneg\\t%<w>0, %<w>3, %<w>2, %M1";
+  }
   [(set_attr "type" "csel")]
 )
 
diff --git a/gcc/testsuite/gcc.target/aarch64/abs_1.c b/gcc/testsuite/gcc.target/aarch64/abs_1.c
index 39364f4..84996a42 100644
--- a/gcc/testsuite/gcc.target/aarch64/abs_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/abs_1.c
@@ -7,14 +7,14 @@ extern void abort (void);
 long long
 abs64 (long long a)
 {
-  /* { dg-final { scan-assembler "csneg\t" } } */
+  /* { dg-final { scan-assembler "cs?neg\t" } } */
   return llabs (a);
 }
 
 long long
 abs64_in_dreg (long long a)
 {
-  /* { dg-final { scan-assembler "csneg\t" } } */
+  /* { dg-final { scan-assembler "cs?neg\t" } } */
   register long long x asm ("d8") = a;
   register long long y asm ("d9");
   asm volatile ("" : : "w" (x));
diff --git a/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c b/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c
index e93a693..a5394cc 100644
--- a/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c
@@ -12,7 +12,7 @@ foonegsi (int a)
   return a ? N : -N;
 }
 
-/* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*" } } */
+/* { dg-final { scan-assembler "cs?neg\tw\[0-9\]*.*" } } */
 
 
 int
@@ -21,7 +21,7 @@ fooinvsi (int a)
   return a ? N : ~N;
 }
 
-/* { dg-final { scan-assembler "csinv\tw\[0-9\]*.*" } } */
+/* { dg-final { scan-assembler "cs?inv\tw\[0-9\]*.*" } } */
 
 
 long long
@@ -36,7 +36,7 @@ largefooneg (long long a)
   return a ? M : -M;
 }
 
-/* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*" } } */
+/* { dg-final { scan-assembler "cs?neg\tx\[0-9\]*.*" } } */
 
 long long
 fooinvdi (long long a)
@@ -50,7 +50,7 @@ largefooinv (long long a)
   return a ? M : ~M;
 }
 
-/* { dg-final { scan-assembler "csinv\tx\[0-9\]*.*" } } */
+/* { dg-final { scan-assembler "cs?inv\tx\[0-9\]*.*" } } */
 
 
 int
diff --git a/gcc/testsuite/gcc.target/aarch64/mod_2.c b/gcc/testsuite/gcc.target/aarch64/mod_2.c
index 2645c18..a49783d 100644
--- a/gcc/testsuite/gcc.target/aarch64/mod_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/mod_2.c
@@ -3,5 +3,5 @@
 
 #include "mod_2.x"
 
-/* { dg-final { scan-assembler "csneg\t\[wx\]\[0-9\]*" } } */
+/* { dg-final { scan-assembler "cs?neg\t\[wx\]\[0-9\]*" } } */
 /* { dg-final { scan-assembler-times "and\t\[wx\]\[0-9\]*" 1 } } */