From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 71906 invoked by alias); 1 Sep 2015 10:08:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 71373 invoked by uid 89); 1 Sep 2015 10:08:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 01 Sep 2015 10:08:18 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-10-4L3qiFtURj2Q__oTG5bDEQ-1; Tue, 01 Sep 2015 11:08:12 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 1 Sep 2015 11:08:10 +0100 Message-ID: <55E5790A.2090205@arm.com> Date: Tue, 01 Sep 2015 10:08:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , James Greenhalgh , Richard Earnshaw Subject: [PATCH][AArch64] Use preferred aliases for CSNEG, CSINC, CSINV X-MC-Unique: 4L3qiFtURj2Q__oTG5bDEQ-1 Content-Type: multipart/mixed; boundary="------------040207060800000301080902" X-IsSubscribed: yes X-SW-Source: 2015-09/txt/msg00020.txt.bz2 This is a multi-part message in MIME format. --------------040207060800000301080902 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 1566 Hi all, The ARMv8-A reference manual says: "CNEG , , is equivalent to CSNEG , , , invert() and is the preferred disassembly when Rn =3D=3D Rm && cond !=3D '111x'." That is, when the two input registers are the same we can use the shorter C= NEG mnemonic with the inverse condition instead of the longer CSNEG instruction. Similar= ly for the CSINV and CSINC instructions, they have shorter CINV and CINC forms. This patch adjusts the output templates to emit the preferred shorter seque= nces when possible. The new mnemonics are just aliases, they map down to the same instruction i= n the end, so there are no performance or behaviour implications. But it does make the assembly= a bit more readable IMO, since: "cneg w27, w9, le" can be simply read as "if the condition is less or equal negate w9" instead= of the previous: "csneg w27, w9, w9, gt" where you have to remember which of the input re= gisters is negated. Bootstrapped and tested on aarch64-linux-gnu. Ok for trunk? Thanks, Kyrill 2015-09-01 Kyrylo Tkachov * config/aarch64/aarch64.md (csinc3_insn): Use CINC mnemonic when possible. (*csinv3_insn): Use CINV mnemonic when possible. (csneg3_insn): USE CNEG mnemonic when possible. 2015-09-01 Kyrylo Tkachov * gcc.target/aarch64/abs_1.c: Update scan-assembler checks to allow cneg. * gcc.target/aarch64/cond_op_imm_1.c: Likewise. Likewise for cinv. * gcc.target/aarch64/mod_2.c: Likewise. --------------040207060800000301080902 Content-Type: text/x-patch; name=aarch64-cneg.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="aarch64-cneg.patch" Content-length: 3829 commit 5f2598ffa7e0d7db92163cc5e8f4f26f7d2aff5a Author: Kyrylo Tkachov Date: Fri Aug 21 14:51:55 2015 +0100 [AArch64] Use preferred aliases for CSNEG, CSINC, CSINV diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 77bc7cd..2e4b26c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3090,7 +3090,12 @@ (define_insn "csinc3_insn" (const_int 1)) (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))] "" - "csinc\\t%0, %3, %2, %M1" + { + if (rtx_equal_p (operands[2], operands[3])) + return "cinc\\t%0, %2, %m1"; + else + return "csinc\\t%0, %3, %2, %M1"; + } [(set_attr "type" "csel")] ) =20 @@ -3101,7 +3106,12 @@ (define_insn "*csinv3_insn" (not:GPI (match_operand:GPI 2 "register_operand" "r")) (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))] "" - "csinv\\t%0, %3, %2, %M1" + { + if (rtx_equal_p (operands[2], operands[3])) + return "cinv\\t%0, %2, %m1"; + else + return "csinv\\t%0, %3, %2, %M1"; + } [(set_attr "type" "csel")] ) =20 @@ -3112,7 +3122,12 @@ (define_insn "csneg3_insn" (neg:GPI (match_operand:GPI 2 "register_operand" "r")) (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))] "" - "csneg\\t%0, %3, %2, %M1" + { + if (rtx_equal_p (operands[2], operands[3])) + return "cneg\\t%0, %2, %m1"; + else + return "csneg\\t%0, %3, %2, %M1"; + } [(set_attr "type" "csel")] ) =20 diff --git a/gcc/testsuite/gcc.target/aarch64/abs_1.c b/gcc/testsuite/gcc.t= arget/aarch64/abs_1.c index 39364f4..84996a42 100644 --- a/gcc/testsuite/gcc.target/aarch64/abs_1.c +++ b/gcc/testsuite/gcc.target/aarch64/abs_1.c @@ -7,14 +7,14 @@ extern void abort (void); long long abs64 (long long a) { - /* { dg-final { scan-assembler "csneg\t" } } */ + /* { dg-final { scan-assembler "cs?neg\t" } } */ return llabs (a); } =20 long long abs64_in_dreg (long long a) { - /* { dg-final { scan-assembler "csneg\t" } } */ + /* { dg-final { scan-assembler "cs?neg\t" } } */ register long long x asm ("d8") =3D a; register long long y asm ("d9"); asm volatile ("" : : "w" (x)); diff --git a/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c b/gcc/testsui= te/gcc.target/aarch64/cond_op_imm_1.c index e93a693..a5394cc 100644 --- a/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c +++ b/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c @@ -12,7 +12,7 @@ foonegsi (int a) return a ? N : -N; } =20 -/* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*" } } */ +/* { dg-final { scan-assembler "cs?neg\tw\[0-9\]*.*" } } */ =20 =20 int @@ -21,7 +21,7 @@ fooinvsi (int a) return a ? N : ~N; } =20 -/* { dg-final { scan-assembler "csinv\tw\[0-9\]*.*" } } */ +/* { dg-final { scan-assembler "cs?inv\tw\[0-9\]*.*" } } */ =20 =20 long long @@ -36,7 +36,7 @@ largefooneg (long long a) return a ? M : -M; } =20 -/* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*" } } */ +/* { dg-final { scan-assembler "cs?neg\tx\[0-9\]*.*" } } */ =20 long long fooinvdi (long long a) @@ -50,7 +50,7 @@ largefooinv (long long a) return a ? M : ~M; } =20 -/* { dg-final { scan-assembler "csinv\tx\[0-9\]*.*" } } */ +/* { dg-final { scan-assembler "cs?inv\tx\[0-9\]*.*" } } */ =20 =20 int diff --git a/gcc/testsuite/gcc.target/aarch64/mod_2.c b/gcc/testsuite/gcc.t= arget/aarch64/mod_2.c index 2645c18..a49783d 100644 --- a/gcc/testsuite/gcc.target/aarch64/mod_2.c +++ b/gcc/testsuite/gcc.target/aarch64/mod_2.c @@ -3,5 +3,5 @@ =20 #include "mod_2.x" =20 -/* { dg-final { scan-assembler "csneg\t\[wx\]\[0-9\]*" } } */ +/* { dg-final { scan-assembler "cs?neg\t\[wx\]\[0-9\]*" } } */ /* { dg-final { scan-assembler-times "and\t\[wx\]\[0-9\]*" 1 } } */ --------------040207060800000301080902--