From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12181 invoked by alias); 17 Sep 2015 17:54:32 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 12169 invoked by uid 89); 17 Sep 2015 17:54:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.7 required=5.0 tests=AWL,BAYES_50,KAM_LAZY_DOMAIN_SECURITY,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 17 Sep 2015 17:54:29 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A993D59E for ; Thu, 17 Sep 2015 10:54:28 -0700 (PDT) Received: from e108033-lin.cambridge.arm.com (e108033-lin.cambridge.arm.com [10.2.206.52]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5493E3F23A for ; Thu, 17 Sep 2015 10:54:27 -0700 (PDT) To: gcc-patches From: Matthew Wahab Subject: [ARM] Add ARMv8.1 command line options. Message-ID: <55FAFE51.5080004@foss.arm.com> Date: Thu, 17 Sep 2015 18:04:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------080501040407010500000207" X-IsSubscribed: yes X-SW-Source: 2015-09/txt/msg01322.txt.bz2 This is a multi-part message in MIME format. --------------080501040407010500000207 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 1150 Hello, ARMv8.1 is a set of architectural extensions to ARMv8. Support has been enabled in binutils for ARMv8.1 for the architechure, using the name "armv8.1-a". This patch adds support to gcc for specifying an ARMv8.1 architecture using options "-march=armv8.1-a" and "-march=armv8.1-a+crc". It also adds the FPU options "-mfpu=neon-fp-armv8.1" and "-mpu=crypto-neon-fp-armv8.1", to specify the ARMv8.1 Adv.SIMD instruction set. The changes set the apropriate architecture and fpu options for binutils but don't otherwise change the code generated by gcc. Tested for arm-none-linux-gnueabihf with native bootstrap and make check. Ok for trunk? Matthew 2015-09-17 Matthew Wahab * config/arm/arm-arches.def: Add "armv8.1-a" and "armv8.1-a+crc". * config/arm/arm-fpus.def: Add "neon-fp-armv8.1" and "crypto-neon-fp-armv8.1". * config/arm/arm-protos.h (FL2_ARCH8_1): New. (FL2_FOR_ARCH8_1A): New. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm.h (FPU_FL_RDMA): New. * doc/invoke.texi (ARM -march): Add "armv8.1-a" and "armv8.1-a+crc". (ARM -mfpu): Add "neon-fp-armv8.1" and "crypto-neon-fp-armv8.1". --------------080501040407010500000207 Content-Type: text/x-patch; name="aarch32_armv8_1_options.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="aarch32_armv8_1_options.patch" Content-length: 4640 diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def index ddf6c3c..4cf71fd 100644 --- a/gcc/config/arm/arm-arches.def +++ b/gcc/config/arm/arm-arches.def @@ -57,6 +57,8 @@ ARM_ARCH("armv7-m", cortexm3, 7M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ ARM_ARCH("armv7e-m", cortexm4, 7EM, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7EM)) ARM_ARCH("armv8-a", cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH8A)) ARM_ARCH("armv8-a+crc",cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A)) +ARM_ARCH("armv8.1-a", cortexa53, 8A, ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A)) +ARM_ARCH("armv8.1-a+crc",cortexa53, 8A, ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A)) ARM_ARCH("iwmmxt", iwmmxt, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT)) ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)) diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def index efd5896..065fb3d9 100644 --- a/gcc/config/arm/arm-fpus.def +++ b/gcc/config/arm/arm-fpus.def @@ -44,5 +44,9 @@ ARM_FPU("fp-armv8", ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_FP16) ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16) ARM_FPU("crypto-neon-fp-armv8", ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO) +ARM_FPU("neon-fp-armv8.1", + ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_RDMA) +ARM_FPU("crypto-neon-fp-armv8.1", + ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_RDMA | FPU_FL_CRYPTO) /* Compatibility aliases. */ ARM_FPU("vfp3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NONE) diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 8df312f..e60ad4c 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -387,6 +387,8 @@ extern bool arm_is_constant_pool_ref (rtx); #define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */ #define FL_ARCH6KZ (1 << 31) /* ARMv6KZ architecture. */ +#define FL2_ARCH8_1 (1 << 0) /* Architecture 8.1. */ + /* Flags that only effect tuning, not available instructions. */ #define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ | FL_CO_PROC) @@ -415,6 +417,7 @@ extern bool arm_is_constant_pool_ref (rtx); #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV) #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) #define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8) +#define FL2_FOR_ARCH8_1A FL2_ARCH8_1 /* There are too many feature bits to fit in a single word so the set of cpu and fpu capabilities is a structure. A feature set is created and manipulated diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index f7a9d63..274bc46 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -336,6 +336,7 @@ typedef unsigned long arm_fpu_feature_set; #define FPU_FL_NEON (1 << 0) /* NEON instructions. */ #define FPU_FL_FP16 (1 << 1) /* Half-precision. */ #define FPU_FL_CRYPTO (1 << 2) /* Crypto extensions. */ +#define FPU_FL_RDMA (1 << 3) /* ARMv8.1 extensions. */ /* Which floating point model to use. */ enum arm_fp_model diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 99c9685..9f49189 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13267,8 +13267,8 @@ of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, @samp{armv6}, @samp{armv6j}, @samp{armv6t2}, @samp{armv6z}, @samp{armv6kz}, @samp{armv6-m}, @samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, @samp{armv7e-m}, -@samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, -@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. +@samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a}, +@samp{armv8.1-a+crc}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. @option{-march=armv7ve} is the armv7-a architecture with virtualization extensions. @@ -13370,7 +13370,8 @@ available on the target. Permissible names are: @samp{vfp}, @samp{vfpv3}, @samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4}, @samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4}, @samp{fpv5-d16}, @samp{fpv5-sp-d16}, -@samp{fp-armv8}, @samp{neon-fp-armv8}, and @samp{crypto-neon-fp-armv8}. +@samp{fp-armv8}, @samp{neon-fp-armv8}, @samp{crypto-neon-fp-armv8}, +@samp{neon-fp-armv8.1} and @samp{crypto-neon-fp-armv8.1}. If @option{-msoft-float} is specified this specifies the format of floating-point values. --------------080501040407010500000207--