From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 55388 invoked by alias); 29 Aug 2019 15:39:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 55380 invoked by uid 89); 29 Aug 2019 15:39:02 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-17.5 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3 autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 29 Aug 2019 15:39:00 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D4AA828; Thu, 29 Aug 2019 08:38:58 -0700 (PDT) Received: from [10.2.206.47] (e120808-lin.cambridge.arm.com [10.2.206.47]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7F7F13F718; Thu, 29 Aug 2019 08:38:58 -0700 (PDT) Subject: Re: [ARM/FDPIC v5 12/21] [ARM] FDPIC: Restore r9 after we call __aeabi_read_tp To: Christophe Lyon , "gcc-patches@gcc.gnu.org" References: <20190515124006.25840-1-christophe.lyon@st.com> <20190515124006.25840-13-christophe.lyon@st.com> From: Kyrill Tkachov Message-ID: <55f718b4-147a-af5a-3e2e-4f8965b4a980@foss.arm.com> Date: Thu, 29 Aug 2019 15:44:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 MIME-Version: 1.0 In-Reply-To: <20190515124006.25840-13-christophe.lyon@st.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2019-08/txt/msg02000.txt.bz2 Hi Christophe, On 5/15/19 1:39 PM, Christophe Lyon wrote: > We call __aeabi_read_tp() to get the thread pointer. Since this is a > function call, we have to restore the FDPIC register afterwards. > > 2019-XX-XX  Christophe Lyon  >         Mickaël Guêné > >         gcc/ >         * config/arm/arm.c (arm_load_tp): Add FDPIC support. >         * config/arm/arm.md (load_tp_soft_fdpic): New pattern. >         (load_tp_soft): Disable in FDPIC mode. > > Change-Id: I1f6dfaee6260ecb453270f4971b3c5124317a186 > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index 5fc7a20..26f29c7 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -8732,7 +8732,25 @@ arm_load_tp (rtx target) > >        rtx tmp; > > -      emit_insn (gen_load_tp_soft ()); > +      if (TARGET_FDPIC) > +       { > +         rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3)); > +         rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); > +         rtx initial_fdpic_reg = get_hard_reg_initial_val (Pmode, > FDPIC_REGNUM); > + > +         emit_insn (gen_load_tp_soft_fdpic ()); > + > +         /* Restore r9.  */ > +         XVECEXP (par, 0, 0) = gen_rtx_UNSPEC (VOIDmode, > +                                               gen_rtvec (2, fdpic_reg, > + initial_fdpic_reg), > + UNSPEC_PIC_RESTORE); > +         XVECEXP (par, 0, 1) = gen_rtx_USE (VOIDmode, initial_fdpic_reg); > +         XVECEXP (par, 0, 2) = gen_rtx_CLOBBER (VOIDmode, fdpic_reg); > +         emit_insn (par); > +       } > +      else > +       emit_insn (gen_load_tp_soft ()); > >        tmp = gen_rtx_REG (SImode, R0_REGNUM); >        emit_move_insn (target, tmp); > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index 9036255..0edcb1d 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -11759,12 +11759,25 @@ >  ) > >  ;; Doesn't clobber R1-R3.  Must use r0 for the first operand. > +(define_insn "load_tp_soft_fdpic" > +  [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) > +   (clobber (reg:SI 9)) Use FDPIC_REGNUM here (does it need to be declared at the top of arm.md for it to work?) Otherwise this is ok. Thanks, Kyrill > +   (clobber (reg:SI LR_REGNUM)) > +   (clobber (reg:SI IP_REGNUM)) > +   (clobber (reg:CC CC_REGNUM))] > +  "TARGET_SOFT_TP && TARGET_FDPIC" > +  "bl\\t__aeabi_read_tp\\t@ load_tp_soft" > +  [(set_attr "conds" "clob") > +   (set_attr "type" "branch")] > +) > + > +;; Doesn't clobber R1-R3.  Must use r0 for the first operand. >  (define_insn "load_tp_soft" >    [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) >     (clobber (reg:SI LR_REGNUM)) >     (clobber (reg:SI IP_REGNUM)) >     (clobber (reg:CC CC_REGNUM))] > -  "TARGET_SOFT_TP" > +  "TARGET_SOFT_TP && !TARGET_FDPIC" >    "bl\\t__aeabi_read_tp\\t@ load_tp_soft" >    [(set_attr "conds" "clob") >     (set_attr "type" "branch")] > -- > 2.6.3 >