From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 60011 invoked by alias); 29 Sep 2015 08:03:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 59981 invoked by uid 89); 29 Sep 2015 08:03:23 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 29 Sep 2015 08:03:22 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-12-iIXkxlbXRVm3-2R1aBZ5eg-1; Tue, 29 Sep 2015 09:03:16 +0100 Received: from [10.2.207.27] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 29 Sep 2015 09:03:16 +0100 Subject: Re: [PATCH][AArch64] Add separate insn sched class for vector LDP & STP To: Evandro Menezes , "gcc-patches@gcc.gnu.org" References: <5609D2D7.4080004@samsung.com> Cc: James Greenhalgh , Kyrylo Tkachov , Ramana Radhakrishnan From: Marcus Shawcroft Message-ID: <560A45D6.8060502@arm.com> Date: Tue, 29 Sep 2015 09:01:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <5609D2D7.4080004@samsung.com> X-MC-Unique: iIXkxlbXRVm3-2R1aBZ5eg-1 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-SW-Source: 2015-09/txt/msg02171.txt.bz2 On 29/09/15 00:52, Evandro Menezes wrote: > In some micro-architectures the insns to load or store pairs of vector > registers are implemented rather differently from those affecting lanes > in vector registers. Then, it's important that such insns be described > likewise differently in the scheduling model. > > This patch adds the insn types neon_ldp{,_q} and neon_stp{,_q} apart > from the current neon_load2_2reg_q and neon_store2_2reg_q types, > respectively. > Hi, The AArch64 part of this is OK. Please wait for Kyrill or Ramana to=20 comment on ARM side. Cheers /Marcus > Thank you, > > -- Evandro Menezes > > > 0001-AArch64-Add-separate-insn-sched-class-for-vector-LDP.patch > > > From 340249dcd2af8dfce486cb4f62d4eaf285c6a799 Mon Sep 17 00:00:00 2001 > From: Evandro Menezes > Date: Mon, 28 Sep 2015 15:00:00 -0500 > Subject: [PATCH] [AArch64] Add separate insn sched class for vector LDP &= STP > > 2015-09-28 Evandro Menezes > > gcc/ > * config/arm/types.md (neon_ldp, neon_ldp_q, neon_stp, neon_stp_q): > add new insn types for vector load and store pairs. s/add/Add/ and likewise the rest of the changelog comments. > * config/arm/cortex-a53.md (cortex_a53_f_load_2reg): add insn > types "neon_ldp{,_q}". > * config/arm/cortex-a57.md (neon_load_c): add insn types > "neon_ldp{,_q}". > (neon_store_complex): add insn types "neon_stp{,_q}". > * config/aarch64/aarch64-simd.md (aarch64_be_movoi): add insn types > "neon_{ldp,stp}_q".