From 429b1d70a7eca76c96250fec6ec5269a7a661a4c Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Mon, 19 Oct 2015 18:31:48 -0500 Subject: [PATCH] [AArch64] Replace insn to zero up DF register gcc/ * config/aarch64/aarch64.md (*movdf_aarch64): Add "movi %d0, #0" to zero up DF register. --- gcc/config/aarch64/aarch64.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 5b7f2fd..5f00686 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1156,21 +1156,22 @@ ) (define_insn "*movdf_aarch64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") - (match_operand:DF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=w,?r,w,w,w ,w,m,r,m ,r") + (match_operand:DF 1 "general_operand" "?r, w,w,Y,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], DFmode) || aarch64_reg_or_fp_zero (operands[1], DFmode))" "@ fmov\\t%d0, %x1 fmov\\t%x0, %d1 fmov\\t%d0, %d1 + movi\\t%d0, #0 fmov\\t%d0, %1 ldr\\t%d0, %1 str\\t%d1, %0 ldr\\t%x0, %1 str\\t%x1, %0 mov\\t%x0, %x1" - [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\ + [(set_attr "type" "f_mcr,f_mrc,fmov,neon_move,fconstd,\ f_loadd,f_stored,load1,store1,mov_reg")] ) -- 2.1.0.243.g30d45f7