From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27678 invoked by alias); 20 Oct 2015 16:26:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 27667 invoked by uid 89); 20 Oct 2015 16:26:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 20 Oct 2015 16:26:21 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-16-34s87fSSRMuG8v4SwbjkpA-1; Tue, 20 Oct 2015 17:26:15 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 20 Oct 2015 17:26:15 +0100 Message-ID: <56266B27.3040709@arm.com> Date: Tue, 20 Oct 2015 16:28:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Marcus Shawcroft CC: GCC Patches , Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: Re: [PATCH][AArch64] Add support for 64-bit vector-mode ldp/stp References: <5620F47B.9010107@arm.com> In-Reply-To: X-MC-Unique: 34s87fSSRMuG8v4SwbjkpA-1 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-10/txt/msg01912.txt.bz2 Hi Marcus, On 20/10/15 17:05, Marcus Shawcroft wrote: > On 16 October 2015 at 13:58, Kyrill Tkachov wrot= e: >> Hi all, >> >> We already support load/store-pair operations on the D-registers when th= ey >> contain an FP value, but the peepholes/sched-fusion machinery that >> do all the hard work currently ignore 64-bit vector modes. >> >> This patch adds support for fusing loads/stores of 64-bit vector operands >> into ldp and stp instructions. >> I've seen this trigger a few times in SPEC2006. Not too many times, but = the >> times it did trigger the code seemed objectively better >> i.e. long sequences of ldr and str instructions essentially halved in si= ze. >> >> Bootstrapped and tested on aarch64-none-linux-gnu. >> >> Ok for trunk? >> >> Thanks, >> Kyrill >> >> 2015-10-16 Kyrylo Tkachov >> >> * config/aarch64/aarch64.c (aarch64_mode_valid_for_sched_fusion_p): > We have several different flavours of fusion in the backend, this one > is specifically load/stores, perhaps making that clear in the name of > this predicate will avoid confusion further down the line? Thanks for the review, This particular type of fusion is called sched_fusion in various places in the compiler and its implementation in aarch64 is only for load/store merging (indeed, the only usage of sched_fusion currently is to merge loads/stores in arm and aarch64). So, I think that sched_fusion in the name already conveys the information that it's the ldp/stp one rather than macro fusion. In fact, there is a macro fusion of ADRP and an LDR instruction, so having sched_fusion in the name is actually a better differentiator than mentioning loads/stores as both types of fusion deal with loads in some way. Is it ok to keep the name as is? Thanks, Kyrill > >> New function. >> (fusion_load_store): Use it. >> * config/aarch64/aarch64-ldpstp.md: Add new peephole2s for >> ldp and stp in VD modes. >> * config/aarch64/aarch64-simd.md (load_pair, VD): New pattern. >> (store_pair, VD): Likewise. >> >> 2015-10-16 Kyrylo Tkachov >> >> * gcc.target/aarch64/stp_vec_64_1.c: New test. >> * gcc.target/aarch64/ldp_vec_64_1.c: New test. > Otherwise OK /Marcus >