From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18292 invoked by alias); 28 Oct 2015 10:07:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 18267 invoked by uid 89); 28 Oct 2015 10:07:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 28 Oct 2015 10:07:05 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-3-UD7_b6laTx6HdImd8-H03g-1; Wed, 28 Oct 2015 10:07:00 +0000 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Oct 2015 10:07:00 +0000 Message-ID: <56309E44.8070100@arm.com> Date: Wed, 28 Oct 2015 10:08:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Ramana Radhakrishnan , Richard Earnshaw , James Greenhalgh Subject: [PATCH][ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwarding check X-MC-Unique: UD7_b6laTx6HdImd8-H03g-1 Content-Type: multipart/mixed; boundary="------------030201020502070005060303" X-IsSubscribed: yes X-SW-Source: 2015-10/txt/msg03010.txt.bz2 This is a multi-part message in MIME format. --------------030201020502070005060303 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 1397 Hi all, This RTL checking error occurs on aarch64 in aarch_accumulator_forwarding w= hen processing an msubsi insn with subregs: (insn 15 14 16 3 (set (reg/v:SI 78 [ i ]) (minus:SI (subreg:SI (reg/v:DI 76 [ aul ]) 0) (mult:SI (subreg:SI (reg:DI 83) 0) (subreg:SI (reg:DI 75 [ _20 ]) 0)))) schedice.c:10 357 {*m= subsi} The register_operand predicate for that pattern allows subregs (I think cor= rectly). The code in aarch_accumulator_forwarding doesn't take that into account and= ends up taking a REGNO of a SUBREG, causing a checking error. This patch fixes that by stripping the subregs off the accumulator rtx befo= re checking that the inner expression is a REG and taking its REGNO. The testcase now works fine with an aarch64-none-elf toolchain configure fo= r RTL checking. The testcase is taken verbatim from the BZ entry for PR 68088. Since this function is shared between arm and aarch64 I've bootstrapped and= tested it on both and I'll need ok's for both ports. Ok for trunk? Thanks, Kyrill 2015-10-28 Kyrylo Tkachov PR target/68088 * config/arm/aarch-common.c (aarch_strip_subreg): New function. (aarch_accumulator_forwarding): Strip subregs from accumulator rtx when appropriate. 2015-10-28 Kyrylo Tkachov * gcc.target/aarch64/pr68088_1.c: New test. --------------030201020502070005060303 Content-Type: text/x-patch; name=aarch64-accum-rtl-check-fix.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="aarch64-accum-rtl-check-fix.patch" Content-length: 2753 commit 7ce1b9ec8b8486cab34071a9c120db13e7c3b96a Author: Kyrylo Tkachov Date: Tue Oct 27 11:42:19 2015 +0000 [ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accu= mulator forwarding check diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c index a940a02..2a21c4e 100644 --- a/gcc/config/arm/aarch-common.c +++ b/gcc/config/arm/aarch-common.c @@ -389,6 +389,15 @@ arm_mac_accumulator_is_result (rtx producer, rtx consu= mer) && !reg_overlap_mentioned_p (result, op1)); } =20 +/* If X is a subreg return the value it contains, otherwise + return X unchanged. */ + +static rtx +aarch_strip_subreg (rtx x) +{ + return GET_CODE (x) =3D=3D SUBREG ? SUBREG_REG (x) : x; +} + /* Return non-zero if the destination of PRODUCER feeds the accumulator operand of an MLA-like operation. */ =20 @@ -420,14 +429,14 @@ aarch_accumulator_forwarding (rtx_insn *producer, rtx= _insn *consumer) case PLUS: /* Possibly an MADD. */ if (GET_CODE (XEXP (mla, 0)) =3D=3D MULT) - accumulator =3D XEXP (mla, 1); + accumulator =3D aarch_strip_subreg (XEXP (mla, 1)); else return 0; break; case MINUS: /* Possibly an MSUB. */ if (GET_CODE (XEXP (mla, 1)) =3D=3D MULT) - accumulator =3D XEXP (mla, 0); + accumulator =3D aarch_strip_subreg (XEXP (mla, 0)); else return 0; break; @@ -441,7 +450,7 @@ aarch_accumulator_forwarding (rtx_insn *producer, rtx_i= nsn *consumer) =20 { /* FMADD/FMSUB. */ - accumulator =3D XEXP (mla, 2); + accumulator =3D aarch_strip_subreg (XEXP (mla, 2)); } else if (REG_P (XEXP (mla, 1)) && GET_CODE (XEXP (mla, 2)) =3D=3D NEG @@ -449,7 +458,7 @@ aarch_accumulator_forwarding (rtx_insn *producer, rtx_i= nsn *consumer) || GET_CODE (XEXP (mla, 0)) =3D=3D NEG)) { /* FNMADD/FNMSUB. */ - accumulator =3D XEXP (XEXP (mla, 2), 0); + accumulator =3D aarch_strip_subreg (XEXP (XEXP (mla, 2), 0)); } else return 0; @@ -460,6 +469,9 @@ aarch_accumulator_forwarding (rtx_insn *producer, rtx_i= nsn *consumer) return 0; } =20 + if (!REG_P (accumulator)) + return 0; + return (REGNO (dest) =3D=3D REGNO (accumulator)); } =20 diff --git a/gcc/testsuite/gcc.target/aarch64/pr68088_1.c b/gcc/testsuite/g= cc.target/aarch64/pr68088_1.c new file mode 100644 index 0000000..49c6aa1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr68088_1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void bar (unsigned long); + +void +foo (unsigned long aul, unsigned m, unsigned i) +{ + while (1) + { + aul +=3D i; + i =3D aul % m; + bar (aul); + } +} --------------030201020502070005060303--