[PATCH] S/390: Clobber r1 in patterns resulting in pfpo instruction.

[PATCH] S/390: Clobber r1 in patterns resulting in pfpo instruction.

[Dominik Vogt]

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The attached patch fixes the S/390 patterns using the "pfpo"
instruction in s390.md.  The instructions clobber r1, but the
patterns did not reflect that.

Ciao

Dominik ^_^  ^_^

-- 

Dominik Vogt
IBM Germany

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gcc/ChangeLog

	* config/s390/s390.md (GPR1_REGNUM): New constant.
	("*trunc<BFP:mode><DFP_ALL:mode>2")
	("*trunc<DFP_ALL:mode><BFP:mode>2")
	("trunc<BFP:mode><DFP_ALL:mode>2")
	("trunc<DFP_ALL:mode><BFP:mode>2")
	("*extend<BFP:mode><DFP_ALL:mode>2")
	("*extend<DFP_ALL:mode><BFP:mode>2")
	("extend<BFP:mode><DFP_ALL:mode>2")
	("extend<DFP_ALL:mode><BFP:mode>2"): Clobber r1.

gcc/testsuite/ChangeLog

	* gcc.target/s390/pfpo.c: New test.

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From c7ddb09c08d4d3e4d394588aa8aa43331582db86 Mon Sep 17 00:00:00 2001
From: Dominik Vogt <vogt@linux.vnet.ibm.com>
Date: Tue, 17 Nov 2015 20:10:04 +0100
Subject: [PATCH] S/390: Clobber r1 in patterns resulting in pfpo
 instruction.

---
 gcc/config/s390/s390.md              | 25 +++++++++++++++++--------
 gcc/testsuite/gcc.target/s390/pfpo.c | 21 +++++++++++++++++++++
 2 files changed, 38 insertions(+), 8 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/s390/pfpo.c

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index ea65c74..f2bb24c 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -301,6 +301,7 @@
   [
    ; General purpose registers
    (GPR0_REGNUM                  0)
+   (GPR1_REGNUM                  1)
    ; Floating point registers.
    (FPR0_REGNUM                 16)
    (FPR1_REGNUM                 20)
@@ -4895,7 +4896,8 @@
   [(set (reg:DFP_ALL FPR0_REGNUM)
         (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
    (use (reg:SI GPR0_REGNUM))
-   (clobber (reg:CC CC_REGNUM))]
+   (clobber (reg:CC CC_REGNUM))
+   (clobber (reg:SI GPR1_REGNUM))]
   "TARGET_HARD_DFP"
   "pfpo")
 
@@ -4903,7 +4905,8 @@
   [(set (reg:BFP FPR0_REGNUM)
         (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
    (use (reg:SI GPR0_REGNUM))
-   (clobber (reg:CC CC_REGNUM))]
+   (clobber (reg:CC CC_REGNUM))
+   (clobber (reg:SI GPR1_REGNUM))]
   "TARGET_HARD_DFP"
   "pfpo")
 
@@ -4914,7 +4917,8 @@
     [(set (reg:DFP_ALL FPR0_REGNUM)
           (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
      (use (reg:SI GPR0_REGNUM))
-     (clobber (reg:CC CC_REGNUM))])
+     (clobber (reg:CC CC_REGNUM))
+     (clobber (reg:SI GPR1_REGNUM))])
    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
         (reg:DFP_ALL FPR0_REGNUM))]
   "TARGET_HARD_DFP
@@ -4936,7 +4940,8 @@
    (parallel
     [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
      (use (reg:SI GPR0_REGNUM))
-     (clobber (reg:CC CC_REGNUM))])
+     (clobber (reg:CC CC_REGNUM))
+     (clobber (reg:SI GPR1_REGNUM))])
    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
   "TARGET_HARD_DFP
    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
@@ -4957,14 +4962,16 @@
 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
   [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
    (use (reg:SI GPR0_REGNUM))
-   (clobber (reg:CC CC_REGNUM))]
+   (clobber (reg:CC CC_REGNUM))
+   (clobber (reg:SI GPR1_REGNUM))]
   "TARGET_HARD_DFP"
   "pfpo")
 
 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
   [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
    (use (reg:SI GPR0_REGNUM))
-   (clobber (reg:CC CC_REGNUM))]
+   (clobber (reg:CC CC_REGNUM))
+   (clobber (reg:SI GPR1_REGNUM))]
   "TARGET_HARD_DFP"
   "pfpo")
 
@@ -4975,7 +4982,8 @@
     [(set (reg:DFP_ALL FPR0_REGNUM)
           (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
      (use (reg:SI GPR0_REGNUM))
-     (clobber (reg:CC CC_REGNUM))])
+     (clobber (reg:CC CC_REGNUM))
+     (clobber (reg:SI GPR1_REGNUM))])
    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
         (reg:DFP_ALL FPR0_REGNUM))]
   "TARGET_HARD_DFP
@@ -4997,7 +5005,8 @@
    (parallel
     [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
      (use (reg:SI GPR0_REGNUM))
-     (clobber (reg:CC CC_REGNUM))])
+     (clobber (reg:CC CC_REGNUM))
+     (clobber (reg:SI GPR1_REGNUM))])
    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
   "TARGET_HARD_DFP
    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
diff --git a/gcc/testsuite/gcc.target/s390/pfpo.c b/gcc/testsuite/gcc.target/s390/pfpo.c
new file mode 100644
index 0000000..ff8b09a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/pfpo.c
@@ -0,0 +1,21 @@
+/* The pfpo instruction generated by this code clobbers the r1 register while
+   it was still in use.  */
+
+/* { dg-do run } */
+/* { dg-options "-O0 -march=z10" } */
+
+int foo(int x)
+{
+  return x;
+}
+
+int bar(int i, float f)
+{
+  return i;
+}
+
+int main()
+{
+  _Decimal32 d = 7;
+  return bar(foo(0x10203040), (float)d) == 0x10203040 ? 0 : 1;
+}
-- 
2.3.0

Re: [PATCH] S/390: Clobber r1 in patterns resulting in pfpo instruction.

[Andreas Krebbel]

On 11/18/2015 03:35 PM, Dominik Vogt wrote:
> The attached patch fixes the S/390 patterns using the "pfpo"
> instruction in s390.md.  The instructions clobber r1, but the
> patterns did not reflect that.

Good catch!

Your testcase requires -mzarch in the options to enable pfpo with -m31 as well.  I've committed the
patch with that change.

Thanks!

Bye,

-Andreas-