From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 94421 invoked by alias); 24 Nov 2015 09:24:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 94404 invoked by uid 89); 24 Nov 2015 09:24:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pa0-f51.google.com Received: from mail-pa0-f51.google.com (HELO mail-pa0-f51.google.com) (209.85.220.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 24 Nov 2015 09:24:38 +0000 Received: by pabfh17 with SMTP id fh17so17348308pab.0 for ; Tue, 24 Nov 2015 01:24:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:message-id:date:from:organization:user-agent :mime-version:to:cc:subject:content-type; bh=pk+k+GNQ952CqijxcFwWq8AKx+cWKgU+6K68UnPWV84=; b=l4UEF649IRzxtbyuE1RADf9zJjhhlgzRXLAqlOXsifOzkzYGO3aE1p8gvpuAdD3LZy SroD5C3zMqqqHSmiU9CoZtyPDwvADExGNxUUo4IG4tIsOkfau2lfBb+6yzgmWDlhUf6T q/Xp7qsw8CmQJbmGBTBLtpYzdT8ylnPx99nl/ArdSsog4NLGuNAyUrJ1PvY6onfC0fE8 eDif3dMQtjrEVKVT6CSiDH06sQfGoe6IDhyjBRwmItOyhGctIWcDwvATHfRp8i0OMPj7 KTpp/ntzhJtlxkB8P63oxR2hj5ja80ljU3JIHAD3BJo6D7zq49WCRzmrxc1Nf43zNjCt 4CSg== X-Gm-Message-State: ALoCoQk+LpgFITpeaRHCTiI7TT9vFjXrJRNTEzZLona6OeYMXJDwnkUUZlGs2SFWJ+W0zaZFZFQ2 X-Received: by 10.66.102.101 with SMTP id fn5mr41311248pab.66.1448357076490; Tue, 24 Nov 2015 01:24:36 -0800 (PST) Received: from [192.168.1.14] (ip70-176-202-128.ph.ph.cox.net. [70.176.202.128]) by smtp.googlemail.com with ESMTPSA id 71sm13100989pfj.28.2015.11.24.01.24.35 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 24 Nov 2015 01:24:35 -0800 (PST) Message-ID: <56542CCE.2080304@linaro.org> Date: Tue, 24 Nov 2015 09:36:00 -0000 From: Michael Collison User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 To: GCC Patches CC: James Greenhalgh Subject: Re: [Aarch64] Use vector wide add for mixed-mode adds Content-Type: multipart/mixed; boundary="------------010609060208060209030009" X-SW-Source: 2015-11/txt/msg02851.txt.bz2 This is a multi-part message in MIME format. --------------010609060208060209030009 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 869 This is a followup patch which addresses formatting comments posted here: https://gcc.gnu.org/ml/gcc-patches/2015-11/msg02611.html 2015-11-24 Michael Collison * config/aarch64/aarch64-simd.md (widen_ssum, widen_usum) (aarch64_w_internal): New patterns * config/aarch64/iterators.md (Vhalf, VDBLW): New mode attributes. * gcc.target/aarch64/saddw-1.c: New test. * gcc.target/aarch64/saddw-2.c: New test. * gcc.target/aarch64/uaddw-1.c: New test. * gcc.target/aarch64/uaddw-2.c: New test. * gcc.target/aarch64/uaddw-3.c: New test. * lib/target-support.exp (check_effective_target_vect_widen_sum_hi_to_si_pattern): Add aarch64 to list of support targets. Okay to commit? -- Michael Collison Linaro Toolchain Working Group michael.collison@linaro.org --------------010609060208060209030009 Content-Type: text/x-patch; name="bugzilla_67322_nov242015.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="bugzilla_67322_nov242015.patch" Content-length: 7628 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 3fa23b3..79be6be 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2777,6 +2777,62 @@ ;; w. +(define_expand "widen_ssum3" + [(set (match_operand: 0 "register_operand" "") + (plus: (sign_extend: + (match_operand:VQW 1 "register_operand" "")) + (match_operand: 2 "register_operand" "")))] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (mode, false); + rtx temp = gen_reg_rtx (GET_MODE (operands[0])); + + emit_insn (gen_aarch64_saddw_internal (temp, operands[2], + operands[1], p)); + emit_insn (gen_aarch64_saddw2 (operands[0], temp, operands[1])); + DONE; + } +) + +(define_expand "widen_ssum3" + [(set (match_operand: 0 "register_operand" "") + (plus: (sign_extend: + (match_operand:VD_BHSI 1 "register_operand" "")) + (match_operand: 2 "register_operand" "")))] + "TARGET_SIMD" +{ + emit_insn (gen_aarch64_saddw (operands[0], operands[2], operands[1])); + DONE; +}) + +(define_expand "widen_usum3" + [(set (match_operand: 0 "register_operand" "") + (plus: (zero_extend: + (match_operand:VQW 1 "register_operand" "")) + (match_operand: 2 "register_operand" "")))] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (mode, false); + rtx temp = gen_reg_rtx (GET_MODE (operands[0])); + + emit_insn (gen_aarch64_uaddw_internal (temp, operands[2], + operands[1], p)); + emit_insn (gen_aarch64_uaddw2 (operands[0], temp, operands[1])); + DONE; + } +) + +(define_expand "widen_usum3" + [(set (match_operand: 0 "register_operand" "") + (plus: (zero_extend: + (match_operand:VD_BHSI 1 "register_operand" "")) + (match_operand: 2 "register_operand" "")))] + "TARGET_SIMD" +{ + emit_insn (gen_aarch64_uaddw (operands[0], operands[2], operands[1])); + DONE; +}) + (define_insn "aarch64_w" [(set (match_operand: 0 "register_operand" "=w") (ADDSUB: (match_operand: 1 "register_operand" "w") @@ -2787,6 +2843,18 @@ [(set_attr "type" "neon__widen")] ) +(define_insn "aarch64_w_internal" + [(set (match_operand: 0 "register_operand" "=w") + (ADDSUB: (match_operand: 1 "register_operand" "w") + (ANY_EXTEND: + (vec_select: + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_lo_half" "")))))] + "TARGET_SIMD" + "w\\t%0., %1., %2." + [(set_attr "type" "neon__widen")] +) + (define_insn "aarch64_w2_internal" [(set (match_operand: 0 "register_operand" "=w") (ADDSUB: (match_operand: 1 "register_operand" "w") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index c2eb7de..02e930b 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -479,6 +479,13 @@ (V4SF "V2SF") (V4HF "V2HF") (V8HF "V4HF") (V2DF "DF")]) +;; Half modes of all vector modes, in lower-case. +(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi") + (V4HI "v2hi") (V8HI "v4hi") + (V2SI "si") (V4SI "v2si") + (V2DI "di") (V2SF "sf") + (V4SF "v2sf") (V2DF "df")]) + ;; Double modes of vector modes. (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") (V4HF "V8HF") @@ -496,6 +503,11 @@ (SI "v2si") (DI "v2di") (DF "v2df")]) +;; Modes with double-width elements. +(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI") + (V4HI "V2SI") (V8HI "V4SI") + (V2SI "DI") (V4SI "V2DI")]) + ;; Narrowed modes for VDN. (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")]) diff --git a/gcc/testsuite/gcc.target/aarch64/saddw-1.c b/gcc/testsuite/gcc.target/aarch64/saddw-1.c new file mode 100644 index 0000000..7500fb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/saddw-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int +t6(int len, void * dummy, short * __restrict x) +{ + len = len & ~31; + int result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "saddw" } } */ +/* { dg-final { scan-assembler "saddw2" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/saddw-2.c b/gcc/testsuite/gcc.target/aarch64/saddw-2.c new file mode 100644 index 0000000..5d9c8d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/saddw-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int +t6(int len, void * dummy, int * __restrict x) +{ + len = len & ~31; + long long result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "saddw" } } */ +/* { dg-final { scan-assembler "saddw2" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/uaddw-1.c b/gcc/testsuite/gcc.target/aarch64/uaddw-1.c new file mode 100644 index 0000000..3d55ecf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/uaddw-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int +t6(int len, void * dummy, unsigned short * __restrict x) +{ + len = len & ~31; + unsigned int result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "uaddw" } } */ +/* { dg-final { scan-assembler "uaddw2" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/uaddw-2.c b/gcc/testsuite/gcc.target/aarch64/uaddw-2.c new file mode 100644 index 0000000..fd3b578 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/uaddw-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int +t6(int len, void * dummy, unsigned short * __restrict x) +{ + len = len & ~31; + unsigned int result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "uaddw" } } */ +/* { dg-final { scan-assembler "uaddw2" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/uaddw-3.c b/gcc/testsuite/gcc.target/aarch64/uaddw-3.c new file mode 100644 index 0000000..499af51 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/uaddw-3.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int +t6(int len, void * dummy, char * __restrict x) +{ + len = len & ~31; + unsigned short result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "uaddw" } } */ +/* { dg-final { scan-assembler "uaddw2" } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 3eb46f2..254c4e3 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4163,6 +4163,7 @@ proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } { } else { set et_vect_widen_sum_hi_to_si_pattern_saved 0 if { [istarget powerpc*-*-*] + || [istarget aarch64*-*-*] || [istarget ia64-*-*] } { set et_vect_widen_sum_hi_to_si_pattern_saved 1 } -- 1.9.1 --------------010609060208060209030009--