[PATCH 1/7][ARM] Add support for ARMv8.1.

[PATCH 1/7][ARM] Add support for ARMv8.1.

[Matthew Wahab]

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Hello,


ARMv8.1 includes an extension to ARM which adds two Adv.SIMD
instructions, vqrdmlah and vqrdmlsh. This patch set adds support for
ARMv8.1 and for the new instructions, enabling the architecture with
--march=armv8.1-a. The new instructions are enabled when both ARMv8.1
and a suitable fpu options are set, for instance with -march=armv8.1-a
-mfpu=neon-fp-armv8 -mfloat-abi=hard.

This patch set adds the command line options and internal feature
macros. Following patches
- enable multilib support for ARMv8.1,
- add patterns for the new instructions,
- add the ACLE feature macro for the ARMv8.1 extensions,
- extend target support in the testsuite to ARMv8.1,
- add the ACLE intrinsics for vqrmdl{as}h and
- add the ACLE intrinsics for vqrmdl{as}h_lane.

Tested the series for arm-none-eabi with cross-compiled check-gcc on an
ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
bootstrap and make check.

Is this ok for trunk?
Matthew

gcc/
2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>

	* config/arm/arm-arches.def: Add "armv8.1-a" and "armv8.1-a+crc".
	* config/arm/arm-protos.h (FL2_ARCH8_1): New.
	(FL2_FOR_ARCH8_1A): New.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm.c (arm_arch8_1): New.
	(arm_option_override): Set arm_arch8_1.
	* config/arm/arm.h (TARGET_NEON_RDMA): New.
	(arm_arch8_1): Declare.
	* doc/invoke.texi (ARM Options, -march): Add "armv8.1-a" and
	"armv8.1-a+crc".
	(ARM Options, -mfpu): Fix a typo.

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From 3ee3a16839c1c316906e33f5384da05ee70dd831 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Tue, 1 Sep 2015 11:31:25 +0100
Subject: [PATCH 1/7] [ARM] Add ARMv8.1 architecture flags and options.

Change-Id: I6bb0c7f020613a1a17e40bccc28b00c30d644c70
---
 gcc/config/arm/arm-arches.def |  5 +++++
 gcc/config/arm/arm-protos.h   |  3 +++
 gcc/config/arm/arm-tables.opt | 10 ++++++++--
 gcc/config/arm/arm.c          |  4 ++++
 gcc/config/arm/arm.h          |  6 ++++++
 gcc/doc/invoke.texi           |  6 +++---
 6 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index ddf6c3c..6c83153 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -57,6 +57,11 @@ ARM_ARCH("armv7-m", cortexm3,	7M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_
 ARM_ARCH("armv7e-m", cortexm4,  7EM,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7EM))
 ARM_ARCH("armv8-a", cortexa53,  8A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH8A))
 ARM_ARCH("armv8-a+crc",cortexa53, 8A,   ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32  | FL_FOR_ARCH8A))
+ARM_ARCH ("armv8.1-a", cortexa53,  8A,
+	  ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8A,  FL2_FOR_ARCH8_1A))
+ARM_ARCH ("armv8.1-a+crc",cortexa53, 8A,
+	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
+			 FL2_FOR_ARCH8_1A))
 ARM_ARCH("iwmmxt",  iwmmxt,     5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
 ARM_ARCH("iwmmxt2", iwmmxt2,    5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
 
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index e4b8fb3..c3eb6d3 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -388,6 +388,8 @@ extern bool arm_is_constant_pool_ref (rtx);
 #define FL_IWMMXT2    (1 << 30)       /* "Intel Wireless MMX2 technology".  */
 #define FL_ARCH6KZ    (1 << 31)       /* ARMv6KZ architecture.  */
 
+#define FL2_ARCH8_1   (1 << 0)	      /* Architecture 8.1.  */
+
 /* Flags that only effect tuning, not available instructions.  */
 #define FL_TUNE		(FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
 			 | FL_CO_PROC)
@@ -416,6 +418,7 @@ extern bool arm_is_constant_pool_ref (rtx);
 #define FL_FOR_ARCH7M	(FL_FOR_ARCH7 | FL_THUMB_DIV)
 #define FL_FOR_ARCH7EM  (FL_FOR_ARCH7M | FL_ARCH7EM)
 #define FL_FOR_ARCH8A	(FL_FOR_ARCH7VE | FL_ARCH8)
+#define FL2_FOR_ARCH8_1A	FL2_ARCH8_1
 
 /* There are too many feature bits to fit in a single word so the set of cpu and
    fpu capabilities is a structure.  A feature set is created and manipulated
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 48aac41..db17f6e 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -416,10 +416,16 @@ EnumValue
 Enum(arm_arch) String(armv8-a+crc) Value(26)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt) Value(27)
+Enum(arm_arch) String(armv8.1-a) Value(27)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(28)
+Enum(arm_arch) String(armv8.1-a+crc) Value(28)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt) Value(29)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt2) Value(30)
 
 Enum
 Name(arm_fpu) Type(int)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index e0cdc20..8cbf364 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -817,6 +817,9 @@ int arm_arch7em = 0;
 /* Nonzero if instructions present in ARMv8 can be used.  */
 int arm_arch8 = 0;
 
+/* Nonzero if this chip supports the ARMv8.1 extensions.  */
+int arm_arch8_1 = 0;
+
 /* Nonzero if this chip can benefit from load scheduling.  */
 int arm_ld_sched = 0;
 
@@ -3109,6 +3112,7 @@ arm_option_override (void)
   arm_arch7 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7);
   arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM);
   arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8);
+  arm_arch8_1 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_1);
   arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2);
   arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);
 
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 6ed8ad3..e7c8898 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -217,6 +217,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
   (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP			\
    && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON))
 
+/* FPU supports ARMv8.1 Adv.SIMD extensions.  */
+#define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1)
+
 /* Q-bit is present.  */
 #define TARGET_ARM_QBIT \
   (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
@@ -436,6 +439,9 @@ extern int arm_arch7em;
 /* Nonzero if this chip supports the ARM Architecture 8 extensions.  */
 extern int arm_arch8;
 
+/* Nonzero if this chip supports the ARM Architecture 8.1 extensions.  */
+extern int arm_arch8_1;
+
 /* Nonzero if this chip can benefit from load scheduling.  */
 extern int arm_ld_sched;
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 53f1fe2..f8e8e5d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13531,8 +13531,8 @@ of the @option{-mcpu=} option.  Permissible names are: @samp{armv2},
 @samp{armv6}, @samp{armv6j},
 @samp{armv6t2}, @samp{armv6z}, @samp{armv6kz}, @samp{armv6-m},
 @samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, @samp{armv7e-m},
-@samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc},
-@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
+@samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a},
+@samp{armv8.1-a+crc}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
 
 @option{-march=armv7ve} is the armv7-a architecture with virtualization
 extensions.
@@ -13635,7 +13635,7 @@ available on the target.  Permissible names are: @samp{vfp}, @samp{vfpv3},
 @samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4},
 @samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4},
 @samp{fpv5-d16}, @samp{fpv5-sp-d16},
-@samp{fp-armv8}, @samp{neon-fp-armv8}, and @samp{crypto-neon-fp-armv8}.
+@samp{fp-armv8}, @samp{neon-fp-armv8} and @samp{crypto-neon-fp-armv8}.
 
 If @option{-msoft-float} is specified this specifies the format of
 floating-point values.
-- 
2.1.4

[PATCH 2/7][ARM] Multilib support for ARMv8.1.

[Matthew Wahab]

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This patch sets up multilib support for ARMv8.1, treating it as a
synonym for ARMv8. Since ARMv8.1 integer, FP or SIMD
instructions are only generated for the new, instruction-specific
instrinsics, mapping to ARMv8 rather than adding a new multilib variant
is sufficient.

Tested the series for arm-none-eabi with cross-compiled check-gcc on an
ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
bootstrap and make check.

Ok for trunk?
Matthew

gcc/
2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>

	* config/arm/t-aprofile: Make "armv8.1-a" and "armv8.1-a+crc"
	matches for "armv8-a".


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From 9cd389bf72cff391423e17423f4624904aff5474 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Fri, 23 Oct 2015 09:37:12 +0100
Subject: [PATCH 2/7] [ARM] Multilib support for ARMv8.1

Change-Id: I65ee77768e22452ac15452cf6d4fdec3079ef852
---
 gcc/config/arm/t-aprofile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile
index cf34161..b23f1bc 100644
--- a/gcc/config/arm/t-aprofile
+++ b/gcc/config/arm/t-aprofile
@@ -98,6 +98,8 @@ MULTILIB_MATCHES       += march?armv8-a=mcpu?xgene1
 
 # Arch Matches
 MULTILIB_MATCHES       += march?armv8-a=march?armv8-a+crc
+MULTILIB_MATCHES       += march?armv8-a=march?armv8.1-a
+MULTILIB_MATCHES       += march?armv8-a=march?armv8.1-a+crc
 
 # FPU matches
 MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3
-- 
2.1.4

[PATCH 3/7][ARM] Add patterns for new instructions

[Matthew Wahab]

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Hello,

This patch adds patterns for the instructions, vqrdmlah and vqrdmlsh,
introduced in the ARMv8.1 architecture. The instructions are made
available when -march=armv8.1-a is enabled with suitable fpu settings,
such as -mfpu=neon-fp-armv8 -mfloat-abi=hard.

Tested the series for arm-none-eabi with cross-compiled check-gcc on an
ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
bootstrap and make check.

Ok for trunk?
Matthew

gcc/
2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>

	* config/arm/iterators.md (VQRDMLH_AS): New.
	(neon_rdma_as): New.
	* config/arm/neon.md
	(neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h<mode>): New.
	(neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>): New.
	* config/arm/unspecs.md (UNSPEC_VQRDMLAH): New.
	(UNSPEC_VQRDMLSH): New.


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From fea646491d51548b775fdfb5a4fd6d6bc72d4c83 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Wed, 17 Jun 2015 12:00:50 +0100
Subject: [PATCH 3/7] [ARM] Add patterns for new instructions.

Change-Id: Ia84c345019c7beda2d3c6c39074043d2e005347a
---
 gcc/config/arm/iterators.md |  5 +++++
 gcc/config/arm/neon.md      | 45 +++++++++++++++++++++++++++++++++++++++++++++
 gcc/config/arm/unspecs.md   |  2 ++
 3 files changed, 52 insertions(+)

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 6a54125..c7a6880 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -362,6 +362,8 @@
 (define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M
                                        UNSPEC_SHA1P])
 
+(define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH])
+
 ;;----------------------------------------------------------------------------
 ;; Mode attributes
 ;;----------------------------------------------------------------------------
@@ -831,3 +833,6 @@
                                (simple_return " && use_simple_return_p ()")])
 (define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)")
                                (simple_return " && use_simple_return_p ()")])
+
+;; Attributes for VQRDMLAH/VQRDMLSH
+(define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")])
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 62fb6da..844ef5e 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2014,6 +2014,18 @@
   [(set_attr "type" "neon_sat_mul_<V_elem_ch><q>")]
 )
 
+;; vqrdmlah, vqrdmlsh
+(define_insn "neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h<mode>"
+  [(set (match_operand:VMDQI 0 "s_register_operand" "=w")
+	(unspec:VMDQI [(match_operand:VMDQI 1 "s_register_operand" "0")
+		       (match_operand:VMDQI 2 "s_register_operand" "w")
+		       (match_operand:VMDQI 3 "s_register_operand" "w")]
+		      VQRDMLH_AS))]
+  "TARGET_NEON_RDMA"
+  "vqrdml<VQRDMLH_AS:neon_rdma_as>h.<V_s_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
+  [(set_attr "type" "neon_sat_mla_<V_elem_ch>_long")]
+)
+
 (define_insn "neon_vqdmlal<mode>"
   [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
         (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
@@ -3176,6 +3188,39 @@ if (BYTES_BIG_ENDIAN)
   [(set_attr "type" "neon_sat_mul_<V_elem_ch>_scalar_q")]
 )
 
+;; vqrdmlah_lane, vqrdmlsh_lane
+(define_insn "neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>"
+  [(set (match_operand:VMQI 0 "s_register_operand" "=w")
+	(unspec:VMQI [(match_operand:VMQI 1 "s_register_operand" "0")
+		      (match_operand:VMQI 2 "s_register_operand" "w")
+		      (match_operand:<V_HALF> 3 "s_register_operand"
+					  "<scalar_mul_constraint>")
+		      (match_operand:SI 4 "immediate_operand" "i")]
+		     VQRDMLH_AS))]
+  "TARGET_NEON_RDMA"
+{
+  return
+   "vqrdml<VQRDMLH_AS:neon_rdma_as>h.<V_s_elem>\t%q0, %q2, %P3[%c4]";
+}
+  [(set_attr "type" "neon_mla_<V_elem_ch>_scalar<q>")]
+)
+
+(define_insn "neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>"
+  [(set (match_operand:VMDI 0 "s_register_operand" "=w")
+	(unspec:VMDI [(match_operand:VMDI 1 "s_register_operand" "0")
+		      (match_operand:VMDI 2 "s_register_operand" "w")
+		      (match_operand:VMDI 3 "s_register_operand"
+					  "<scalar_mul_constraint>")
+		      (match_operand:SI 4 "immediate_operand" "i")]
+		     VQRDMLH_AS))]
+  "TARGET_NEON_RDMA"
+{
+  return
+   "vqrdml<VQRDMLH_AS:neon_rdma_as>h.<V_s_elem>\t%P0, %P2, %P3[%c4]";
+}
+  [(set_attr "type" "neon_mla_<V_elem_ch>_scalar")]
+)
+
 (define_insn "neon_vmla_lane<mode>"
   [(set (match_operand:VMD 0 "s_register_operand" "=w")
 	(unspec:VMD [(match_operand:VMD 1 "s_register_operand" "0")
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 44d4e7d..e7ae9a2 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -360,5 +360,7 @@
   UNSPEC_NVRINTX
   UNSPEC_NVRINTA
   UNSPEC_NVRINTN
+  UNSPEC_VQRDMLAH
+  UNSPEC_VQRDMLSH
 ])
 
-- 
2.1.4

[PATCH 4/7][ARM] Add ACLE feature macro for ARMv8.1 instructions.

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 576 bytes --]

Hello,

This patch adds the feature macro __ARM_FEATURE_QRDMX to indicate the
presence of the ARMv8.1 instructions vqrdmlah and vqrdmlsh. It is
defined when the instructions are available, as it is when
-march=armv8.1-a is enabled with suitable fpu options.

Tested the series for arm-none-eabi with cross-compiled check-gcc on an
ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
bootstrap and make check.

Ok for trunk?
Matthew

gcc/
2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>

	* config/arm/arm-c.c (arm_cpu_builtins): Define __ARM_FEATURE_QRDMX.


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From 4009cf5c0455429a415be9ca239ac09ac86b17dd Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Wed, 17 Jun 2015 13:25:09 +0100
Subject: [PATCH 4/7] [ARM] Add __ARM_FEATURE_QRDMX

Change-Id: I26cde507e8844a731e4fd857fbd30bf87f213f89
---
 gcc/config/arm/arm-c.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index c336a16..6bf740b 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -66,6 +66,8 @@ arm_cpu_builtins (struct cpp_reader* pfile)
   def_or_undef_macro (pfile, "__ARM_FEATURE_SAT", TARGET_ARM_SAT);
   def_or_undef_macro (pfile, "__ARM_FEATURE_CRYPTO", TARGET_CRYPTO);
 
+  if (TARGET_NEON_RDMA)
+    builtin_define ("__ARM_FEATURE_QRDMX");
   if (unaligned_access)
     builtin_define ("__ARM_FEATURE_UNALIGNED");
   if (TARGET_CRC32)
-- 
2.1.4

[PATCH 5/7][Testsuite] Support ARMv8.1 ARM tests.

[Matthew Wahab]

Hello,

This patch adds ARMv8.1 support to GCC Dejagnu, to allow ARM
tests to specify targest and to set up command line options.
It builds on the ARMv8.1 target support added for AArch64 tests, partly
reworking that support to take into account the different configurations
that tests may be run under.

The main changes are
- add_options_for_arm_v8_1a_neon: Call
   check_effective_target_arm_v8_1a_neon_ok to select a suitable set of
   options.
- check_effective_target_arm_v8_1a_neon_ok: Test possible command line
   options, recording the first set that works.
- check_effective_target_arm_v8_1a_neon_hw: Add a test for ARM targets.

Tested the series for arm-none-eabi with cross-compiled check-gcc on an
ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
bootstrap and make check.

Ok for trunk?
Matthew

testsuite/
2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>

	* lib/target-supports.exp (add_options_for_arm_v8_1a_neon): Update
	comment.  Use check_effetive_target_arm_v8_1a_neon_ok to select
	the command line options.
	(check_effective_target_arm_v8_1a_neon_ok_nocache): Update initial
	test to allow ARM targets.  Select and record a working set of
	command line options.
	(check_effective_target_arm_v8_1a_neon_hw): Add tests for ARM
	targets.

[PATCH 6/7][ARM] Add ACLE intrinsics vqrdmlah and vqrdmlsh

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 817 bytes --]

Hello,

This patch adds the ACLE intrinsics for the instructions introduced in
ARMv8.1. It adds the vqrmdlah and vqrdmlsh forms of the instrinsics to
the arm_neon.h header, together with the ARM builtins used to implement
them. The intrinsics are available when -march=armv8.1-a is enabled
together with appropriate fpu options.

Tested the series for arm-none-eabi with cross-compiled check-gcc on an
ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
bootstrap and make check.

Ok for trunk?
Matthew

gcc/
2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>

	* config/arm/arm_neon.h (vqrdmlah_s16, vqrdmlah_s32): New.
	(vqrdmlahq_s16, vqrdmlahq_s32): New.
	(vqrdmlsh_s16, vqrdmlsh_s32): New.
	(vqrdmlahq_s16, vqrdmlshq_s32): New.
	* config/arm/arm_neon_builtins.def: Add "vqrdmlah" and "vqrdmlsh".


[-- Attachment #2: 0006-ARM-Add-neon-intrinsics-vqrdmlah-vqrdmlsh.patch --]
[-- Type: text/x-patch, Size: 3199 bytes --]

From 93e9db5bf06172f18f4e89e9533c66d8a0c4f2ca Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Tue, 1 Sep 2015 16:21:44 +0100
Subject: [PATCH 6/7] [ARM] Add neon intrinsics vqrdmlah, vqrdmlsh.

Change-Id: Ic40ff4d477f36ec01714c68e3b83b66208c7958b
---
 gcc/config/arm/arm_neon.h            | 50 ++++++++++++++++++++++++++++++++++++
 gcc/config/arm/arm_neon_builtins.def |  2 ++
 2 files changed, 52 insertions(+)

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 0a33d21..b617f80 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -1158,6 +1158,56 @@ vqrdmulhq_s32 (int32x4_t __a, int32x4_t __b)
   return (int32x4_t)__builtin_neon_vqrdmulhv4si (__a, __b);
 }
 
+#ifdef __ARM_FEATURE_QRDMX
+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+vqrdmlah_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+{
+  return (int16x4_t)__builtin_neon_vqrdmlahv4hi (__a, __b, __c);
+}
+
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vqrdmlah_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+  return (int32x2_t)__builtin_neon_vqrdmlahv2si (__a, __b, __c);
+}
+
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vqrdmlahq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+{
+  return (int16x8_t)__builtin_neon_vqrdmlahv8hi (__a, __b, __c);
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vqrdmlahq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return (int32x4_t)__builtin_neon_vqrdmlahv4si (__a, __b, __c);
+}
+
+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+vqrdmlsh_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+{
+  return (int16x4_t)__builtin_neon_vqrdmlshv4hi (__a, __b, __c);
+}
+
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vqrdmlsh_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+  return (int32x2_t)__builtin_neon_vqrdmlshv2si (__a, __b, __c);
+}
+
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vqrdmlshq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+{
+  return (int16x8_t)__builtin_neon_vqrdmlshv8hi (__a, __b, __c);
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vqrdmlshq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return (int32x4_t)__builtin_neon_vqrdmlshv4si (__a, __b, __c);
+}
+#endif
+
 __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
 vmull_s8 (int8x8_t __a, int8x8_t __b)
 {
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 0b719df..8d5c0ca 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -45,6 +45,8 @@ VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si)
 VAR4 (BINOP, vqrdmulh, v4hi, v2si, v8hi, v4si)
 VAR2 (TERNOP, vqdmlal, v4hi, v2si)
 VAR2 (TERNOP, vqdmlsl, v4hi, v2si)
+VAR4 (TERNOP, vqrdmlah, v4hi, v2si, v8hi, v4si)
+VAR4 (TERNOP, vqrdmlsh, v4hi, v2si, v8hi, v4si)
 VAR3 (BINOP, vmullp, v8qi, v4hi, v2si)
 VAR3 (BINOP, vmulls, v8qi, v4hi, v2si)
 VAR3 (BINOP, vmullu, v8qi, v4hi, v2si)
-- 
2.1.4

[PATCH 7/7][ARM] Add ACLE intrinsics vqrdmlah_lane and vqrdmlsh_lane

[Matthew Wahab]

Hello,

This patch adds the ACLE intrinsics for the instructions introduced in
ARMv8.1. It adds the vqrmdlah_lane and vqrdmlsh_lane forms of the
instrinsics to the arm_neon.h header, together with the ARM builtins
used to implement them. The intrinsics are available when
-march=armv8.1-a is enabled together with appropriate fpu options.

Tested the series for arm-none-eabi with cross-compiled check-gcc on an
ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
bootstrap and make check.

Ok for trunk?
Matthew

gcc/
2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>

	* config/arm/arm_neon.h (vqrdmlahq_lane_s16): New.
	(vqrdmlahq_lane_s32): New.
	(vqrdmlah_lane_s16): New.
	(vqrdmlah_lane_s32): New.
	(vqrdmlshq_lane_s16): New.
	(vqrdmlshq_lane_s32): New.
	(vqrdmlsh_lane_s16): New.
	(vqrdmlsh_lane_s32): New.
	* config/arm/arm_neon_builtins.def: Add "vqrdmlah_lane" and
	"vqrdmlsh_lane".

Re: [PATCH 5/7][Testsuite] Support ARMv8.1 ARM tests.

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 1455 bytes --]

Attached the missing patch.
Matthew

On 26/11/15 16:02, Matthew Wahab wrote:
> Hello,
>
> This patch adds ARMv8.1 support to GCC Dejagnu, to allow ARM
> tests to specify targest and to set up command line options.
> It builds on the ARMv8.1 target support added for AArch64 tests, partly
> reworking that support to take into account the different configurations
> that tests may be run under.
>
> The main changes are
> - add_options_for_arm_v8_1a_neon: Call
>    check_effective_target_arm_v8_1a_neon_ok to select a suitable set of
>    options.
> - check_effective_target_arm_v8_1a_neon_ok: Test possible command line
>    options, recording the first set that works.
> - check_effective_target_arm_v8_1a_neon_hw: Add a test for ARM targets.
>
> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
> bootstrap and make check.
>
> Ok for trunk?
> Matthew
>
> testsuite/
> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>
>      * lib/target-supports.exp (add_options_for_arm_v8_1a_neon): Update
>      comment.  Use check_effetive_target_arm_v8_1a_neon_ok to select
>      the command line options.
>      (check_effective_target_arm_v8_1a_neon_ok_nocache): Update initial
>      test to allow ARM targets.  Select and record a working set of
>      command line options.
>      (check_effective_target_arm_v8_1a_neon_hw): Add tests for ARM
>      targets.
>


[-- Attachment #2: 0005-Testsuite-Support-ARMv8.1-NEON-on-ARM.patch --]
[-- Type: text/x-patch, Size: 3697 bytes --]

From 6f767289ce83be88bc088c7adf66d137ed335762 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Fri, 9 Oct 2015 17:38:12 +0100
Subject: [PATCH 5/7] [Testsuite] Support ARMv8.1 NEON on ARM.

Change-Id: I35436b64996789d54f215d66ed4b0ec5ffe48e37
---
 gcc/testsuite/lib/target-supports.exp | 56 +++++++++++++++++++++++++----------
 1 file changed, 41 insertions(+), 15 deletions(-)

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index dcd51fd..34bb45d 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2816,14 +2816,15 @@ proc add_options_for_arm_v8_neon { flags } {
     return "$flags $et_arm_v8_neon_flags -march=armv8-a"
 }
 
-# Add the options needed for ARMv8.1 Adv.SIMD.
+# Add the options needed for ARMv8.1 Adv.SIMD.  Also adds the ARMv8 NEON
+# options for AArch64 and for ARM.
 
 proc add_options_for_arm_v8_1a_neon { flags } {
-    if { [istarget aarch64*-*-*] } {
-	return "$flags -march=armv8.1-a"
-    } else {
+    if { ! [check_effective_target_arm_v8_1a_neon_ok] } {
 	return "$flags"
     }
+    global et_arm_v8_1a_neon_flags
+    return "$flags $et_arm_v8_1a_neon_flags -march=armv8.1-a"
 }
 
 proc add_options_for_arm_crc { flags } {
@@ -3271,17 +3272,29 @@ proc check_effective_target_arm_neonv2_hw { } {
 }
 
 # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0
-# otherwise.  The test is valid for AArch64.
+# otherwise.  The test is valid for AArch64 and ARM.
 
 proc check_effective_target_arm_v8_1a_neon_ok_nocache { } {
-    if { ![istarget aarch64*-*-*] } {
-	return 0
+    global et_arm_v8_1a_neon_flags
+    set et_arm_v8_1a_neon_flags ""
+
+    if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
+	return 0;
     }
-    return [check_no_compiler_messages_nocache arm_v8_1a_neon_ok assembly {
-	#if !defined (__ARM_FEATURE_QRDMX)
-	#error "__ARM_FEATURE_QRDMX not defined"
-	#endif
-    } [add_options_for_arm_v8_1a_neon ""]]
+
+    foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
+		       "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
+	if { [check_no_compiler_messages_nocache arm_v8_1a_neon_ok object {
+	    #if !defined (__ARM_FEATURE_QRDMX)
+	    #error "__ARM_FEATURE_QRDMX not defined"
+	    #endif
+	} "$flags -march=armv8.1-a"] } {
+	    set et_arm_v8_1a_neon_flags "$flags -march=armv8.1-a"
+	    return 1
+	}
+    }
+
+    return 0;
 }
 
 proc check_effective_target_arm_v8_1a_neon_ok { } {
@@ -3308,16 +3321,17 @@ proc check_effective_target_arm_v8_neon_hw { } {
 }
 
 # Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0
-# otherwise.  The test is valid for AArch64.
+# otherwise.  The test is valid for AArch64 and ARM.
 
 proc check_effective_target_arm_v8_1a_neon_hw { } {
     if { ![check_effective_target_arm_v8_1a_neon_ok] } {
 	return 0;
     }
-    return [check_runtime_nocache arm_v8_1a_neon_hw_available {
+    return [check_runtime arm_v8_1a_neon_hw_available {
 	int
 	main (void)
 	{
+	  #ifdef __ARM_ARCH_ISA_A64
 	  __Int32x2_t a = {0, 1};
 	  __Int32x2_t b = {0, 2};
 	  __Int32x2_t result;
@@ -3327,9 +3341,21 @@ proc check_effective_target_arm_v8_1a_neon_hw { } {
 	       : "w"(a), "w"(b)
 	       : /* No clobbers.  */);
 
+	  #else
+
+	  __simd64_int32_t a = {0, 1};
+	  __simd64_int32_t b = {0, 2};
+	  __simd64_int32_t result;
+
+	  asm ("vqrdmlah.s32 %P0, %P1, %P2"
+	       : "=w"(result)
+	       : "w"(a), "w"(b)
+	       : /* No clobbers.  */);
+	  #endif
+
 	  return result[0];
 	}
-    }  [add_options_for_arm_v8_1a_neon ""]]
+    } [add_options_for_arm_v8_1a_neon ""]]
 }
 
 # Return 1 if this is a ARM target with NEON enabled.
-- 
2.1.4

Re: [PATCH 7/7][ARM] Add ACLE intrinsics vqrdmlah_lane and vqrdmlsh_lane

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 1080 bytes --]

Attached the missing patch.
Matthew

On 26/11/15 16:04, Matthew Wahab wrote:
> Hello,
>
> This patch adds the ACLE intrinsics for the instructions introduced in
> ARMv8.1. It adds the vqrmdlah_lane and vqrdmlsh_lane forms of the
> instrinsics to the arm_neon.h header, together with the ARM builtins
> used to implement them. The intrinsics are available when
> -march=armv8.1-a is enabled together with appropriate fpu options.
>
> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
> bootstrap and make check.
>
> Ok for trunk?
> Matthew
>
> gcc/
> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>
>      * config/arm/arm_neon.h (vqrdmlahq_lane_s16): New.
>      (vqrdmlahq_lane_s32): New.
>      (vqrdmlah_lane_s16): New.
>      (vqrdmlah_lane_s32): New.
>      (vqrdmlshq_lane_s16): New.
>      (vqrdmlshq_lane_s32): New.
>      (vqrdmlsh_lane_s16): New.
>      (vqrdmlsh_lane_s32): New.
>      * config/arm/arm_neon_builtins.def: Add "vqrdmlah_lane" and
>      "vqrdmlsh_lane".
>


[-- Attachment #2: 0007-ARM-Add-neon-intrinsics-vqrdmlah_lane-vqrdmlsh_lane.patch --]
[-- Type: text/x-patch, Size: 3586 bytes --]

From cdfee6be49e52056de8999fbc33a432f2cc7254f Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Tue, 1 Sep 2015 16:22:34 +0100
Subject: [PATCH 7/7] [ARM] Add neon intrinsics vqrdmlah_lane, vqrdmlsh_lane.

Change-Id: Ia0ab4bbe683af2d019d18a34302a7b9798193a79
---
 gcc/config/arm/arm_neon.h            | 50 ++++++++++++++++++++++++++++++++++++
 gcc/config/arm/arm_neon_builtins.def |  2 ++
 2 files changed, 52 insertions(+)

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index b617f80..ed50253 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -7096,6 +7096,56 @@ vqrdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
   return (int32x2_t)__builtin_neon_vqrdmulh_lanev2si (__a, __b, __c);
 }
 
+#ifdef __ARM_FEATURE_QRDMX
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vqrdmlahq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
+{
+  return (int16x8_t)__builtin_neon_vqrdmlah_lanev8hi (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vqrdmlahq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
+{
+  return (int32x4_t)__builtin_neon_vqrdmlah_lanev4si (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+vqrdmlah_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+{
+  return (int16x4_t)__builtin_neon_vqrdmlah_lanev4hi (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vqrdmlah_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+{
+  return (int32x2_t)__builtin_neon_vqrdmlah_lanev2si (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vqrdmlshq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
+{
+  return (int16x8_t)__builtin_neon_vqrdmlsh_lanev8hi (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vqrdmlshq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
+{
+  return (int32x4_t)__builtin_neon_vqrdmlsh_lanev4si (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+vqrdmlsh_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+{
+  return (int16x4_t)__builtin_neon_vqrdmlsh_lanev4hi (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vqrdmlsh_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+{
+  return (int32x2_t)__builtin_neon_vqrdmlsh_lanev2si (__a, __b, __c, __d);
+}
+#endif
+
 __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
 vmul_n_s16 (int16x4_t __a, int16_t __b)
 {
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 8d5c0ca..1fdb2a8 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -60,6 +60,8 @@ VAR4 (BINOP, vqdmulh_n, v4hi, v2si, v8hi, v4si)
 VAR4 (BINOP, vqrdmulh_n, v4hi, v2si, v8hi, v4si)
 VAR4 (SETLANE, vqdmulh_lane, v4hi, v2si, v8hi, v4si)
 VAR4 (SETLANE, vqrdmulh_lane, v4hi, v2si, v8hi, v4si)
+VAR4 (MAC_LANE, vqrdmlah_lane, v4hi, v2si, v8hi, v4si)
+VAR4 (MAC_LANE, vqrdmlsh_lane, v4hi, v2si, v8hi, v4si)
 VAR2 (BINOP, vqdmull, v4hi, v2si)
 VAR8 (BINOP, vshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
 VAR8 (BINOP, vshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
-- 
2.1.4

Re: [PATCH 5/7][Testsuite] Support ARMv8.1 ARM tests.

[Christophe Lyon]

On 26 November 2015 at 17:10, Matthew Wahab <matthew.wahab@foss.arm.com> wrote:
> Attached the missing patch.
> Matthew
>
>
> On 26/11/15 16:02, Matthew Wahab wrote:
>>
>> Hello,
>>
>> This patch adds ARMv8.1 support to GCC Dejagnu, to allow ARM
>> tests to specify targest and to set up command line options.
>> It builds on the ARMv8.1 target support added for AArch64 tests, partly
>> reworking that support to take into account the different configurations
>> that tests may be run under.
>>
>> The main changes are
>> - add_options_for_arm_v8_1a_neon: Call
>>    check_effective_target_arm_v8_1a_neon_ok to select a suitable set of
>>    options.
>> - check_effective_target_arm_v8_1a_neon_ok: Test possible command line
>>    options, recording the first set that works.
>> - check_effective_target_arm_v8_1a_neon_hw: Add a test for ARM targets.
>>
>> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
>> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
>> bootstrap and make check.
>>
>> Ok for trunk?
>> Matthew
>>

Hi Matthew,

I may be mistaken, but -mfpu=neon-fp-armv8 and -mfloat-abi=softfp are not
supported by aarch64-gcc. So it seems to me that
check_effective_target_arm_v8_1a_neon_ok_nocache will not always work
for aarch64 after your patch.

Or does it work because no option is needed and thus "" always
matches and thus the loop always exits after the first iteration
on aarch64?

Maybe a more accurate comment would help remembering that, in case
-mfpu option becomes necessary for aarch64.

Christophe.



>> testsuite/
>> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>>
>>      * lib/target-supports.exp (add_options_for_arm_v8_1a_neon): Update
>>      comment.  Use check_effetive_target_arm_v8_1a_neon_ok to select
>>      the command line options.
>>      (check_effective_target_arm_v8_1a_neon_ok_nocache): Update initial
>>      test to allow ARM targets.  Select and record a working set of
>>      command line options.
>>      (check_effective_target_arm_v8_1a_neon_hw): Add tests for ARM
>>      targets.
>>
>

Re: [PATCH 1/7][ARM] Add support for ARMv8.1.

[Christophe Lyon]

On 26 November 2015 at 16:55, Matthew Wahab <matthew.wahab@foss.arm.com> wrote:
> Hello,
>
>
> ARMv8.1 includes an extension to ARM which adds two Adv.SIMD
> instructions, vqrdmlah and vqrdmlsh. This patch set adds support for
> ARMv8.1 and for the new instructions, enabling the architecture with
> --march=armv8.1-a. The new instructions are enabled when both ARMv8.1
> and a suitable fpu options are set, for instance with -march=armv8.1-a
> -mfpu=neon-fp-armv8 -mfloat-abi=hard.
>
> This patch set adds the command line options and internal feature
> macros. Following patches
> - enable multilib support for ARMv8.1,
> - add patterns for the new instructions,
> - add the ACLE feature macro for the ARMv8.1 extensions,
> - extend target support in the testsuite to ARMv8.1,
> - add the ACLE intrinsics for vqrmdl{as}h and
> - add the ACLE intrinsics for vqrmdl{as}h_lane.
>
> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
> bootstrap and make check.
>
> Is this ok for trunk?
> Matthew
>
Hi,

The whole series LGTM, but do you plan to add tests for the new intrinsics?

Thanks,

Christophe.


> gcc/
> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>
>         * config/arm/arm-arches.def: Add "armv8.1-a" and "armv8.1-a+crc".
>         * config/arm/arm-protos.h (FL2_ARCH8_1): New.
>         (FL2_FOR_ARCH8_1A): New.
>         * config/arm/arm-tables.opt: Regenerate.
>         * config/arm/arm.c (arm_arch8_1): New.
>         (arm_option_override): Set arm_arch8_1.
>         * config/arm/arm.h (TARGET_NEON_RDMA): New.
>         (arm_arch8_1): Declare.
>         * doc/invoke.texi (ARM Options, -march): Add "armv8.1-a" and
>         "armv8.1-a+crc".
>         (ARM Options, -mfpu): Fix a typo.

Re: [PATCH 5/7][Testsuite] Support ARMv8.1 ARM tests.

[Matthew Wahab]

On 27/11/15 13:44, Christophe Lyon wrote:
>> On 26/11/15 16:02, Matthew Wahab wrote:

>>> This patch adds ARMv8.1 support to GCC Dejagnu, to allow ARM
>>> tests to specify targest and to set up command line options.
>>> It builds on the ARMv8.1 target support added for AArch64 tests, partly
>>> reworking that support to take into account the different configurations
>>> that tests may be run under.

> I may be mistaken, but -mfpu=neon-fp-armv8 and -mfloat-abi=softfp are not
> supported by aarch64-gcc. So it seems to me that
> check_effective_target_arm_v8_1a_neon_ok_nocache will not always work
> for aarch64 after your patch.

> Or does it work because no option is needed and thus "" always
> matches and thus the loop always exits after the first iteration
> on aarch64?

Yes, the idea is that the empty string will make the function first try 
'-march=armv8.1-a' without any other flag. That will work for AArch64 because it 
doesn't need any other option.

> Maybe a more accurate comment would help remembering that, in case
> -mfpu option becomes necessary for aarch64.
>

Agreed, it's worth having a comment to explain what the 'foreach' construct is doing.

Matthew

Re: [PATCH 1/7][ARM] Add support for ARMv8.1.

[Matthew Wahab]

On 27/11/15 14:05, Christophe Lyon wrote:
> On 26 November 2015 at 16:55, Matthew Wahab <matthew.wahab@foss.arm.com> wrote:

>> ARMv8.1 includes an extension to ARM which adds two Adv.SIMD
>> instructions, vqrdmlah and vqrdmlsh. This patch set adds support for
>> ARMv8.1 and for the new instructions, enabling the architecture with
>> --march=armv8.1-a. The new instructions are enabled when both ARMv8.1
>> and a suitable fpu options are set, for instance with -march=armv8.1-a
>> -mfpu=neon-fp-armv8 -mfloat-abi=hard.
>>
>> This patch set adds the command line options and internal feature
>> macros. Following patches
>> - enable multilib support for ARMv8.1,
>> - add patterns for the new instructions,
>> - add the ACLE feature macro for the ARMv8.1 extensions,
>> - extend target support in the testsuite to ARMv8.1,
>> - add the ACLE intrinsics for vqrmdl{as}h and
>> - add the ACLE intrinsics for vqrmdl{as}h_lane.
>>

>
> The whole series LGTM, but do you plan to add tests for the new intrinsics?

The Adv.SIMD intrinsics tests are in gcc.target/aarch64/advsimd-intrinsics, they get 
run for both AArch64 and ARM backends. The tests for the new intrinsics were added 
(yesterday) by the AArch64 version of this patch.

Matthew

Re: [PATCH 5/7][Testsuite] Support ARMv8.1 ARM tests.

[Matthew Wahab]

On 27/11/15 13:44, Christophe Lyon wrote:
>> On 26/11/15 16:02, Matthew Wahab wrote:

>>> This patch adds ARMv8.1 support to GCC Dejagnu, to allow ARM
>>> tests to specify targest and to set up command line options.
>>> It builds on the ARMv8.1 target support added for AArch64 tests, partly
>>> reworking that support to take into account the different configurations
>>> that tests may be run under.

> I may be mistaken, but -mfpu=neon-fp-armv8 and -mfloat-abi=softfp are not
> supported by aarch64-gcc. So it seems to me that
> check_effective_target_arm_v8_1a_neon_ok_nocache will not always work
> for aarch64 after your patch.

> Or does it work because no option is needed and thus "" always
> matches and thus the loop always exits after the first iteration
> on aarch64?

Yes, the idea is that the empty string will make the function first try 
'-march=armv8.1-a' without any other flag. That will work for AArch64 because it 
doesn't need any other option.

> Maybe a more accurate comment would help remembering that, in case
> -mfpu option becomes necessary for aarch64.
>

Agreed, it's worth having a comment to explain what the 'foreach' construct is doing.

Matthew

Re: [PATCH 1/7][ARM] Add support for ARMv8.1.

[Christophe Lyon]

On 27 November 2015 at 18:05, Matthew Wahab <matthew.wahab@foss.arm.com> wrote:
> On 27/11/15 14:05, Christophe Lyon wrote:
>>
>> On 26 November 2015 at 16:55, Matthew Wahab <matthew.wahab@foss.arm.com>
>> wrote:
>
>
>>> ARMv8.1 includes an extension to ARM which adds two Adv.SIMD
>>> instructions, vqrdmlah and vqrdmlsh. This patch set adds support for
>>> ARMv8.1 and for the new instructions, enabling the architecture with
>>> --march=armv8.1-a. The new instructions are enabled when both ARMv8.1
>>> and a suitable fpu options are set, for instance with -march=armv8.1-a
>>> -mfpu=neon-fp-armv8 -mfloat-abi=hard.
>>>
>>> This patch set adds the command line options and internal feature
>>> macros. Following patches
>>> - enable multilib support for ARMv8.1,
>>> - add patterns for the new instructions,
>>> - add the ACLE feature macro for the ARMv8.1 extensions,
>>> - extend target support in the testsuite to ARMv8.1,
>>> - add the ACLE intrinsics for vqrmdl{as}h and
>>> - add the ACLE intrinsics for vqrmdl{as}h_lane.
>>>
>
>>
>> The whole series LGTM, but do you plan to add tests for the new
>> intrinsics?
>
>
> The Adv.SIMD intrinsics tests are in gcc.target/aarch64/advsimd-intrinsics,
> they get run for both AArch64 and ARM backends. The tests for the new
> intrinsics were added (yesterday) by the AArch64 version of this patch.
>

Ha yes, of course.

> Matthew

Re: [PATCH 1/7][ARM] Add support for ARMv8.1.

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 1664 bytes --]

Ping. Updated patch attached.
Matthew

On 26/11/15 15:55, Matthew Wahab wrote:
> Hello,
>
>
> ARMv8.1 includes an extension to ARM which adds two Adv.SIMD
> instructions, vqrdmlah and vqrdmlsh. This patch set adds support for
> ARMv8.1 and for the new instructions, enabling the architecture with
> --march=armv8.1-a. The new instructions are enabled when both ARMv8.1
> and a suitable fpu options are set, for instance with -march=armv8.1-a
> -mfpu=neon-fp-armv8 -mfloat-abi=hard.
>
> This patch set adds the command line options and internal feature
> macros. Following patches
> - enable multilib support for ARMv8.1,
> - add patterns for the new instructions,
> - add the ACLE feature macro for the ARMv8.1 extensions,
> - extend target support in the testsuite to ARMv8.1,
> - add the ACLE intrinsics for vqrmdl{as}h and
> - add the ACLE intrinsics for vqrmdl{as}h_lane.
>
> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
> bootstrap and make check.
>
> Is this ok for trunk?
> Matthew
>
> gcc/
> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>
>      * config/arm/arm-arches.def: Add "armv8.1-a" and "armv8.1-a+crc".
>      * config/arm/arm-protos.h (FL2_ARCH8_1): New.
>      (FL2_FOR_ARCH8_1A): New.
>      * config/arm/arm-tables.opt: Regenerate.
>      * config/arm/arm.c (arm_arch8_1): New.
>      (arm_option_override): Set arm_arch8_1.
>      * config/arm/arm.h (TARGET_NEON_RDMA): New.
>      (arm_arch8_1): Declare.
>      * doc/invoke.texi (ARM Options, -march): Add "armv8.1-a" and
>      "armv8.1-a+crc".
>      (ARM Options, -mfpu): Fix a typo.


[-- Attachment #2: 0001-ARM-Add-ARMv8.1-architecture-flags-and-options.patch --]
[-- Type: text/x-patch, Size: 6273 bytes --]

From 65bcf9a875fd31f6201e64cbbd4fdfb0b8f4719e Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Tue, 1 Sep 2015 11:31:25 +0100
Subject: [PATCH 1/7] [ARM] Add ARMv8.1 architecture flags and options.

Change-Id: I6bb0c7f020613a1a17e40bccc28b00c30d644c70
---
 gcc/config/arm/arm-arches.def |  5 +++++
 gcc/config/arm/arm-protos.h   |  3 +++
 gcc/config/arm/arm-tables.opt | 10 ++++++++--
 gcc/config/arm/arm.c          |  4 ++++
 gcc/config/arm/arm.h          |  6 ++++++
 gcc/doc/invoke.texi           |  6 +++---
 6 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index ddf6c3c..6c83153 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -57,6 +57,11 @@ ARM_ARCH("armv7-m", cortexm3,	7M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_
 ARM_ARCH("armv7e-m", cortexm4,  7EM,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7EM))
 ARM_ARCH("armv8-a", cortexa53,  8A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH8A))
 ARM_ARCH("armv8-a+crc",cortexa53, 8A,   ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32  | FL_FOR_ARCH8A))
+ARM_ARCH ("armv8.1-a", cortexa53,  8A,
+	  ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8A,  FL2_FOR_ARCH8_1A))
+ARM_ARCH ("armv8.1-a+crc",cortexa53, 8A,
+	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
+			 FL2_FOR_ARCH8_1A))
 ARM_ARCH("iwmmxt",  iwmmxt,     5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
 ARM_ARCH("iwmmxt2", iwmmxt2,    5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
 
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index e7328e7..d649e86 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -387,6 +387,8 @@ extern bool arm_is_constant_pool_ref (rtx);
 #define FL_IWMMXT2    (1 << 30)       /* "Intel Wireless MMX2 technology".  */
 #define FL_ARCH6KZ    (1 << 31)       /* ARMv6KZ architecture.  */
 
+#define FL2_ARCH8_1   (1 << 0)	      /* Architecture 8.1.  */
+
 /* Flags that only effect tuning, not available instructions.  */
 #define FL_TUNE		(FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
 			 | FL_CO_PROC)
@@ -415,6 +417,7 @@ extern bool arm_is_constant_pool_ref (rtx);
 #define FL_FOR_ARCH7M	(FL_FOR_ARCH7 | FL_THUMB_DIV)
 #define FL_FOR_ARCH7EM  (FL_FOR_ARCH7M | FL_ARCH7EM)
 #define FL_FOR_ARCH8A	(FL_FOR_ARCH7VE | FL_ARCH8)
+#define FL2_FOR_ARCH8_1A	FL2_ARCH8_1
 
 /* There are too many feature bits to fit in a single word so the set of cpu and
    fpu capabilities is a structure.  A feature set is created and manipulated
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 48aac41..db17f6e 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -416,10 +416,16 @@ EnumValue
 Enum(arm_arch) String(armv8-a+crc) Value(26)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt) Value(27)
+Enum(arm_arch) String(armv8.1-a) Value(27)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(28)
+Enum(arm_arch) String(armv8.1-a+crc) Value(28)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt) Value(29)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt2) Value(30)
 
 Enum
 Name(arm_fpu) Type(int)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3588b83..f89411e 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -817,6 +817,9 @@ int arm_arch7em = 0;
 /* Nonzero if instructions present in ARMv8 can be used.  */
 int arm_arch8 = 0;
 
+/* Nonzero if this chip supports the ARMv8.1 extensions.  */
+int arm_arch8_1 = 0;
+
 /* Nonzero if this chip can benefit from load scheduling.  */
 int arm_ld_sched = 0;
 
@@ -3154,6 +3157,7 @@ arm_option_override (void)
   arm_arch7 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7);
   arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM);
   arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8);
+  arm_arch8_1 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_1);
   arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2);
   arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);
 
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index fd999dd..f3c5e11 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -218,6 +218,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
   (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP			\
    && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON))
 
+/* FPU supports ARMv8.1 Adv.SIMD extensions.  */
+#define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1)
+
 /* Q-bit is present.  */
 #define TARGET_ARM_QBIT \
   (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
@@ -437,6 +440,9 @@ extern int arm_arch7em;
 /* Nonzero if this chip supports the ARM Architecture 8 extensions.  */
 extern int arm_arch8;
 
+/* Nonzero if this chip supports the ARM Architecture 8.1 extensions.  */
+extern int arm_arch8_1;
+
 /* Nonzero if this chip can benefit from load scheduling.  */
 extern int arm_ld_sched;
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 33f579f..f479b4b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13534,8 +13534,8 @@ of the @option{-mcpu=} option.  Permissible names are: @samp{armv2},
 @samp{armv6}, @samp{armv6j},
 @samp{armv6t2}, @samp{armv6z}, @samp{armv6kz}, @samp{armv6-m},
 @samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, @samp{armv7e-m},
-@samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc},
-@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
+@samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a},
+@samp{armv8.1-a+crc}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
 
 @option{-march=armv7ve} is the armv7-a architecture with virtualization
 extensions.
@@ -13638,7 +13638,7 @@ available on the target.  Permissible names are: @samp{vfp}, @samp{vfpv3},
 @samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4},
 @samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4},
 @samp{fpv5-d16}, @samp{fpv5-sp-d16},
-@samp{fp-armv8}, @samp{neon-fp-armv8}, and @samp{crypto-neon-fp-armv8}.
+@samp{fp-armv8}, @samp{neon-fp-armv8} and @samp{crypto-neon-fp-armv8}.
 
 If @option{-msoft-float} is specified this specifies the format of
 floating-point values.
-- 
2.1.4

Re: [PATCH 2/7][ARM] Multilib support for ARMv8.1.

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 728 bytes --]

Ping. Updated patch attached.
Matthew

On 26/11/15 15:58, Matthew Wahab wrote:
> This patch sets up multilib support for ARMv8.1, treating it as a
> synonym for ARMv8. Since ARMv8.1 integer, FP or SIMD
> instructions are only generated for the new, instruction-specific
> instrinsics, mapping to ARMv8 rather than adding a new multilib variant
> is sufficient.
>
> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
> bootstrap and make check.
>
> Ok for trunk?
> Matthew
>
> gcc/
> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>
>      * config/arm/t-aprofile: Make "armv8.1-a" and "armv8.1-a+crc"
>      matches for "armv8-a".
>


[-- Attachment #2: 0002-ARM-Multilib-support-for-ARMv8.1.patch --]
[-- Type: text/x-patch, Size: 842 bytes --]

From c5c0f983e03135fe0cde29077353b429c0c502a2 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Fri, 23 Oct 2015 09:37:12 +0100
Subject: [PATCH 2/7] [ARM] Multilib support for ARMv8.1

Change-Id: I65ee77768e22452ac15452cf6d4fdec3079ef852
---
 gcc/config/arm/t-aprofile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile
index cf34161..b23f1bc 100644
--- a/gcc/config/arm/t-aprofile
+++ b/gcc/config/arm/t-aprofile
@@ -98,6 +98,8 @@ MULTILIB_MATCHES       += march?armv8-a=mcpu?xgene1
 
 # Arch Matches
 MULTILIB_MATCHES       += march?armv8-a=march?armv8-a+crc
+MULTILIB_MATCHES       += march?armv8-a=march?armv8.1-a
+MULTILIB_MATCHES       += march?armv8-a=march?armv8.1-a+crc
 
 # FPU matches
 MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3
-- 
2.1.4

Re: [PATCH 3/7][ARM] Add patterns for new instructions

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 936 bytes --]

Ping. Updated patch attached.
Matthew

On 26/11/15 16:00, Matthew Wahab wrote:
> Hello,
>
> This patch adds patterns for the instructions, vqrdmlah and vqrdmlsh,
> introduced in the ARMv8.1 architecture. The instructions are made
> available when -march=armv8.1-a is enabled with suitable fpu settings,
> such as -mfpu=neon-fp-armv8 -mfloat-abi=hard.
>
> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
> bootstrap and make check.
>
> Ok for trunk?
> Matthew
>
> gcc/
> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>
>      * config/arm/iterators.md (VQRDMLH_AS): New.
>      (neon_rdma_as): New.
>      * config/arm/neon.md
>      (neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h<mode>): New.
>      (neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>): New.
>      * config/arm/unspecs.md (UNSPEC_VQRDMLAH): New.
>      (UNSPEC_VQRDMLSH): New.
>


[-- Attachment #2: 0003-ARM-Add-patterns-for-new-instructions.patch --]
[-- Type: text/x-patch, Size: 4066 bytes --]

From 8b69bae2f0057be09d3cbe3fe3c29155085e260d Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Wed, 17 Jun 2015 12:00:50 +0100
Subject: [PATCH 3/7] [ARM] Add patterns for new instructions.

Change-Id: Ia84c345019c7beda2d3c6c39074043d2e005347a
---
 gcc/config/arm/iterators.md |  5 +++++
 gcc/config/arm/neon.md      | 45 +++++++++++++++++++++++++++++++++++++++++++++
 gcc/config/arm/unspecs.md   |  2 ++
 3 files changed, 52 insertions(+)

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 6a54125..c7a6880 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -362,6 +362,8 @@
 (define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M
                                        UNSPEC_SHA1P])
 
+(define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH])
+
 ;;----------------------------------------------------------------------------
 ;; Mode attributes
 ;;----------------------------------------------------------------------------
@@ -831,3 +833,6 @@
                                (simple_return " && use_simple_return_p ()")])
 (define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)")
                                (simple_return " && use_simple_return_p ()")])
+
+;; Attributes for VQRDMLAH/VQRDMLSH
+(define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")])
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 62fb6da..844ef5e 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2014,6 +2014,18 @@
   [(set_attr "type" "neon_sat_mul_<V_elem_ch><q>")]
 )
 
+;; vqrdmlah, vqrdmlsh
+(define_insn "neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h<mode>"
+  [(set (match_operand:VMDQI 0 "s_register_operand" "=w")
+	(unspec:VMDQI [(match_operand:VMDQI 1 "s_register_operand" "0")
+		       (match_operand:VMDQI 2 "s_register_operand" "w")
+		       (match_operand:VMDQI 3 "s_register_operand" "w")]
+		      VQRDMLH_AS))]
+  "TARGET_NEON_RDMA"
+  "vqrdml<VQRDMLH_AS:neon_rdma_as>h.<V_s_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
+  [(set_attr "type" "neon_sat_mla_<V_elem_ch>_long")]
+)
+
 (define_insn "neon_vqdmlal<mode>"
   [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
         (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
@@ -3176,6 +3188,39 @@ if (BYTES_BIG_ENDIAN)
   [(set_attr "type" "neon_sat_mul_<V_elem_ch>_scalar_q")]
 )
 
+;; vqrdmlah_lane, vqrdmlsh_lane
+(define_insn "neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>"
+  [(set (match_operand:VMQI 0 "s_register_operand" "=w")
+	(unspec:VMQI [(match_operand:VMQI 1 "s_register_operand" "0")
+		      (match_operand:VMQI 2 "s_register_operand" "w")
+		      (match_operand:<V_HALF> 3 "s_register_operand"
+					  "<scalar_mul_constraint>")
+		      (match_operand:SI 4 "immediate_operand" "i")]
+		     VQRDMLH_AS))]
+  "TARGET_NEON_RDMA"
+{
+  return
+   "vqrdml<VQRDMLH_AS:neon_rdma_as>h.<V_s_elem>\t%q0, %q2, %P3[%c4]";
+}
+  [(set_attr "type" "neon_mla_<V_elem_ch>_scalar<q>")]
+)
+
+(define_insn "neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>"
+  [(set (match_operand:VMDI 0 "s_register_operand" "=w")
+	(unspec:VMDI [(match_operand:VMDI 1 "s_register_operand" "0")
+		      (match_operand:VMDI 2 "s_register_operand" "w")
+		      (match_operand:VMDI 3 "s_register_operand"
+					  "<scalar_mul_constraint>")
+		      (match_operand:SI 4 "immediate_operand" "i")]
+		     VQRDMLH_AS))]
+  "TARGET_NEON_RDMA"
+{
+  return
+   "vqrdml<VQRDMLH_AS:neon_rdma_as>h.<V_s_elem>\t%P0, %P2, %P3[%c4]";
+}
+  [(set_attr "type" "neon_mla_<V_elem_ch>_scalar")]
+)
+
 (define_insn "neon_vmla_lane<mode>"
   [(set (match_operand:VMD 0 "s_register_operand" "=w")
 	(unspec:VMD [(match_operand:VMD 1 "s_register_operand" "0")
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 67acafd..ffe703c 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -360,5 +360,7 @@
   UNSPEC_NVRINTX
   UNSPEC_NVRINTA
   UNSPEC_NVRINTN
+  UNSPEC_VQRDMLAH
+  UNSPEC_VQRDMLSH
 ])
 
-- 
2.1.4

Re: [PATCH 4/7][ARM] Add ACLE feature macro for ARMv8.1 instructions.

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 693 bytes --]

Ping. Updated patch attached.
Matthew


On 26/11/15 16:01, Matthew Wahab wrote:
> Hello,
>
> This patch adds the feature macro __ARM_FEATURE_QRDMX to indicate the
> presence of the ARMv8.1 instructions vqrdmlah and vqrdmlsh. It is
> defined when the instructions are available, as it is when
> -march=armv8.1-a is enabled with suitable fpu options.
>
> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
> bootstrap and make check.
>
> Ok for trunk?
> Matthew
>
> gcc/
> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>
>      * config/arm/arm-c.c (arm_cpu_builtins): Define __ARM_FEATURE_QRDMX.
>


[-- Attachment #2: 0004-ARM-Add-__ARM_FEATURE_QRDMX.patch --]
[-- Type: text/x-patch, Size: 770 bytes --]

From 721586aad45f7f75a0c198517602125c9d8f76f2 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Wed, 17 Jun 2015 13:25:09 +0100
Subject: [PATCH 4/7] [ARM] Add __ARM_FEATURE_QRDMX

Change-Id: I26cde507e8844a731e4fd857fbd30bf87f213f89
---
 gcc/config/arm/arm-c.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 7dee28e..62c9304 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -68,6 +68,9 @@ arm_cpu_builtins (struct cpp_reader* pfile)
 
   def_or_undef_macro (pfile, "__ARM_FEATURE_UNALIGNED", unaligned_access);
 
+  if (TARGET_NEON_RDMA)
+    builtin_define ("__ARM_FEATURE_QRDMX");
+
   if (TARGET_CRC32)
     builtin_define ("__ARM_FEATURE_CRC32");
 
-- 
2.1.4

Re: [PATCH 5/7][Testsuite] Support ARMv8.1 ARM tests.

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 1801 bytes --]

On 27/11/15 17:11, Matthew Wahab wrote:
> On 27/11/15 13:44, Christophe Lyon wrote:
>>> On 26/11/15 16:02, Matthew Wahab wrote:
>
>>>> This patch adds ARMv8.1 support to GCC Dejagnu, to allow ARM
>>>> tests to specify targest and to set up command line options.
>>>> It builds on the ARMv8.1 target support added for AArch64 tests, partly
>>>> reworking that support to take into account the different configurations
>>>> that tests may be run under.
>
>> I may be mistaken, but -mfpu=neon-fp-armv8 and -mfloat-abi=softfp are not
>> supported by aarch64-gcc. So it seems to me that
>> check_effective_target_arm_v8_1a_neon_ok_nocache will not always work
>> for aarch64 after your patch.
>
>> Or does it work because no option is needed and thus "" always
>> matches and thus the loop always exits after the first iteration
>> on aarch64?
>
> Yes, the idea is that the empty string will make the function first try
> '-march=armv8.1-a' without any other flag. That will work for AArch64 because it
> doesn't need any other option.
>
>> Maybe a more accurate comment would help remembering that, in case
>> -mfpu option becomes necessary for aarch64.
>>
>
> Agreed, it's worth having a comment to explain what the 'foreach' construct is doing.
>
> Matthew

I've added a comment to the foreach construct, to make it clearer what
it's doing.

Matthew

testsuite/
2015-12-07  Matthew Wahab  <matthew.wahab@arm.com>

	* lib/target-supports.exp (add_options_for_arm_v8_1a_neon): Update
	comment.  Use check_effetive_target_arm_v8_1a_neon_ok to select
	the command line options.
	(check_effective_target_arm_v8_1a_neon_ok_nocache): Update initial
	test to allow ARM targets.  Select and record a working set of
	command line options.
	(check_effective_target_arm_v8_1a_neon_hw): Add tests for ARM
	targets.


[-- Attachment #2: 0005-Testsuite-Support-ARMv8.1-NEON-on-ARM.patch --]
[-- Type: text/x-patch, Size: 3888 bytes --]

From 7e2cd1ef475a5c7f4a4722b9ba32bd46e3b30eae Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Fri, 9 Oct 2015 17:38:12 +0100
Subject: [PATCH 5/7] [Testsuite] Support ARMv8.1 NEON on ARM.

---
 gcc/testsuite/lib/target-supports.exp | 60 ++++++++++++++++++++++++++---------
 1 file changed, 45 insertions(+), 15 deletions(-)

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 4e349e9..6dfb6f6 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2816,14 +2816,15 @@ proc add_options_for_arm_v8_neon { flags } {
     return "$flags $et_arm_v8_neon_flags -march=armv8-a"
 }
 
-# Add the options needed for ARMv8.1 Adv.SIMD.
+# Add the options needed for ARMv8.1 Adv.SIMD.  Also adds the ARMv8 NEON
+# options for AArch64 and for ARM.
 
 proc add_options_for_arm_v8_1a_neon { flags } {
-    if { [istarget aarch64*-*-*] } {
-	return "$flags -march=armv8.1-a"
-    } else {
+    if { ! [check_effective_target_arm_v8_1a_neon_ok] } {
 	return "$flags"
     }
+    global et_arm_v8_1a_neon_flags
+    return "$flags $et_arm_v8_1a_neon_flags -march=armv8.1-a"
 }
 
 proc add_options_for_arm_crc { flags } {
@@ -3271,17 +3272,33 @@ proc check_effective_target_arm_neonv2_hw { } {
 }
 
 # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0
-# otherwise.  The test is valid for AArch64.
+# otherwise.  The test is valid for AArch64 and ARM.  Record the command
+# line options that needed.
 
 proc check_effective_target_arm_v8_1a_neon_ok_nocache { } {
-    if { ![istarget aarch64*-*-*] } {
-	return 0
+    global et_arm_v8_1a_neon_flags
+    set et_arm_v8_1a_neon_flags ""
+
+    if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
+	return 0;
     }
-    return [check_no_compiler_messages_nocache arm_v8_1a_neon_ok assembly {
-	#if !defined (__ARM_FEATURE_QRDMX)
-	#error "__ARM_FEATURE_QRDMX not defined"
-	#endif
-    } [add_options_for_arm_v8_1a_neon ""]]
+
+    # Iterate through sets of options to find the compiler flags that
+    # need to be added to the -march option.  Start with the empty set
+    # since AArch64 only needs the -march setting.
+    foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
+		       "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
+	if { [check_no_compiler_messages_nocache arm_v8_1a_neon_ok object {
+	    #if !defined (__ARM_FEATURE_QRDMX)
+	    #error "__ARM_FEATURE_QRDMX not defined"
+	    #endif
+	} "$flags -march=armv8.1-a"] } {
+	    set et_arm_v8_1a_neon_flags "$flags -march=armv8.1-a"
+	    return 1
+	}
+    }
+
+    return 0;
 }
 
 proc check_effective_target_arm_v8_1a_neon_ok { } {
@@ -3308,16 +3325,17 @@ proc check_effective_target_arm_v8_neon_hw { } {
 }
 
 # Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0
-# otherwise.  The test is valid for AArch64.
+# otherwise.  The test is valid for AArch64 and ARM.
 
 proc check_effective_target_arm_v8_1a_neon_hw { } {
     if { ![check_effective_target_arm_v8_1a_neon_ok] } {
 	return 0;
     }
-    return [check_runtime_nocache arm_v8_1a_neon_hw_available {
+    return [check_runtime arm_v8_1a_neon_hw_available {
 	int
 	main (void)
 	{
+	  #ifdef __ARM_ARCH_ISA_A64
 	  __Int32x2_t a = {0, 1};
 	  __Int32x2_t b = {0, 2};
 	  __Int32x2_t result;
@@ -3327,9 +3345,21 @@ proc check_effective_target_arm_v8_1a_neon_hw { } {
 	       : "w"(a), "w"(b)
 	       : /* No clobbers.  */);
 
+	  #else
+
+	  __simd64_int32_t a = {0, 1};
+	  __simd64_int32_t b = {0, 2};
+	  __simd64_int32_t result;
+
+	  asm ("vqrdmlah.s32 %P0, %P1, %P2"
+	       : "=w"(result)
+	       : "w"(a), "w"(b)
+	       : /* No clobbers.  */);
+	  #endif
+
 	  return result[0];
 	}
-    }  [add_options_for_arm_v8_1a_neon ""]]
+    } [add_options_for_arm_v8_1a_neon ""]]
 }
 
 # Return 1 if this is a ARM target with NEON enabled.
-- 
2.1.4

Re: [PATCH 6/7][ARM] Add ACLE intrinsics vqrdmlah and vqrdmlsh

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 959 bytes --]

Ping. Updated patch attached.
Matthew

On 26/11/15 16:04, Matthew Wahab wrote:
> Hello,
>
> This patch adds the ACLE intrinsics for the instructions introduced in
> ARMv8.1. It adds the vqrmdlah and vqrdmlsh forms of the instrinsics to
> the arm_neon.h header, together with the ARM builtins used to implement
> them. The intrinsics are available when -march=armv8.1-a is enabled
> together with appropriate fpu options.
>
> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
> bootstrap and make check.
>
> Ok for trunk?
> Matthew
>
> gcc/
> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>
>      * config/arm/arm_neon.h (vqrdmlah_s16, vqrdmlah_s32): New.
>      (vqrdmlahq_s16, vqrdmlahq_s32): New.
>      (vqrdmlsh_s16, vqrdmlsh_s32): New.
>      (vqrdmlahq_s16, vqrdmlshq_s32): New.
>      * config/arm/arm_neon_builtins.def: Add "vqrdmlah" and "vqrdmlsh".
>


[-- Attachment #2: 0006-ARM-Add-neon-intrinsics-vqrdmlah-vqrdmlsh.patch --]
[-- Type: text/x-patch, Size: 3199 bytes --]

From 1844027592d818e0de53a3da904ae6bfe1aef534 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Tue, 1 Sep 2015 16:21:44 +0100
Subject: [PATCH 6/7] [ARM] Add neon intrinsics vqrdmlah, vqrdmlsh.

Change-Id: Ic40ff4d477f36ec01714c68e3b83b66208c7958b
---
 gcc/config/arm/arm_neon.h            | 50 ++++++++++++++++++++++++++++++++++++
 gcc/config/arm/arm_neon_builtins.def |  2 ++
 2 files changed, 52 insertions(+)

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 0a33d21..b617f80 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -1158,6 +1158,56 @@ vqrdmulhq_s32 (int32x4_t __a, int32x4_t __b)
   return (int32x4_t)__builtin_neon_vqrdmulhv4si (__a, __b);
 }
 
+#ifdef __ARM_FEATURE_QRDMX
+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+vqrdmlah_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+{
+  return (int16x4_t)__builtin_neon_vqrdmlahv4hi (__a, __b, __c);
+}
+
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vqrdmlah_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+  return (int32x2_t)__builtin_neon_vqrdmlahv2si (__a, __b, __c);
+}
+
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vqrdmlahq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+{
+  return (int16x8_t)__builtin_neon_vqrdmlahv8hi (__a, __b, __c);
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vqrdmlahq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return (int32x4_t)__builtin_neon_vqrdmlahv4si (__a, __b, __c);
+}
+
+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+vqrdmlsh_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+{
+  return (int16x4_t)__builtin_neon_vqrdmlshv4hi (__a, __b, __c);
+}
+
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vqrdmlsh_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+  return (int32x2_t)__builtin_neon_vqrdmlshv2si (__a, __b, __c);
+}
+
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vqrdmlshq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+{
+  return (int16x8_t)__builtin_neon_vqrdmlshv8hi (__a, __b, __c);
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vqrdmlshq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return (int32x4_t)__builtin_neon_vqrdmlshv4si (__a, __b, __c);
+}
+#endif
+
 __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
 vmull_s8 (int8x8_t __a, int8x8_t __b)
 {
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 0b719df..8d5c0ca 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -45,6 +45,8 @@ VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si)
 VAR4 (BINOP, vqrdmulh, v4hi, v2si, v8hi, v4si)
 VAR2 (TERNOP, vqdmlal, v4hi, v2si)
 VAR2 (TERNOP, vqdmlsl, v4hi, v2si)
+VAR4 (TERNOP, vqrdmlah, v4hi, v2si, v8hi, v4si)
+VAR4 (TERNOP, vqrdmlsh, v4hi, v2si, v8hi, v4si)
 VAR3 (BINOP, vmullp, v8qi, v4hi, v2si)
 VAR3 (BINOP, vmulls, v8qi, v4hi, v2si)
 VAR3 (BINOP, vmullu, v8qi, v4hi, v2si)
-- 
2.1.4

Re: [PATCH 7/7][ARM] Add ACLE intrinsics vqrdmlah_lane and vqrdmlsh_lane

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 1197 bytes --]

Ping. Updated patch attached.
Matthew

On 26/11/15 16:10, Matthew Wahab wrote:
> Attached the missing patch.
> Matthew
>
> On 26/11/15 16:04, Matthew Wahab wrote:
>> Hello,
>>
>> This patch adds the ACLE intrinsics for the instructions introduced in
>> ARMv8.1. It adds the vqrmdlah_lane and vqrdmlsh_lane forms of the
>> instrinsics to the arm_neon.h header, together with the ARM builtins
>> used to implement them. The intrinsics are available when
>> -march=armv8.1-a is enabled together with appropriate fpu options.
>>
>> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
>> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
>> bootstrap and make check.
>>
>> Ok for trunk?
>> Matthew
>>
>> gcc/
>> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>>
>>      * config/arm/arm_neon.h (vqrdmlahq_lane_s16): New.
>>      (vqrdmlahq_lane_s32): New.
>>      (vqrdmlah_lane_s16): New.
>>      (vqrdmlah_lane_s32): New.
>>      (vqrdmlshq_lane_s16): New.
>>      (vqrdmlshq_lane_s32): New.
>>      (vqrdmlsh_lane_s16): New.
>>      (vqrdmlsh_lane_s32): New.
>>      * config/arm/arm_neon_builtins.def: Add "vqrdmlah_lane" and
>>      "vqrdmlsh_lane".
>>
>


[-- Attachment #2: 0007-ARM-Add-neon-intrinsics-vqrdmlah_lane-vqrdmlsh_lane.patch --]
[-- Type: text/x-patch, Size: 3586 bytes --]

From 9928f1e8e30c500933fa68f95311cf0f78dd6712 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Tue, 1 Sep 2015 16:22:34 +0100
Subject: [PATCH 7/7] [ARM] Add neon intrinsics vqrdmlah_lane, vqrdmlsh_lane.

Change-Id: Ia0ab4bbe683af2d019d18a34302a7b9798193a79
---
 gcc/config/arm/arm_neon.h            | 50 ++++++++++++++++++++++++++++++++++++
 gcc/config/arm/arm_neon_builtins.def |  2 ++
 2 files changed, 52 insertions(+)

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index b617f80..ed50253 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -7096,6 +7096,56 @@ vqrdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
   return (int32x2_t)__builtin_neon_vqrdmulh_lanev2si (__a, __b, __c);
 }
 
+#ifdef __ARM_FEATURE_QRDMX
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vqrdmlahq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
+{
+  return (int16x8_t)__builtin_neon_vqrdmlah_lanev8hi (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vqrdmlahq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
+{
+  return (int32x4_t)__builtin_neon_vqrdmlah_lanev4si (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+vqrdmlah_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+{
+  return (int16x4_t)__builtin_neon_vqrdmlah_lanev4hi (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vqrdmlah_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+{
+  return (int32x2_t)__builtin_neon_vqrdmlah_lanev2si (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vqrdmlshq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
+{
+  return (int16x8_t)__builtin_neon_vqrdmlsh_lanev8hi (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vqrdmlshq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
+{
+  return (int32x4_t)__builtin_neon_vqrdmlsh_lanev4si (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+vqrdmlsh_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+{
+  return (int16x4_t)__builtin_neon_vqrdmlsh_lanev4hi (__a, __b, __c, __d);
+}
+
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vqrdmlsh_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+{
+  return (int32x2_t)__builtin_neon_vqrdmlsh_lanev2si (__a, __b, __c, __d);
+}
+#endif
+
 __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
 vmul_n_s16 (int16x4_t __a, int16_t __b)
 {
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 8d5c0ca..1fdb2a8 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -60,6 +60,8 @@ VAR4 (BINOP, vqdmulh_n, v4hi, v2si, v8hi, v4si)
 VAR4 (BINOP, vqrdmulh_n, v4hi, v2si, v8hi, v4si)
 VAR4 (SETLANE, vqdmulh_lane, v4hi, v2si, v8hi, v4si)
 VAR4 (SETLANE, vqrdmulh_lane, v4hi, v2si, v8hi, v4si)
+VAR4 (MAC_LANE, vqrdmlah_lane, v4hi, v2si, v8hi, v4si)
+VAR4 (MAC_LANE, vqrdmlsh_lane, v4hi, v2si, v8hi, v4si)
 VAR2 (BINOP, vqdmull, v4hi, v2si)
 VAR8 (BINOP, vshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
 VAR8 (BINOP, vshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
-- 
2.1.4

Re: [PATCH 4/7][ARM] Add ACLE feature macro for ARMv8.1 instructions.

[Christian Bruel]

Hi Matthew,

On 12/07/2015 05:07 PM, Matthew Wahab wrote:
> Ping. Updated patch attached.
> Matthew
>
>
> On 26/11/15 16:01, Matthew Wahab wrote:
>> Hello,
>>
>> This patch adds the feature macro __ARM_FEATURE_QRDMX to indicate the
>> presence of the ARMv8.1 instructions vqrdmlah and vqrdmlsh. It is
>> defined when the instructions are available, as it is when
>> -march=armv8.1-a is enabled with suitable fpu options.
>>
>> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
>> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
>> bootstrap and make check.
>>
>> Ok for trunk?
>> Matthew
>>
>> gcc/
>> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>>
>>       * config/arm/arm-c.c (arm_cpu_builtins): Define __ARM_FEATURE_QRDMX.
>>
>

+  if (TARGET_NEON_RDMA)
+    builtin_define ("__ARM_FEATURE_QRDMX");
+

Since it depends on TARGET_NEON, could you please use

   def_or_undef_macro (pfile, "__ARM_FEATURE_QRDMX", TARGET_NEON_RDMA);

instead ?

thanks

Christian

Re: [PATCH 5/7][Testsuite] Support ARMv8.1 ARM tests.

[Christophe Lyon]

On 7 December 2015 at 17:10, Matthew Wahab <matthew.wahab@foss.arm.com> wrote:
> On 27/11/15 17:11, Matthew Wahab wrote:
>>
>> On 27/11/15 13:44, Christophe Lyon wrote:
>>>>
>>>> On 26/11/15 16:02, Matthew Wahab wrote:
>>
>>
>>>>> This patch adds ARMv8.1 support to GCC Dejagnu, to allow ARM
>>>>> tests to specify targest and to set up command line options.
>>>>> It builds on the ARMv8.1 target support added for AArch64 tests, partly
>>>>> reworking that support to take into account the different
>>>>> configurations
>>>>> that tests may be run under.
>>
>>
>>> I may be mistaken, but -mfpu=neon-fp-armv8 and -mfloat-abi=softfp are not
>>> supported by aarch64-gcc. So it seems to me that
>>> check_effective_target_arm_v8_1a_neon_ok_nocache will not always work
>>> for aarch64 after your patch.
>>
>>
>>> Or does it work because no option is needed and thus "" always
>>> matches and thus the loop always exits after the first iteration
>>> on aarch64?
>>
>>
>> Yes, the idea is that the empty string will make the function first try
>> '-march=armv8.1-a' without any other flag. That will work for AArch64
>> because it
>> doesn't need any other option.
>>
>>> Maybe a more accurate comment would help remembering that, in case
>>> -mfpu option becomes necessary for aarch64.
>>>
>>
>> Agreed, it's worth having a comment to explain what the 'foreach'
>> construct is doing.
>>
>> Matthew
>
>
> I've added a comment to the foreach construct, to make it clearer what
> it's doing.
>

I only have a minor typo to report in the other comment you added before
check_effective_target_arm_v8_1a_neon_ok_nocache:
"Record the command line options that needed."
("that" doesn't sound right to my non-native ears :-)

Otherwise OK for me, but I can't approve.

Christophe.


> Matthew
>
> testsuite/
> 2015-12-07  Matthew Wahab  <matthew.wahab@arm.com>
>
>
>         * lib/target-supports.exp (add_options_for_arm_v8_1a_neon): Update
>         comment.  Use check_effetive_target_arm_v8_1a_neon_ok to select
>         the command line options.
>         (check_effective_target_arm_v8_1a_neon_ok_nocache): Update initial
>         test to allow ARM targets.  Select and record a working set of
>         command line options.
>         (check_effective_target_arm_v8_1a_neon_hw): Add tests for ARM
>         targets.
>

Re: [PATCH 1/7][ARM] Add support for ARMv8.1.

[Ramana Radhakrishnan]

On Mon, Dec 7, 2015 at 4:04 PM, Matthew Wahab
<matthew.wahab@foss.arm.com> wrote:
> Ping. Updated patch attached.
> Matthew
>
>
> On 26/11/15 15:55, Matthew Wahab wrote:
>>
>> Hello,
>>
>>
>> ARMv8.1 includes an extension to ARM which adds two Adv.SIMD
>> instructions, vqrdmlah and vqrdmlsh. This patch set adds support for
>> ARMv8.1 and for the new instructions, enabling the architecture with
>> --march=armv8.1-a. The new instructions are enabled when both ARMv8.1
>> and a suitable fpu options are set, for instance with -march=armv8.1-a
>> -mfpu=neon-fp-armv8 -mfloat-abi=hard.
>>
>> This patch set adds the command line options and internal feature
>> macros. Following patches
>> - enable multilib support for ARMv8.1,
>> - add patterns for the new instructions,
>> - add the ACLE feature macro for the ARMv8.1 extensions,
>> - extend target support in the testsuite to ARMv8.1,
>> - add the ACLE intrinsics for vqrmdl{as}h and
>> - add the ACLE intrinsics for vqrmdl{as}h_lane.
>>
>> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
>> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
>> bootstrap and make check.
>>
>> Is this ok for trunk?
>> Matthew
>>
>> gcc/
>> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>>
>>      * config/arm/arm-arches.def: Add "armv8.1-a" and "armv8.1-a+crc".
>>      * config/arm/arm-protos.h (FL2_ARCH8_1): New.
>>      (FL2_FOR_ARCH8_1A): New.
>>      * config/arm/arm-tables.opt: Regenerate.
>>      * config/arm/arm.c (arm_arch8_1): New.
>>      (arm_option_override): Set arm_arch8_1.
>>      * config/arm/arm.h (TARGET_NEON_RDMA): New.
>>      (arm_arch8_1): Declare.
>>      * doc/invoke.texi (ARM Options, -march): Add "armv8.1-a" and
>>      "armv8.1-a+crc".
>>      (ARM Options, -mfpu): Fix a typo.
>
>

OK.

Re: [PATCH 2/7][ARM] Multilib support for ARMv8.1.

[Ramana Radhakrishnan]

On Mon, Dec 7, 2015 at 4:05 PM, Matthew Wahab
<matthew.wahab@foss.arm.com> wrote:
> Ping. Updated patch attached.
> Matthew
>
>
> On 26/11/15 15:58, Matthew Wahab wrote:
>>
>> This patch sets up multilib support for ARMv8.1, treating it as a
>> synonym for ARMv8. Since ARMv8.1 integer, FP or SIMD
>> instructions are only generated for the new, instruction-specific
>> instrinsics, mapping to ARMv8 rather than adding a new multilib variant
>> is sufficient.
>>
>> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
>> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
>> bootstrap and make check.
>>
>> Ok for trunk?
>> Matthew
>>
>> gcc/
>> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>>
>>      * config/arm/t-aprofile: Make "armv8.1-a" and "armv8.1-a+crc"
>>      matches for "armv8-a".
>>


OK.

Ramana
>

Re: [PATCH 3/7][ARM] Add patterns for new instructions

[Ramana Radhakrishnan]

On Mon, Dec 7, 2015 at 4:06 PM, Matthew Wahab
<matthew.wahab@foss.arm.com> wrote:
> Ping. Updated patch attached.
> Matthew
>
>
> On 26/11/15 16:00, Matthew Wahab wrote:
>>
>> Hello,
>>
>> This patch adds patterns for the instructions, vqrdmlah and vqrdmlsh,
>> introduced in the ARMv8.1 architecture. The instructions are made
>> available when -march=armv8.1-a is enabled with suitable fpu settings,
>> such as -mfpu=neon-fp-armv8 -mfloat-abi=hard.
>>
>> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
>> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
>> bootstrap and make check.
>>
>> Ok for trunk?
>> Matthew

OK.

Ramana

>>
>> gcc/
>> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>>
>>      * config/arm/iterators.md (VQRDMLH_AS): New.
>>      (neon_rdma_as): New.
>>      * config/arm/neon.md
>>      (neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h<mode>): New.
>>      (neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>): New.
>>      * config/arm/unspecs.md (UNSPEC_VQRDMLAH): New.
>>      (UNSPEC_VQRDMLSH): New.
>>
>

Re: [PATCH 4/7][ARM] Add ACLE feature macro for ARMv8.1 instructions.

[Ramana Radhakrishnan]

On Tue, Dec 8, 2015 at 7:45 AM, Christian Bruel <christian.bruel@st.com> wrote:
> Hi Matthew,
>
>
> On 12/07/2015 05:07 PM, Matthew Wahab wrote:
>>
>> Ping. Updated patch attached.
>> Matthew
>>
>>
>> On 26/11/15 16:01, Matthew Wahab wrote:
>>>
>>> Hello,
>>>
>>> This patch adds the feature macro __ARM_FEATURE_QRDMX to indicate the
>>> presence of the ARMv8.1 instructions vqrdmlah and vqrdmlsh. It is
>>> defined when the instructions are available, as it is when
>>> -march=armv8.1-a is enabled with suitable fpu options.
>>>
>>> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
>>> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
>>> bootstrap and make check.
>>>
>>> Ok for trunk?
>>> Matthew
>>>
>>> gcc/
>>> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>>>
>>>       * config/arm/arm-c.c (arm_cpu_builtins): Define
>>> __ARM_FEATURE_QRDMX.
>>>
>>
>
> +  if (TARGET_NEON_RDMA)
> +    builtin_define ("__ARM_FEATURE_QRDMX");
> +
>
> Since it depends on TARGET_NEON, could you please use
>
>   def_or_undef_macro (pfile, "__ARM_FEATURE_QRDMX", TARGET_NEON_RDMA);
>
> instead ?

I think that's what it should be -

OK with that fixed.

Ramana


>
> thanks
>
> Christian

Re: [PATCH 5/7][Testsuite] Support ARMv8.1 ARM tests.

[Ramana Radhakrishnan]

On Mon, Dec 7, 2015 at 4:10 PM, Matthew Wahab
<matthew.wahab@foss.arm.com> wrote:
> On 27/11/15 17:11, Matthew Wahab wrote:
>>
>> On 27/11/15 13:44, Christophe Lyon wrote:
>>>>
>>>> On 26/11/15 16:02, Matthew Wahab wrote:
>>
>>
>>>>> This patch adds ARMv8.1 support to GCC Dejagnu, to allow ARM
>>>>> tests to specify targest and to set up command line options.
>>>>> It builds on the ARMv8.1 target support added for AArch64 tests, partly
>>>>> reworking that support to take into account the different
>>>>> configurations
>>>>> that tests may be run under.
>>
>>
>>> I may be mistaken, but -mfpu=neon-fp-armv8 and -mfloat-abi=softfp are not
>>> supported by aarch64-gcc. So it seems to me that
>>> check_effective_target_arm_v8_1a_neon_ok_nocache will not always work
>>> for aarch64 after your patch.
>>
>>
>>> Or does it work because no option is needed and thus "" always
>>> matches and thus the loop always exits after the first iteration
>>> on aarch64?
>>
>>
>> Yes, the idea is that the empty string will make the function first try
>> '-march=armv8.1-a' without any other flag. That will work for AArch64
>> because it
>> doesn't need any other option.
>>
>>> Maybe a more accurate comment would help remembering that, in case
>>> -mfpu option becomes necessary for aarch64.
>>>
>>
>> Agreed, it's worth having a comment to explain what the 'foreach'
>> construct is doing.
>>
>> Matthew
>
>
> I've added a comment to the foreach construct, to make it clearer what
> it's doing.
>
> Matthew
>
> testsuite/
> 2015-12-07  Matthew Wahab  <matthew.wahab@arm.com>
>
>
>         * lib/target-supports.exp (add_options_for_arm_v8_1a_neon): Update
>         comment.  Use check_effetive_target_arm_v8_1a_neon_ok to select
>         the command line options.
>         (check_effective_target_arm_v8_1a_neon_ok_nocache): Update initial
>         test to allow ARM targets.  Select and record a working set of
>         command line options.
>         (check_effective_target_arm_v8_1a_neon_hw): Add tests for ARM
>         targets.
>


># Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0
>-# otherwise.  The test is valid for AArch64.
>+# otherwise.  The test is valid for AArch64 and ARM.  Record the command
>+# line options that needed.

s/that//

Can you also make sure doc/sourcebuild.texi is updated for this helper
function ? If not documented,it would be good to add the documentation
for the same while you are here.

Ramana

Re: [PATCH 7/7][ARM] Add ACLE intrinsics vqrdmlah_lane and vqrdmlsh_lane

[Ramana Radhakrishnan]

On Thu, Nov 26, 2015 at 4:04 PM, Matthew Wahab
<matthew.wahab@foss.arm.com> wrote:
> Hello,
>
> This patch adds the ACLE intrinsics for the instructions introduced in
> ARMv8.1. It adds the vqrmdlah_lane and vqrdmlsh_lane forms of the
> instrinsics to the arm_neon.h header, together with the ARM builtins
> used to implement them. The intrinsics are available when
> -march=armv8.1-a is enabled together with appropriate fpu options.
>
> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
> bootstrap and make check.
>
> Ok for trunk?
> Matthew
>
> gcc/
> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>
>         * config/arm/arm_neon.h (vqrdmlahq_lane_s16): New.
>         (vqrdmlahq_lane_s32): New.
>         (vqrdmlah_lane_s16): New.
>         (vqrdmlah_lane_s32): New.
>         (vqrdmlshq_lane_s16): New.
>         (vqrdmlshq_lane_s32): New.
>         (vqrdmlsh_lane_s16): New.
>         (vqrdmlsh_lane_s32): New.
>         * config/arm/arm_neon_builtins.def: Add "vqrdmlah_lane" and
>         "vqrdmlsh_lane".
>

OK.

Ramana

Re: [PATCH 6/7][ARM] Add ACLE intrinsics vqrdmlah and vqrdmlsh

[Ramana Radhakrishnan]

On Mon, Dec 7, 2015 at 4:12 PM, Matthew Wahab
<matthew.wahab@foss.arm.com> wrote:
> Ping. Updated patch attached.
> Matthew
>
>
> On 26/11/15 16:04, Matthew Wahab wrote:
>>
>> Hello,
>>
>> This patch adds the ACLE intrinsics for the instructions introduced in
>> ARMv8.1. It adds the vqrmdlah and vqrdmlsh forms of the instrinsics to
>> the arm_neon.h header, together with the ARM builtins used to implement
>> them. The intrinsics are available when -march=armv8.1-a is enabled
>> together with appropriate fpu options.
>>
>> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
>> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
>> bootstrap and make check.
>>
>> Ok for trunk?
>> Matthew
>>
>> gcc/
>> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>>
>>      * config/arm/arm_neon.h (vqrdmlah_s16, vqrdmlah_s32): New.
>>      (vqrdmlahq_s16, vqrdmlahq_s32): New.
>>      (vqrdmlsh_s16, vqrdmlsh_s32): New.
>>      (vqrdmlahq_s16, vqrdmlshq_s32): New.
>>      * config/arm/arm_neon_builtins.def: Add "vqrdmlah" and "vqrdmlsh".
>>
>


OK.

Ramana

Re: [PATCH 1/7][ARM] Add support for ARMv8.1.

[Ramana Radhakrishnan]

On Thu, Dec 10, 2015 at 10:43 AM, Ramana Radhakrishnan
<ramana.gcc@googlemail.com> wrote:
> On Mon, Dec 7, 2015 at 4:04 PM, Matthew Wahab
> <matthew.wahab@foss.arm.com> wrote:
>> Ping. Updated patch attached.
>> Matthew
>>
>>
>> On 26/11/15 15:55, Matthew Wahab wrote:
>>>
>>> Hello,
>>>
>>>
>>> ARMv8.1 includes an extension to ARM which adds two Adv.SIMD
>>> instructions, vqrdmlah and vqrdmlsh. This patch set adds support for
>>> ARMv8.1 and for the new instructions, enabling the architecture with
>>> --march=armv8.1-a. The new instructions are enabled when both ARMv8.1
>>> and a suitable fpu options are set, for instance with -march=armv8.1-a
>>> -mfpu=neon-fp-armv8 -mfloat-abi=hard.
>>>
>>> This patch set adds the command line options and internal feature
>>> macros. Following patches
>>> - enable multilib support for ARMv8.1,
>>> - add patterns for the new instructions,
>>> - add the ACLE feature macro for the ARMv8.1 extensions,
>>> - extend target support in the testsuite to ARMv8.1,
>>> - add the ACLE intrinsics for vqrmdl{as}h and
>>> - add the ACLE intrinsics for vqrmdl{as}h_lane.
>>>
>>> Tested the series for arm-none-eabi with cross-compiled check-gcc on an
>>> ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native
>>> bootstrap and make check.
>>>
>>> Is this ok for trunk?
>>> Matthew
>>>
>>> gcc/
>>> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>>>
>>>      * config/arm/arm-arches.def: Add "armv8.1-a" and "armv8.1-a+crc".
>>>      * config/arm/arm-protos.h (FL2_ARCH8_1): New.
>>>      (FL2_FOR_ARCH8_1A): New.
>>>      * config/arm/arm-tables.opt: Regenerate.
>>>      * config/arm/arm.c (arm_arch8_1): New.
>>>      (arm_option_override): Set arm_arch8_1.
>>>      * config/arm/arm.h (TARGET_NEON_RDMA): New.
>>>      (arm_arch8_1): Declare.
>>>      * doc/invoke.texi (ARM Options, -march): Add "armv8.1-a" and
>>>      "armv8.1-a+crc".
>>>      (ARM Options, -mfpu): Fix a typo.
>>
>>
>
> OK.

I couldn't find 0/7 but in addition here you need to update the output
for TAG_FP_SIMD_Arch to be 4.

regards
Ramana

Re: [PATCH 4/7][ARM] Add ACLE feature macro for ARMv8.1 instructions.

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 1267 bytes --]

On 10/12/15 10:45, Ramana Radhakrishnan wrote:
> On Tue, Dec 8, 2015 at 7:45 AM, Christian Bruel <christian.bruel@st.com> wrote:
>> Hi Matthew,
>>>
>>> On 26/11/15 16:01, Matthew Wahab wrote:
>>>>
>>>> Hello,
>>>>
>>>> This patch adds the feature macro __ARM_FEATURE_QRDMX to indicate the
>>>> presence of the ARMv8.1 instructions vqrdmlah and vqrdmlsh. It is
>>>> defined when the instructions are available, as it is when
>>>> -march=armv8.1-a is enabled with suitable fpu options.
>>>>
>>>> gcc/
>>>> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>>>>
>>>>        * config/arm/arm-c.c (arm_cpu_builtins): Define
>>>> __ARM_FEATURE_QRDMX.
>>>>
>>>
>>
>> +  if (TARGET_NEON_RDMA)
>> +    builtin_define ("__ARM_FEATURE_QRDMX");
>> +
>>
>> Since it depends on TARGET_NEON, could you please use
>>
>>    def_or_undef_macro (pfile, "__ARM_FEATURE_QRDMX", TARGET_NEON_RDMA);
>>
>> instead ?
>
> I think that's what it should be -
>
> OK with that fixed.

Attached an updated patch using the def_or_undef macro. It also removes some trailing 
whitespace in that part of the code.

Still ok?
Matthew

gcc/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* config/arm/arm-c.c (arm_cpu_builtins): Define
	__ARM_FEATURE_QRDMX.  Clean up some trailing whitespace.



[-- Attachment #2: 0004-ARM-Add-__ARM_FEATURE_QRDMX.patch --]
[-- Type: text/x-patch, Size: 1487 bytes --]

From 8cce5cd7b6d89c49dcf694a5c72ab0ed7c26fe20 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Wed, 17 Jun 2015 13:25:09 +0100
Subject: [PATCH 4/7] [ARM] Add __ARM_FEATURE_QRDMX

---
 gcc/config/arm/arm-c.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 7dee28e..a980ed8 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -62,19 +62,21 @@ static void
 arm_cpu_builtins (struct cpp_reader* pfile)
 {
   def_or_undef_macro (pfile, "__ARM_FEATURE_DSP", TARGET_DSP_MULTIPLY);
-  def_or_undef_macro (pfile, "__ARM_FEATURE_QBIT", TARGET_ARM_QBIT); 
+  def_or_undef_macro (pfile, "__ARM_FEATURE_QBIT", TARGET_ARM_QBIT);
   def_or_undef_macro (pfile, "__ARM_FEATURE_SAT", TARGET_ARM_SAT);
   def_or_undef_macro (pfile, "__ARM_FEATURE_CRYPTO", TARGET_CRYPTO);
 
   def_or_undef_macro (pfile, "__ARM_FEATURE_UNALIGNED", unaligned_access);
 
+  def_or_undef_macro (pfile, "__ARM_FEATURE_QRDMX", TARGET_NEON_RDMA);
+
   if (TARGET_CRC32)
     builtin_define ("__ARM_FEATURE_CRC32");
 
-  def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT); 
+  def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT);
 
   if (TARGET_ARM_FEATURE_LDREX)
-    builtin_define_with_int_value ("__ARM_FEATURE_LDREX", 
+    builtin_define_with_int_value ("__ARM_FEATURE_LDREX",
 				   TARGET_ARM_FEATURE_LDREX);
   else
     cpp_undef (pfile, "__ARM_FEATURE_LDREX");
-- 
2.1.4

Re: [PATCH 5/7][Testsuite] Support ARMv8.1 ARM tests.

[Matthew Wahab]

[-- Attachment #1: Type: text/plain, Size: 1942 bytes --]

On 10/12/15 10:49, Ramana Radhakrishnan wrote:
> On Mon, Dec 7, 2015 at 4:10 PM, Matthew Wahab <matthew.wahab@foss.arm.com> wrote:
>> On 27/11/15 17:11, Matthew Wahab wrote:
>>> On 27/11/15 13:44, Christophe Lyon wrote:
>>>>> On 26/11/15 16:02, Matthew Wahab wrote
>>>
>>>>>> This patch adds ARMv8.1 support to GCC Dejagnu, to allow ARM tests to
>>>>>> specify targest and to set up command line options. It builds on the
>>>>>> ARMv8.1 target support added for AArch64 tests, partly reworking that
>>>>>> support to take into account the different configurations that tests may
>>>>>> be run under.
[..]
>> # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0 -#
>> otherwise.  The test is valid for AArch64. +# otherwise.  The test is valid for
>> AArch64 and ARM.  Record the command +# line options that needed.
>
> s/that//

Fixed in attached patch.

> Can you also make sure doc/sourcebuild.texi is updated for this helper function ?
> If not documented,it would be good to add the documentation for the same while you
> are here.

Done, I've listed them as ARM attributes based on their names.

Tested this and the other update patch (#4/7) for arm-none-eabi with cross-compiled
check-gcc by running the gcc.target/aarch64/advsimd-intrinsics with and without 
ARMv8.1 enabled as a test target.

Ok?
Matthew

testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* lib/target-supports.exp (add_options_for_arm_v8_1a_neon): Update
	comment.  Use check_effective_target_arm_v8_1a_neon_ok to select
	the command line options.
	(check_effective_target_arm_v8_1a_neon_ok_nocache): Update initial
	test to allow ARM targets.  Select and record a working set of
	command line options.
	(check_effective_target_arm_v8_1a_neon_hw): Add tests for ARM
	targets.

gcc/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* doc/sourcebuild.texi (ARM-specific attributes): Add
	"arm_v8_1a_neon_ok" and "arm_v8_1a_neon_hw".


[-- Attachment #2: 0005-Testsuite-Support-ARMv8.1-NEON-on-ARM.patch --]
[-- Type: text/x-patch, Size: 4767 bytes --]

From d6a4dfd89cfb29aeaa0e2d58ac9d8271b31879c1 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Fri, 9 Oct 2015 17:38:12 +0100
Subject: [PATCH 5/7] [Testsuite] Support ARMv8.1 NEON on ARM.

---
 gcc/doc/sourcebuild.texi              |  9 ++++++
 gcc/testsuite/lib/target-supports.exp | 60 ++++++++++++++++++++++++++---------
 2 files changed, 54 insertions(+), 15 deletions(-)

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 61de4a5..cd49e6d8 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1582,6 +1582,15 @@ Some multilibs may be incompatible with these options.
 ARM target supports @code{-mfpu=neon-fp-armv8 -mfloat-abi=softfp}.
 Some multilibs may be incompatible with these options.
 
+@item arm_v8_1a_neon_ok
+ARM target supports options to generate ARMv8.1 Adv.SIMD instructions.
+Some multilibs may be incompatible with these options.
+
+@item arm_v8_1a_neon_hw
+ARM target supports executing ARMv8.1 Adv.SIMD instructions.  Some
+multilibs may be incompatible with the options needed.  Implies
+arm_v8_1a_neon_ok.
+
 @item arm_prefer_ldrd_strd
 ARM target prefers @code{LDRD} and @code{STRD} instructions over
 @code{LDM} and @code{STM} instructions.
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 8d28b23..a0de314 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2825,14 +2825,15 @@ proc add_options_for_arm_v8_neon { flags } {
     return "$flags $et_arm_v8_neon_flags -march=armv8-a"
 }
 
-# Add the options needed for ARMv8.1 Adv.SIMD.
+# Add the options needed for ARMv8.1 Adv.SIMD.  Also adds the ARMv8 NEON
+# options for AArch64 and for ARM.
 
 proc add_options_for_arm_v8_1a_neon { flags } {
-    if { [istarget aarch64*-*-*] } {
-	return "$flags -march=armv8.1-a"
-    } else {
+    if { ! [check_effective_target_arm_v8_1a_neon_ok] } {
 	return "$flags"
     }
+    global et_arm_v8_1a_neon_flags
+    return "$flags $et_arm_v8_1a_neon_flags -march=armv8.1-a"
 }
 
 proc add_options_for_arm_crc { flags } {
@@ -3280,17 +3281,33 @@ proc check_effective_target_arm_neonv2_hw { } {
 }
 
 # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0
-# otherwise.  The test is valid for AArch64.
+# otherwise.  The test is valid for AArch64 and ARM.  Record the command
+# line options needed.
 
 proc check_effective_target_arm_v8_1a_neon_ok_nocache { } {
-    if { ![istarget aarch64*-*-*] } {
-	return 0
+    global et_arm_v8_1a_neon_flags
+    set et_arm_v8_1a_neon_flags ""
+
+    if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
+	return 0;
     }
-    return [check_no_compiler_messages_nocache arm_v8_1a_neon_ok assembly {
-	#if !defined (__ARM_FEATURE_QRDMX)
-	#error "__ARM_FEATURE_QRDMX not defined"
-	#endif
-    } [add_options_for_arm_v8_1a_neon ""]]
+
+    # Iterate through sets of options to find the compiler flags that
+    # need to be added to the -march option.  Start with the empty set
+    # since AArch64 only needs the -march setting.
+    foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
+		       "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
+	if { [check_no_compiler_messages_nocache arm_v8_1a_neon_ok object {
+	    #if !defined (__ARM_FEATURE_QRDMX)
+	    #error "__ARM_FEATURE_QRDMX not defined"
+	    #endif
+	} "$flags -march=armv8.1-a"] } {
+	    set et_arm_v8_1a_neon_flags "$flags -march=armv8.1-a"
+	    return 1
+	}
+    }
+
+    return 0;
 }
 
 proc check_effective_target_arm_v8_1a_neon_ok { } {
@@ -3317,16 +3334,17 @@ proc check_effective_target_arm_v8_neon_hw { } {
 }
 
 # Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0
-# otherwise.  The test is valid for AArch64.
+# otherwise.  The test is valid for AArch64 and ARM.
 
 proc check_effective_target_arm_v8_1a_neon_hw { } {
     if { ![check_effective_target_arm_v8_1a_neon_ok] } {
 	return 0;
     }
-    return [check_runtime_nocache arm_v8_1a_neon_hw_available {
+    return [check_runtime arm_v8_1a_neon_hw_available {
 	int
 	main (void)
 	{
+	  #ifdef __ARM_ARCH_ISA_A64
 	  __Int32x2_t a = {0, 1};
 	  __Int32x2_t b = {0, 2};
 	  __Int32x2_t result;
@@ -3336,9 +3354,21 @@ proc check_effective_target_arm_v8_1a_neon_hw { } {
 	       : "w"(a), "w"(b)
 	       : /* No clobbers.  */);
 
+	  #else
+
+	  __simd64_int32_t a = {0, 1};
+	  __simd64_int32_t b = {0, 2};
+	  __simd64_int32_t result;
+
+	  asm ("vqrdmlah.s32 %P0, %P1, %P2"
+	       : "=w"(result)
+	       : "w"(a), "w"(b)
+	       : /* No clobbers.  */);
+	  #endif
+
 	  return result[0];
 	}
-    }  [add_options_for_arm_v8_1a_neon ""]]
+    } [add_options_for_arm_v8_1a_neon ""]]
 }
 
 # Return 1 if this is a ARM target with NEON enabled.
-- 
2.1.4

Re: [PATCH 5/7][Testsuite] Support ARMv8.1 ARM tests.

[Ramana Radhakrishnan]

On Tue, Dec 15, 2015 at 4:07 PM, Matthew Wahab
<matthew.wahab@foss.arm.com> wrote:
> On 10/12/15 10:49, Ramana Radhakrishnan wrote:
>>
>> On Mon, Dec 7, 2015 at 4:10 PM, Matthew Wahab <matthew.wahab@foss.arm.com>
>> wrote:
>>>
>>> On 27/11/15 17:11, Matthew Wahab wrote:
>>>>
>>>> On 27/11/15 13:44, Christophe Lyon wrote:
>>>>>>
>>>>>> On 26/11/15 16:02, Matthew Wahab wrote
>>>>
>>>>
>>>>>>> This patch adds ARMv8.1 support to GCC Dejagnu, to allow ARM tests to
>>>>>>> specify targest and to set up command line options. It builds on the
>>>>>>> ARMv8.1 target support added for AArch64 tests, partly reworking that
>>>>>>> support to take into account the different configurations that tests
>>>>>>> may
>>>>>>> be run under.
>
> [..]
>>>
>>> # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0 -#
>>> otherwise.  The test is valid for AArch64. +# otherwise.  The test is
>>> valid for
>>> AArch64 and ARM.  Record the command +# line options that needed.
>>
>>
>> s/that//
>
>
> Fixed in attached patch.
>
>> Can you also make sure doc/sourcebuild.texi is updated for this helper
>> function ?
>> If not documented,it would be good to add the documentation for the same
>> while you
>> are here.
>
>
> Done, I've listed them as ARM attributes based on their names.
>
> Tested this and the other update patch (#4/7) for arm-none-eabi with
> cross-compiled
> check-gcc by running the gcc.target/aarch64/advsimd-intrinsics with and
> without ARMv8.1 enabled as a test target.
>
> Ok?

Ok - thanks for dealing with this.


Ramana


> Matthew
>
> testsuite/
> 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
>
>         * lib/target-supports.exp (add_options_for_arm_v8_1a_neon): Update
>         comment.  Use check_effective_target_arm_v8_1a_neon_ok to select
>         the command line options.
>         (check_effective_target_arm_v8_1a_neon_ok_nocache): Update initial
>         test to allow ARM targets.  Select and record a working set of
>         command line options.
>         (check_effective_target_arm_v8_1a_neon_hw): Add tests for ARM
>         targets.
>
> gcc/
> 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
>
>         * doc/sourcebuild.texi (ARM-specific attributes): Add
>         "arm_v8_1a_neon_ok" and "arm_v8_1a_neon_hw".
>

Re: [PATCH 4/7][ARM] Add ACLE feature macro for ARMv8.1 instructions.

[Ramana Radhakrishnan]

On Tue, Dec 15, 2015 at 4:03 PM, Matthew Wahab
<matthew.wahab@foss.arm.com> wrote:
> On 10/12/15 10:45, Ramana Radhakrishnan wrote:
>>
>> On Tue, Dec 8, 2015 at 7:45 AM, Christian Bruel <christian.bruel@st.com>
>> wrote:
>>>
>>> Hi Matthew,
>>>>
>>>>
>>>> On 26/11/15 16:01, Matthew Wahab wrote:
>>>>>
>>>>>
>>>>> Hello,
>>>>>
>>>>> This patch adds the feature macro __ARM_FEATURE_QRDMX to indicate the
>>>>> presence of the ARMv8.1 instructions vqrdmlah and vqrdmlsh. It is
>>>>> defined when the instructions are available, as it is when
>>>>> -march=armv8.1-a is enabled with suitable fpu options.
>>>>>
>>>>> gcc/
>>>>> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>>>>>
>>>>>        * config/arm/arm-c.c (arm_cpu_builtins): Define
>>>>> __ARM_FEATURE_QRDMX.
>>>>>
>>>>
>>>
>>> +  if (TARGET_NEON_RDMA)
>>> +    builtin_define ("__ARM_FEATURE_QRDMX");
>>> +
>>>
>>> Since it depends on TARGET_NEON, could you please use
>>>
>>>    def_or_undef_macro (pfile, "__ARM_FEATURE_QRDMX", TARGET_NEON_RDMA);
>>>
>>> instead ?
>>
>>
>> I think that's what it should be -
>>
>> OK with that fixed.
>
>
> Attached an updated patch using the def_or_undef macro. It also removes some
> trailing whitespace in that part of the code.
>
> Still ok?

Yep, OK.


regards
Ramana

> Matthew
>
> gcc/
> 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
>
>         * config/arm/arm-c.c (arm_cpu_builtins): Define
>         __ARM_FEATURE_QRDMX.  Clean up some trailing whitespace.
>
>

Re: [PATCH 1/7][ARM] Add support for ARMv8.1.

[Matthew Wahab]

On 10/12/15 11:02, Ramana Radhakrishnan wrote:
> On Thu, Dec 10, 2015 at 10:43 AM, Ramana Radhakrishnan
> <ramana.gcc@googlemail.com> wrote:
>> On Mon, Dec 7, 2015 at 4:04 PM, Matthew Wahab
>> <matthew.wahab@foss.arm.com> wrote:
>>> Ping. Updated patch attached.
>>> Matthew
>>>
>>>
>>> On 26/11/15 15:55, Matthew Wahab wrote:
>>>>
>>>> Hello,
>>>>
>>>>
>>>> ARMv8.1 includes an extension to ARM which adds two Adv.SIMD
>>>> instructions, vqrdmlah and vqrdmlsh. This patch set adds support for
>>>> ARMv8.1 and for the new instructions, enabling the architecture with
>>>> --march=armv8.1-a. The new instructions are enabled when both ARMv8.1
>>>> and a suitable fpu options are set, for instance with -march=armv8.1-a
>>>> -mfpu=neon-fp-armv8 -mfloat-abi=hard.
>>>>
[..]
>>>> gcc/
>>>> 2015-11-26  Matthew Wahab  <matthew.wahab@arm.com>
>>>>
>>>>       * config/arm/arm-arches.def: Add "armv8.1-a" and "armv8.1-a+crc".
>>>>       * config/arm/arm-protos.h (FL2_ARCH8_1): New.
>>>>       (FL2_FOR_ARCH8_1A): New.
>>>>       * config/arm/arm-tables.opt: Regenerate.
>>>>       * config/arm/arm.c (arm_arch8_1): New.
>>>>       (arm_option_override): Set arm_arch8_1.
>>>>       * config/arm/arm.h (TARGET_NEON_RDMA): New.
>>>>       (arm_arch8_1): Declare.
>>>>       * doc/invoke.texi (ARM Options, -march): Add "armv8.1-a" and
>>>>       "armv8.1-a+crc".
>>>>       (ARM Options, -mfpu): Fix a typo.
>>>
>>>
>>
>> OK.
>
> I couldn't find 0/7 but in addition here you need to update the output
> for TAG_FP_SIMD_Arch to be 4.
>
> regards
> Ramana

After discussing this offline, it turns out that the relevant attribute 
(Tag_Advanced_SIMD_arch) is set by the assembler.

Matthew

Re: [PATCH 1/7][ARM] Add support for ARMv8.1.

[Ramana Radhakrishnan]

>>
>> I couldn't find 0/7 but in addition here you need to update the output
>> for TAG_FP_SIMD_Arch to be 4.
>>
>> regards
>> Ramana
> 
> After discussing this offline, it turns out that the relevant attribute (Tag_Advanced_SIMD_arch) is set by the assembler.

Yep - sorry about the noise.

The patch set is OK with the changes suggested.

Ramana

> 
> Matthew
> 
> 
> 
>