* [Patch,microblaze]: Instruction prefetch optimization for microblaze.
@ 2015-12-01 8:49 Ajit Kumar Agarwal
2015-12-03 13:57 ` Michael Eager
0 siblings, 1 reply; 5+ messages in thread
From: Ajit Kumar Agarwal @ 2015-12-01 8:49 UTC (permalink / raw)
To: GCC Patches
Cc: Vinod Kathail, Shail Aditya Gupta, Vidhumouli Hunsigida, Nagaraju Mekala
[-- Attachment #1: Type: text/plain, Size: 1160 bytes --]
The changes are made in this patch for the instruction prefetch optimizations for Microblaze.
Reg tested for Microblaze target.
The changes are made for instruction prefetch optimizations for Microblaze. The "wic" microblaze instruction is the
instruction prefetch instruction. The instruction prefetch optimization is done to generate the iprefetch instruction
at the call site fall through path. This optimization is enabled with microblaze target flag mxl-prefetch. The purpose
of adding the flags is that selection of "wic" instruction should be enabled in the reconfigurable design and the
selection is not enabled by default.
ChangeLog:
2015-12-01 Ajit Agarwal <ajitkum@xilinx.com>
* config/microblaze/microblaze.c
(get_branch_target): New.
(insert_wic_for_ilb_runout): New.
(insert_wic): New.
(microblaze_machine_dependent_reorg): New.
(TARGET_MACHINE_DEPENDENT_REORG): Define macro.
* config/microblaze/microblaze.md
(UNSPEC_IPREFETCH): Define.
(iprefetch): New pattern
* config/microblaze/microblaze.opt
(mxl-prefetch): New flag.
Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
Thanks & Regards
Ajit
[-- Attachment #2: iprefetch.patch --]
[-- Type: application/octet-stream, Size: 7498 bytes --]
From 07eaacd1f5a1e4d860e9207894ef86bce815b044 Mon Sep 17 00:00:00 2001
From: Ajit Kumar Agarwal <ajitkum@xilix.com>
Date: Tue, 1 Dec 2015 14:09:52 +0530
Subject: [PATCH] [Patch,microblaze]: Instruction prefetch optimization for microblaze.
The changes are made for instruction prefetch optimizations for Microblaze. The "wic"
microblaze instruction is the instruction prefetch instruction. The instruction prefetch
optimization is done to generate the iprefetch instruction at the call site fall through
path. This optimization is enabled with microblaze target flag mxl-prefetch. The purpose
of adding the flags is that selection of "wic" instruction should be enabled in the
reconfigurable design and the selection is not enabled by default.
ChangeLog:
2015-12-01 Ajit Agarwal <ajitkum@xilinx.com>
* config/microblaze/microblaze.c
(get_branch_target): New.
(insert_wic_for_ilb_runout): New.
(insert_wic): New.
(microblaze_machine_dependent_reorg): New.
(TARGET_MACHINE_DEPENDENT_REORG): Define macro.
* config/microblaze/microblaze.md
(UNSPEC_IPREFETCH): Define.
(iprefetch): New pattern
* config/microblaze/microblaze.opt
(mxl-prefetch): New flag.
Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
---
gcc/config/microblaze/microblaze.c | 139 ++++++++++++++++++++++++++++++++++
gcc/config/microblaze/microblaze.md | 14 ++++
gcc/config/microblaze/microblaze.opt | 4 +
3 files changed, 157 insertions(+), 0 deletions(-)
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index aebbc3b..7d3f3ba 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -43,6 +43,9 @@
#include "output.h"
#include "builtins.h"
#include "rtl-iter.h"
+#include "cfgloop.h"
+#include "insn-addr.h"
+#include "cfgrtl.h"
/* This file should be included last. */
#include "target-def.h"
@@ -3607,6 +3610,139 @@ microblaze_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
return true;
}
+static rtx
+get_branch_target (rtx branch)
+{
+ if (CALL_P (branch))
+ {
+ rtx call;
+
+ call = XVECEXP (PATTERN (branch), 0, 0);
+ if (GET_CODE (call) == SET)
+ call = SET_SRC (call);
+ if (GET_CODE (call) != CALL)
+ abort ();
+ return XEXP (XEXP (call, 0), 0);
+ }
+}
+
+/* Heuristics to identify where to insert at the
+ fall through path of the caller function. If there
+ is a call after the caller branch delay slot then
+ we dont generate the instruction prefetch instruction. */
+
+static void
+insert_wic_for_ilb_runout (rtx_insn *first)
+{
+ rtx_insn *insn, *before_4 = 0, *before_16 = 0;
+ int addr = 0, length, first_addr = -1;
+ int wic_addr0 = 128 * 4, wic_addr1 = 128 * 4;
+ int insert_lnop_after = 0;
+
+ for (insn = first; insn; insn = NEXT_INSN (insn))
+ if (INSN_P (insn))
+ {
+ if (first_addr == -1)
+ first_addr = INSN_ADDRESSES (INSN_UID (insn));
+
+ addr = INSN_ADDRESSES (INSN_UID (insn)) - first_addr;
+ length = get_attr_length (insn);
+ if (before_4 == 0 && addr + length >= 4 * 4)
+ before_4 = insn;
+
+ if (JUMP_P(insn))
+ return;
+ if (before_16 == 0 && addr + length >= 14 * 4)
+ before_16 = insn;
+ if (CALL_P (insn) || tablejump_p (insn, 0, 0))
+ return;
+ if (addr + length >= 32 * 4)
+ {
+ gcc_assert (before_4 && before_16);
+ if (wic_addr0 > 4 * 4)
+ {
+ insn =
+ emit_insn_before (gen_iprefetch
+ (gen_int_mode (addr, SImode)),
+ before_4);
+ recog_memoized (insn);
+ INSN_LOCATION (insn) = INSN_LOCATION (before_4);
+ INSN_ADDRESSES_NEW (insn, INSN_ADDRESSES (INSN_UID (before_4)));
+ return;
+ }
+ }
+ }
+}
+
+/* Insert instruction prefetch instruction at the fall
+ through path of the function call. */
+
+static void
+insert_wic (void)
+{
+ rtx_insn *insn;
+ int i, j;
+ basic_block bb, prev = 0;
+ rtx branch_target = 0;
+
+ shorten_branches (get_insns ());
+
+ for (i = 0; i < n_basic_blocks_for_fn (cfun) - 1; i++)
+ {
+ edge e;
+ edge_iterator ei;
+ bool simple_loop = false;
+
+ bb = BASIC_BLOCK_FOR_FN (cfun, i);
+
+ if (bb == NULL)
+ continue;
+
+ if ((prev != 0) && (prev != bb))
+ continue;
+ else
+ prev = 0;
+
+ FOR_EACH_EDGE (e, ei, bb->preds)
+ if (e->src == bb)
+ {
+ simple_loop = true;
+ prev= e->dest;
+ break;
+ }
+
+ for (insn = BB_END (bb); insn; insn = PREV_INSN (insn))
+ {
+ if (INSN_P (insn) && !simple_loop
+ && CALL_P(insn))
+ {
+ if ((branch_target = get_branch_target (insn)))
+ insert_wic_for_ilb_runout (
+ next_active_insn (next_active_insn (insn)));
+ }
+ if (insn == BB_HEAD (bb))
+ break;
+ }
+ }
+}
+
+/* The reorg function defined through the macro
+ TARGET_MACHINE_DEPENDENT_REORG. */
+
+static void
+microblaze_machine_dependent_reorg (void)
+{
+ if (TARGET_PREFETCH)
+ {
+ compute_bb_for_insn ();
+ loop_optimizer_init (AVOID_CFG_MODIFICATIONS);
+ shorten_branches (get_insns ());
+ insert_wic ();
+ loop_optimizer_finalize();
+ free_bb_for_insn ();
+ return;
+ }
+}
\f
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO microblaze_encode_section_info
@@ -3699,6 +3835,9 @@ microblaze_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
#undef TARGET_LEGITIMATE_CONSTANT_P
#define TARGET_LEGITIMATE_CONSTANT_P microblaze_legitimate_constant_p
+#undef TARGET_MACHINE_DEPENDENT_REORG
+#define TARGET_MACHINE_DEPENDENT_REORG microblaze_machine_dependent_reorg
+
struct gcc_target targetm = TARGET_INITIALIZER;
\f
#include "gt-microblaze.h"
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 596968d..3c7dc29 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -43,6 +43,9 @@
(UNSPEC_TLS 106) ;; jump table
])
+(define_c_enum "unspec" [
+ UNSPEC_IPREFETCH
+])
;;----------------------------------------------------
;; Instruction Attributes
@@ -508,6 +511,17 @@
(set_attr "mode" "SI")
(set_attr "length" "4,8")])
+(define_insn "iprefetch"
+ [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH)
+ (clobber (mem:BLK (scratch)))]
+ "TARGET_PREFETCH"
+ {
+ operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
+ return "mfs\t%2,rpc\n\twic\t%2,r0";
+ }
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "8")])
;;----------------------------------------------------------------
;; Double Precision Subtraction
diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
index 360a8d5..2a00171 100644
--- a/gcc/config/microblaze/microblaze.opt
+++ b/gcc/config/microblaze/microblaze.opt
@@ -123,5 +123,9 @@ mxl-mode-novectors
Target Mask(XL_MODE_NOVECTORS)
Description for mxl-mode-novectors.
+mxl-prefetch
+Target Mask(PREFETCH)
+Use hardware prefetch instruction
+
mxl-mode-xilkernel
Target
--
1.7.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Patch,microblaze]: Instruction prefetch optimization for microblaze.
2015-12-01 8:49 [Patch,microblaze]: Instruction prefetch optimization for microblaze Ajit Kumar Agarwal
@ 2015-12-03 13:57 ` Michael Eager
2015-12-07 17:39 ` Ajit Kumar Agarwal
0 siblings, 1 reply; 5+ messages in thread
From: Michael Eager @ 2015-12-03 13:57 UTC (permalink / raw)
To: Ajit Kumar Agarwal, GCC Patches
Cc: Vinod Kathail, Shail Aditya Gupta, Vidhumouli Hunsigida, Nagaraju Mekala
On 12/01/2015 12:49 AM, Ajit Kumar Agarwal wrote:
> The changes are made in this patch for the instruction prefetch optimizations for Microblaze.
>
> Reg tested for Microblaze target.
>
> The changes are made for instruction prefetch optimizations for Microblaze. The "wic" microblaze instruction is the
> instruction prefetch instruction. The instruction prefetch optimization is done to generate the iprefetch instruction
> at the call site fall through path. This optimization is enabled with microblaze target flag mxl-prefetch. The purpose
> of adding the flags is that selection of "wic" instruction should be enabled in the reconfigurable design and the
> selection is not enabled by default.
>
> ChangeLog:
> 2015-12-01 Ajit Agarwal <ajitkum@xilinx.com>
>
> * config/microblaze/microblaze.c
> (get_branch_target): New.
> (insert_wic_for_ilb_runout): New.
> (insert_wic): New.
> (microblaze_machine_dependent_reorg): New.
> (TARGET_MACHINE_DEPENDENT_REORG): Define macro.
> * config/microblaze/microblaze.md
> (UNSPEC_IPREFETCH): Define.
> (iprefetch): New pattern
> * config/microblaze/microblaze.opt
> (mxl-prefetch): New flag.
>
> Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
>
>
> Thanks & Regards
> Ajit
>
+ rtx_insn *insn, *before_4 = 0, *before_16 = 0;
+ int addr = 0, length, first_addr = -1;
+ int wic_addr0 = 128 * 4, wic_addr1 = 128 * 4;
Especially when there are initializers, I prefer to see each variable declared
on a separate line. If the meaning of a variable is not clear (and most of
these are not), include a comment before the declaration.
+ if (first_addr == -1)
+ first_addr = INSN_ADDRESSES (INSN_UID (insn));
Can be moved to initialize first_addr.
+ addr = INSN_ADDRESSES (INSN_UID (insn)) - first_addr;
Is "addr" and address or offset? If the latter, use a more descriptive name.
+ if (before_4 == 0 && addr + length >= 4 * 4)
+ before_4 = insn;
...
Please add comments to describe what you are doing here. What are before_4
and before_16? What are all these conditions testing?
+ loop_optimizer_finalize();
Space before parens.
--
Michael Eager eager@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [Patch,microblaze]: Instruction prefetch optimization for microblaze.
2015-12-03 13:57 ` Michael Eager
@ 2015-12-07 17:39 ` Ajit Kumar Agarwal
2016-01-21 17:16 ` Michael Eager
0 siblings, 1 reply; 5+ messages in thread
From: Ajit Kumar Agarwal @ 2015-12-07 17:39 UTC (permalink / raw)
To: Michael Eager, GCC Patches
Cc: Vinod Kathail, Shail Aditya Gupta, Vidhumouli Hunsigida, Nagaraju Mekala
[-- Attachment #1: Type: text/plain, Size: 4004 bytes --]
-----Original Message-----
From: Michael Eager [mailto:eager@eagerm.com]
Sent: Thursday, December 03, 2015 7:27 PM
To: Ajit Kumar Agarwal; GCC Patches
Cc: Vinod Kathail; Shail Aditya Gupta; Vidhumouli Hunsigida; Nagaraju Mekala
Subject: Re: [Patch,microblaze]: Instruction prefetch optimization for microblaze.
On 12/01/2015 12:49 AM, Ajit Kumar Agarwal wrote:
> The changes are made in this patch for the instruction prefetch optimizations for Microblaze.
>
> Reg tested for Microblaze target.
>
> The changes are made for instruction prefetch optimizations for
> Microblaze. The "wic" microblaze instruction is the instruction
> prefetch instruction. The instruction prefetch optimization is done to
> generate the iprefetch instruction at the call site fall through path.
> This optimization is enabled with microblaze target flag mxl-prefetch. The purpose of adding the flags is that selection of "wic" instruction should be enabled in the reconfigurable design and the selection is not enabled by default.
>
> ChangeLog:
> 2015-12-01 Ajit Agarwal <ajitkum@xilinx.com>
>
> * config/microblaze/microblaze.c
> (get_branch_target): New.
> (insert_wic_for_ilb_runout): New.
> (insert_wic): New.
> (microblaze_machine_dependent_reorg): New.
> (TARGET_MACHINE_DEPENDENT_REORG): Define macro.
> * config/microblaze/microblaze.md
> (UNSPEC_IPREFETCH): Define.
> (iprefetch): New pattern
> * config/microblaze/microblaze.opt
> (mxl-prefetch): New flag.
>
> Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
>
>
> Thanks & Regards
> Ajit
>
>>+ rtx_insn *insn, *before_4 = 0, *before_16 = 0; int addr = 0, length,
>>+ first_addr = -1; int wic_addr0 = 128 * 4, wic_addr1 = 128 * 4;
>>Especially when there are initializers, I prefer to see each variable declared on a separate line. If the meaning of a variable is not clear (and most of these are not), include a comment >>before the declaration.
>>+ if (first_addr == -1)
>>+ first_addr = INSN_ADDRESSES (INSN_UID (insn));
>>Can be moved to initialize first_addr.
>>+ addr = INSN_ADDRESSES (INSN_UID (insn)) - first_addr;
>>Is "addr" and address or offset? If the latter, use a more descriptive name.
>>+ if (before_4 == 0 && addr + length >= 4 * 4)
>>+ before_4 = insn;
...
>>Please add comments to describe what you are doing here. What are before_4 and before_16? What are all these conditions testing?
>>+ loop_optimizer_finalize();
>>Space before parens.
All the above comments are incorporated. Updated patch is attached.
Regtested for Microblaze target.
Mibench/EEMBC benchmarks are run on the hardware enabling the mxl-prefetch and the run goes through fine
With the generation of "wic" instruction.
[Patch,microblaze]: Instruction prefetch optimization for microblaze.
The changes are made for instruction prefetch optimizations for Microblaze. The "wic"
microblaze instruction is the instruction prefetch instruction. The instruction prefetch
optimization is done to generate the iprefetch instruction at the call site fall through
path. This optimization is enabled with microblaze target flag mxl-prefetch. The purpose
of adding the flags is that selection of "wic" instruction should be enabled in the
reconfigurable design and the selection is not enabled by default.
ChangeLog:
2015-12-07 Ajit Agarwal <ajitkum@xilinx.com>
* config/microblaze/microblaze.c
(get_branch_target): New.
(insert_wic_for_ilb_runout): New.
(insert_wic): New.
(microblaze_machine_dependent_reorg): New.
(TARGET_MACHINE_DEPENDENT_REORG): Define macro.
* config/microblaze/microblaze.md
(UNSPEC_IPREFETCH): Define.
(iprefetch): New pattern
* config/microblaze/microblaze.opt
(mxl-prefetch): New flag.
Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
Thanks & Regards
Ajit
--
Michael Eager eager@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
[-- Attachment #2: iprefetch.patch --]
[-- Type: application/octet-stream, Size: 7989 bytes --]
From 4f546b2f866dd3da1350775ef3b16363f21e38fd Mon Sep 17 00:00:00 2001
From: Ajit Kumar Agarwal <ajitkum@xilix.com>
Date: Mon, 7 Dec 2015 22:52:35 +0530
Subject: [PATCH] [Patch,microblaze]: Instruction prefetch optimization for microblaze.
The changes are made for instruction prefetch optimizations for Microblaze. The "wic"
microblaze instruction is the instruction prefetch instruction. The instruction prefetch
optimization is done to generate the iprefetch instruction at the call site fall through
path. This optimization is enabled with microblaze target flag mxl-prefetch. The purpose
of adding the flags is that selection of "wic" instruction should be enabled in the
reconfigurable design and the selection is not enabled by default.
ChangeLog:
2015-12-07 Ajit Agarwal <ajitkum@xilinx.com>
* config/microblaze/microblaze.c
(get_branch_target): New.
(insert_wic_for_ilb_runout): New.
(insert_wic): New.
(microblaze_machine_dependent_reorg): New.
(TARGET_MACHINE_DEPENDENT_REORG): Define macro.
* config/microblaze/microblaze.md
(UNSPEC_IPREFETCH): Define.
(iprefetch): New pattern
* config/microblaze/microblaze.opt
(mxl-prefetch): New flag.
Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
---
gcc/config/microblaze/microblaze.c | 151 ++++++++++++++++++++++++++++++++++
gcc/config/microblaze/microblaze.md | 14 +++
gcc/config/microblaze/microblaze.opt | 4 +
3 files changed, 169 insertions(+), 0 deletions(-)
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index aebbc3b..5ed4de1 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -43,6 +43,9 @@
#include "output.h"
#include "builtins.h"
#include "rtl-iter.h"
+#include "cfgloop.h"
+#include "insn-addr.h"
+#include "cfgrtl.h"
/* This file should be included last. */
#include "target-def.h"
@@ -3607,6 +3610,151 @@ microblaze_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
return true;
}
+static rtx
+get_branch_target (rtx branch)
+{
+ if (CALL_P (branch))
+ {
+ rtx call;
+
+ call = XVECEXP (PATTERN (branch), 0, 0);
+ if (GET_CODE (call) == SET)
+ call = SET_SRC (call);
+ if (GET_CODE (call) != CALL)
+ abort ();
+ return XEXP (XEXP (call, 0), 0);
+ }
+}
+
+/* Heuristics to identify where to insert at the
+ fall through path of the caller function. If there
+ is a call after the caller branch delay slot then
+ we dont generate the instruction prefetch instruction.
+
+ Scan up to 32 instructions after the call and checks
+ for the JUMP and call instruction . If there is a call
+ or JUMP instruction in the range of 32 instruction "wic"
+ instruction wont be generated. Otherwise insert the "wic"
+ instruction in the fall through of the call instruction
+ four instruction after the call. before_4 is used for
+ the position to insert "wic" instructions. before_16 is
+ used to check for call and JUMP instruction for first
+ 15 insns. */
+
+static void
+insert_wic_for_ilb_runout (rtx_insn *first)
+{
+ rtx_insn *insn;
+ rtx_insn *before_4 = 0;
+ rtx_insn *before_16 = 0;
+ int addr_offset = 0;
+ int length;
+ int wic_addr0 = 128 * 4;
+ int wic_addr1 = 128 * 4;
+
+ int first_addr = INSN_ADDRESSES (INSN_UID (first));
+
+ for (insn = first; insn; insn = NEXT_INSN (insn))
+ if (INSN_P (insn))
+ {
+ addr_offset = INSN_ADDRESSES (INSN_UID (insn)) - first_addr;
+ length = get_attr_length (insn);
+ if (before_4 == 0 && addr_offset + length >= 4 * 4)
+ before_4 = insn;
+
+ if (JUMP_P(insn))
+ return;
+ if (before_16 == 0 && addr_offset + length >= 14 * 4)
+ before_16 = insn;
+ if (CALL_P (insn) || tablejump_p (insn, 0, 0))
+ return;
+ if (addr_offset + length >= 32 * 4)
+ {
+ gcc_assert (before_4 && before_16);
+ if (wic_addr0 > 4 * 4)
+ {
+ insn =
+ emit_insn_before (gen_iprefetch
+ (gen_int_mode (addr_offset, SImode)),
+ before_4);
+ recog_memoized (insn);
+ INSN_LOCATION (insn) = INSN_LOCATION (before_4);
+ INSN_ADDRESSES_NEW (insn, INSN_ADDRESSES (INSN_UID (before_4)));
+ return;
+ }
+ }
+ }
+}
+
+/* Insert instruction prefetch instruction at the fall
+ through path of the function call. */
+
+static void
+insert_wic (void)
+{
+ rtx_insn *insn;
+ int i, j;
+ basic_block bb, prev = 0;
+ rtx branch_target = 0;
+
+ shorten_branches (get_insns ());
+
+ for (i = 0; i < n_basic_blocks_for_fn (cfun) - 1; i++)
+ {
+ edge e;
+ edge_iterator ei;
+ bool simple_loop = false;
+
+ bb = BASIC_BLOCK_FOR_FN (cfun, i);
+
+ if (bb == NULL)
+ continue;
+
+ if ((prev != 0) && (prev != bb))
+ continue;
+ else
+ prev = 0;
+
+ FOR_EACH_EDGE (e, ei, bb->preds)
+ if (e->src == bb)
+ {
+ simple_loop = true;
+ prev= e->dest;
+ break;
+ }
+
+ for (insn = BB_END (bb); insn; insn = PREV_INSN (insn))
+ {
+ if (INSN_P (insn) && !simple_loop
+ && CALL_P(insn))
+ {
+ if ((branch_target = get_branch_target (insn)))
+ insert_wic_for_ilb_runout (
+ next_active_insn (next_active_insn (insn)));
+ }
+ if (insn == BB_HEAD (bb))
+ break;
+ }
+ }
+}
+
+/* The reorg function defined through the macro
+ TARGET_MACHINE_DEPENDENT_REORG. */
+
+static void
+microblaze_machine_dependent_reorg (void)
+{
+ if (TARGET_PREFETCH)
+ {
+ compute_bb_for_insn ();
+ loop_optimizer_init (AVOID_CFG_MODIFICATIONS);
+ shorten_branches (get_insns ());
+ insert_wic ();
+ loop_optimizer_finalize ();
+ free_bb_for_insn ();
+ return;
+ }
+}
\f
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO microblaze_encode_section_info
@@ -3699,6 +3847,9 @@ microblaze_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
#undef TARGET_LEGITIMATE_CONSTANT_P
#define TARGET_LEGITIMATE_CONSTANT_P microblaze_legitimate_constant_p
+#undef TARGET_MACHINE_DEPENDENT_REORG
+#define TARGET_MACHINE_DEPENDENT_REORG microblaze_machine_dependent_reorg
+
struct gcc_target targetm = TARGET_INITIALIZER;
\f
#include "gt-microblaze.h"
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 596968d..3c7dc29 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -43,6 +43,9 @@
(UNSPEC_TLS 106) ;; jump table
])
+(define_c_enum "unspec" [
+ UNSPEC_IPREFETCH
+])
;;----------------------------------------------------
;; Instruction Attributes
@@ -508,6 +511,17 @@
(set_attr "mode" "SI")
(set_attr "length" "4,8")])
+(define_insn "iprefetch"
+ [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH)
+ (clobber (mem:BLK (scratch)))]
+ "TARGET_PREFETCH"
+ {
+ operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
+ return "mfs\t%2,rpc\n\twic\t%2,r0";
+ }
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "8")])
;;----------------------------------------------------------------
;; Double Precision Subtraction
diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
index 360a8d5..2a00171 100644
--- a/gcc/config/microblaze/microblaze.opt
+++ b/gcc/config/microblaze/microblaze.opt
@@ -123,5 +123,9 @@ mxl-mode-novectors
Target Mask(XL_MODE_NOVECTORS)
Description for mxl-mode-novectors.
+mxl-prefetch
+Target Mask(PREFETCH)
+Use hardware prefetch instruction
+
mxl-mode-xilkernel
Target
--
1.7.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Patch,microblaze]: Instruction prefetch optimization for microblaze.
2015-12-07 17:39 ` Ajit Kumar Agarwal
@ 2016-01-21 17:16 ` Michael Eager
0 siblings, 0 replies; 5+ messages in thread
From: Michael Eager @ 2016-01-21 17:16 UTC (permalink / raw)
To: Ajit Kumar Agarwal, GCC Patches
Cc: Vinod Kathail, Shail Aditya Gupta, Vidhumouli Hunsigida, Nagaraju Mekala
On 12/07/2015 09:39 AM, Ajit Kumar Agarwal wrote:
>
>
> -----Original Message-----
> From: Michael Eager [mailto:eager@eagerm.com]
> Sent: Thursday, December 03, 2015 7:27 PM
> To: Ajit Kumar Agarwal; GCC Patches
> Cc: Vinod Kathail; Shail Aditya Gupta; Vidhumouli Hunsigida; Nagaraju Mekala
> Subject: Re: [Patch,microblaze]: Instruction prefetch optimization for microblaze.
>
> On 12/01/2015 12:49 AM, Ajit Kumar Agarwal wrote:
>> The changes are made in this patch for the instruction prefetch optimizations for Microblaze.
>>
>> Reg tested for Microblaze target.
>>
>> The changes are made for instruction prefetch optimizations for
>> Microblaze. The "wic" microblaze instruction is the instruction
>> prefetch instruction. The instruction prefetch optimization is done to
>> generate the iprefetch instruction at the call site fall through path.
>> This optimization is enabled with microblaze target flag mxl-prefetch. The purpose of adding the flags is that selection of "wic" instruction should be enabled in the reconfigurable design and the selection is not enabled by default.
>>
>> ChangeLog:
>> 2015-12-01 Ajit Agarwal <ajitkum@xilinx.com>
>>
>> * config/microblaze/microblaze.c
>> (get_branch_target): New.
>> (insert_wic_for_ilb_runout): New.
>> (insert_wic): New.
>> (microblaze_machine_dependent_reorg): New.
>> (TARGET_MACHINE_DEPENDENT_REORG): Define macro.
>> * config/microblaze/microblaze.md
>> (UNSPEC_IPREFETCH): Define.
>> (iprefetch): New pattern
>> * config/microblaze/microblaze.opt
>> (mxl-prefetch): New flag.
>>
>> Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
>>
>>
>> Thanks & Regards
>> Ajit
>>
>
>>> + rtx_insn *insn, *before_4 = 0, *before_16 = 0; int addr = 0, length,
>>> + first_addr = -1; int wic_addr0 = 128 * 4, wic_addr1 = 128 * 4;
>
>>> Especially when there are initializers, I prefer to see each variable declared on a separate line. If the meaning of a variable is not clear (and most of these are not), include a comment >>before the declaration.
>
>>> + if (first_addr == -1)
>>> + first_addr = INSN_ADDRESSES (INSN_UID (insn));
>
>>> Can be moved to initialize first_addr.
>
>>> + addr = INSN_ADDRESSES (INSN_UID (insn)) - first_addr;
>
>>> Is "addr" and address or offset? If the latter, use a more descriptive name.
>
>
>>> + if (before_4 == 0 && addr + length >= 4 * 4)
>>> + before_4 = insn;
> ...
>
>>> Please add comments to describe what you are doing here. What are before_4 and before_16? What are all these conditions testing?
>
>
>>> + loop_optimizer_finalize();
>
>>> Space before parens.
>
> All the above comments are incorporated. Updated patch is attached.
>
> Regtested for Microblaze target.
>
> Mibench/EEMBC benchmarks are run on the hardware enabling the mxl-prefetch and the run goes through fine
> With the generation of "wic" instruction.
>
> [Patch,microblaze]: Instruction prefetch optimization for microblaze.
>
> The changes are made for instruction prefetch optimizations for Microblaze. The "wic"
> microblaze instruction is the instruction prefetch instruction. The instruction prefetch
> optimization is done to generate the iprefetch instruction at the call site fall through
> path. This optimization is enabled with microblaze target flag mxl-prefetch. The purpose
> of adding the flags is that selection of "wic" instruction should be enabled in the
> reconfigurable design and the selection is not enabled by default.
>
> ChangeLog:
> 2015-12-07 Ajit Agarwal <ajitkum@xilinx.com>
>
> * config/microblaze/microblaze.c
> (get_branch_target): New.
> (insert_wic_for_ilb_runout): New.
> (insert_wic): New.
> (microblaze_machine_dependent_reorg): New.
> (TARGET_MACHINE_DEPENDENT_REORG): Define macro.
> * config/microblaze/microblaze.md
> (UNSPEC_IPREFETCH): Define.
> (iprefetch): New pattern
> * config/microblaze/microblaze.opt
> (mxl-prefetch): New flag.
>
> Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
>
> Thanks & Regards
> Ajit
>
Committed revision 232683.
--
Michael Eager eager@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [Patch,microblaze]: Instruction prefetch optimization for microblaze.
@ 2015-12-01 9:01 Ajit Kumar Agarwal
0 siblings, 0 replies; 5+ messages in thread
From: Ajit Kumar Agarwal @ 2015-12-01 9:01 UTC (permalink / raw)
To: GCC Patches
Cc: Vinod Kathail, Shail Aditya Gupta, Vidhumouli Hunsigida, Nagaraju Mekala
Moreover this patch is tested and run on hardware with Mibench/EEMBC benchmarks for Microblaze target. The reconfigurable
design is enabled with the selection of "wic" instruction prefetch instruction and above benchmarks compiled with -mxl-prefetch flags.
Thanks & Regards
Ajit
-----Original Message-----
From: Ajit Kumar Agarwal
Sent: Tuesday, December 01, 2015 2:19 PM
To: GCC Patches
Cc: Vinod Kathail; Shail Aditya Gupta; Vidhumouli Hunsigida; Nagaraju Mekala
Subject: [Patch,microblaze]: Instruction prefetch optimization for microblaze.
The changes are made in this patch for the instruction prefetch optimizations for Microblaze.
Reg tested for Microblaze target.
The changes are made for instruction prefetch optimizations for Microblaze. The "wic" microblaze instruction is the instruction prefetch instruction. The instruction prefetch optimization is done to generate the iprefetch instruction at the call site fall through path. This optimization is enabled with microblaze target flag mxl-prefetch. The purpose of adding the flags is that selection of "wic" instruction should be enabled in the reconfigurable design and the selection is not enabled by default.
ChangeLog:
2015-12-01 Ajit Agarwal <ajitkum@xilinx.com>
* config/microblaze/microblaze.c
(get_branch_target): New.
(insert_wic_for_ilb_runout): New.
(insert_wic): New.
(microblaze_machine_dependent_reorg): New.
(TARGET_MACHINE_DEPENDENT_REORG): Define macro.
* config/microblaze/microblaze.md
(UNSPEC_IPREFETCH): Define.
(iprefetch): New pattern
* config/microblaze/microblaze.opt
(mxl-prefetch): New flag.
Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
Thanks & Regards
Ajit
^ permalink raw reply [flat|nested] 5+ messages in thread
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2015-12-01 8:49 [Patch,microblaze]: Instruction prefetch optimization for microblaze Ajit Kumar Agarwal
2015-12-03 13:57 ` Michael Eager
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2016-01-21 17:16 ` Michael Eager
2015-12-01 9:01 Ajit Kumar Agarwal
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