From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 130252 invoked by alias); 16 Dec 2015 21:30:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 130236 invoked by uid 89); 16 Dec 2015 21:30:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.1 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=recommendation, H*r:May, Hx-spam-relays-external:ESMTPA, HContent-transfer-encoding:7bit X-HELO: usmailout2.samsung.com Received: from mailout2.w2.samsung.com (HELO usmailout2.samsung.com) (211.189.100.12) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 16 Dec 2015 21:30:42 +0000 Received: from uscpsbgm1.samsung.com (u114.gpu85.samsung.co.kr [203.254.195.114]) by mailout2.w2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZG002NGZR45B10@mailout2.w2.samsung.com> for gcc-patches@gcc.gnu.org; Wed, 16 Dec 2015 16:30:40 -0500 (EST) Received: from ussync3.samsung.com ( [203.254.195.83]) by uscpsbgm1.samsung.com (USCPMTA) with SMTP id 6D.B3.23844.008D1765; Wed, 16 Dec 2015 16:30:40 -0500 (EST) Received: from [172.31.207.194] ([105.140.31.10]) by ussync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZG005TJZR3CP50@ussync3.samsung.com>; Wed, 16 Dec 2015 16:30:40 -0500 (EST) Subject: Re: [PATCH][AArch64] Replace insn to zero up DF register To: Marcus Shawcroft References: <56257F53.2000905@samsung.com> Cc: "gcc-patches@gcc.gnu.org" , Marcus Shawcroft , Kyrill Tkachov From: Evandro Menezes Message-id: <5671D7FF.3070900@samsung.com> Date: Wed, 16 Dec 2015 21:30:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-version: 1.0 In-reply-to: Content-type: text/plain; charset=utf-8; format=flowed Content-transfer-encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2015-12/txt/msg01664.txt.bz2 On 10/30/2015 05:24 AM, Marcus Shawcroft wrote: > On 20 October 2015 at 00:40, Evandro Menezes wrote: >> In the existing targets, it seems that it's always faster to zero up a DF >> register with "movi %d0, #0" instead of "fmov %d0, xzr". >> >> This patch modifies the respective pattern. > > Hi Evandro, > > This patch changes the generic, u architecture independent instruction > selection. The ARM ARM (C3.5.3) makes a specific recommendation about > the choice of instruction in this situation and the current > implementation in GCC follows that recommendation. Wilco has also > picked up on this issue he has the same patch internal to ARM along > with an ongoing discussion with ARM architecture folk regarding this > recommendation. I'm reluctant to take this patch right now on the > basis that it runs contrary to ARM ARM recommendation pending the > conclusion of Wilco's discussion with ARM architecture folk. > Marcus, Have you had a chance to discuss this internally further? Thank you, -- Evandro Menezes