Hi all,

Following up from https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01723.html
here is the patch that makes combine canonicalise x + x expressions into x << 1.
This allows for more simplification opportunities, as well as increases the recognition
opportunities on targets that support combined arithmetic and shift instructions,
like aarch64 and arm.

This has the same effect on aarch64 as my first attempt, i.e. it increases the combination
opportunities for -mcpu=cortex-a53 with the added effect that simple register adds of the form:
"add x1, x0, x0" are now transformed into shifts "lsl x1, x0, #1".

It has been suggested in that thread that if the target wants to distinguish between a shift-by-one
and the plus form then it should match the shift form and explicitly output the instruction pattern for
the plus form.

This would be, of course, a separate aarch64-specific patch.

Bootstrapped and tested on arm, aarch64, x86_64.
As before, there were no codegen differences for SPEC2006 on x86_64.
aarch64 SPEC2006 sees the effects described above.

How does this approach look?

2015-12-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     PR rtl-optimization/68651
     * combine.c (combine_simplify_rtx): Canonicalize x + x into
     x << 1.

2015-12-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     PR rtl-optimization/68651
     * gcc.target/aarch64/pr68651_1.c: New test.