From: Edwin Lu <ewlu@rivosinc.com>
To: Jeff Law <jeffreyalaw@gmail.com>, gcc-patches@gcc.gnu.org
Cc: gnu-toolchain@rivosinc.com, Robin Dapp <rdapp@ventanamicro.com>
Subject: Re: [Committed V3 2/2] RISC-V: Move mode assertion out of conditional branch in emit_insn
Date: Tue, 18 Jun 2024 16:34:18 -0600 [thread overview]
Message-ID: <56849545-6067-404b-afd4-15a864aeb937@rivosinc.com> (raw)
In-Reply-To: <eb0616ae-5d6b-4606-9711-a8bd1e370aaf@gmail.com>
Thanks!
Edwin
On 6/17/2024 5:33 PM, Jeff Law wrote:
>
>
> On 6/17/24 12:33 PM, Edwin Lu wrote:
>> When emitting insns, we have an early assertion to ensure the input
>> operand's mode and the expanded operand's mode are the same; however, it
>> does not perform this check if the pattern does not have an explicit
>> machine mode specifying the operand. In this scenario, it will always
>> assume that mode = Pmode to correctly satisfy the
>> maybe_legitimize_operand check, however, there may be problems when
>> working in 32 bit environments.
>>
>> Make the assert unconditional and replace it with an internal error for
>> more descriptive logging
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv-v.cc: Move assert out of conditional block
> OK.
>
> Jeff
>
prev parent reply other threads:[~2024-06-18 22:34 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-17 18:33 [PATCH V3 0/2] Fix ICE with vwsll combine on 32bit targets Edwin Lu
2024-06-17 18:33 ` [PATCH V3 1/2] RISC-V: Fix vwsll combine on rv32 targets Edwin Lu
2024-06-17 23:31 ` Jeff Law
2024-06-18 22:34 ` [Committed " Edwin Lu
2024-06-17 18:33 ` [PATCH V3 2/2] RISC-V: Move mode assertion out of conditional branch in emit_insn Edwin Lu
2024-06-17 23:33 ` Jeff Law
2024-06-18 22:34 ` Edwin Lu [this message]
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