From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 129925 invoked by alias); 13 Jan 2016 00:06:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 129916 invoked by uid 89); 13 Jan 2016 00:06:34 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=HContent-type:flowed, HContent-type:format, recommendation, HContent-transfer-encoding:7bit X-HELO: usmailout4.samsung.com Received: from mailout4.w2.samsung.com (HELO usmailout4.samsung.com) (211.189.100.14) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 13 Jan 2016 00:06:32 +0000 Received: from uscpsbgm1.samsung.com (u114.gpu85.samsung.co.kr [203.254.195.114]) by usmailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O0V00ATE6YU6UB0@usmailout4.samsung.com> for gcc-patches@gcc.gnu.org; Tue, 12 Jan 2016 19:06:30 -0500 (EST) Received: from ussync2.samsung.com ( [203.254.195.82]) by uscpsbgm1.samsung.com (USCPMTA) with SMTP id B3.2D.23844.60595965; Tue, 12 Jan 2016 19:06:30 -0500 (EST) Received: from [172.31.207.192] ([105.140.31.209]) by ussync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O0V008YC6YSGV90@ussync2.samsung.com>; Tue, 12 Jan 2016 19:06:30 -0500 (EST) Subject: Re: [PATCH][AArch64] Replace insn to zero up DF register To: Marcus Shawcroft References: <56257F53.2000905@samsung.com> <5671D7FF.3070900@samsung.com> Cc: "gcc-patches@gcc.gnu.org" , Marcus Shawcroft , Kyrill Tkachov , James Greenhalgh From: Evandro Menezes Message-id: <56959504.8040609@samsung.com> Date: Wed, 13 Jan 2016 00:06:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-version: 1.0 In-reply-to: <5671D7FF.3070900@samsung.com> Content-type: text/plain; charset=utf-8; format=flowed Content-transfer-encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2016-01/txt/msg00780.txt.bz2 On 12/16/2015 03:30 PM, Evandro Menezes wrote: > On 10/30/2015 05:24 AM, Marcus Shawcroft wrote: >> On 20 October 2015 at 00:40, Evandro Menezes >> wrote: >>> In the existing targets, it seems that it's always faster to zero up >>> a DF >>> register with "movi %d0, #0" instead of "fmov %d0, xzr". >>> >>> This patch modifies the respective pattern. >> >> Hi Evandro, >> >> This patch changes the generic, u architecture independent instruction >> selection. The ARM ARM (C3.5.3) makes a specific recommendation about >> the choice of instruction in this situation and the current >> implementation in GCC follows that recommendation. Wilco has also >> picked up on this issue he has the same patch internal to ARM along >> with an ongoing discussion with ARM architecture folk regarding this >> recommendation. I'm reluctant to take this patch right now on the >> basis that it runs contrary to ARM ARM recommendation pending the >> conclusion of Wilco's discussion with ARM architecture folk. > > Have you had a chance to discuss this internally further? > Ping. -- Evandro Menezes