From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 60680 invoked by alias); 22 Jan 2016 09:32:12 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 60663 invoked by uid 89); 22 Jan 2016 09:32:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 22 Jan 2016 09:32:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B6263A8; Fri, 22 Jan 2016 01:31:29 -0800 (PST) Received: from [10.2.206.200] (e100706-lin.cambridge.arm.com [10.2.206.200]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 10F963F246; Fri, 22 Jan 2016 01:32:07 -0800 (PST) Message-ID: <56A1F716.9000405@foss.arm.com> Date: Fri, 22 Jan 2016 09:32:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Han Shen CC: GCC Patches , Ramana Radhakrishnan , Richard Earnshaw Subject: Re: [PATCH][ARM] Fix PR target/69403: Bug in thumb2_ior_scc_strict_it pattern References: <56A11A98.1020503@foss.arm.com> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2016-01/txt/msg01711.txt.bz2 Hi Han, On 21/01/16 22:57, Han Shen wrote: > Hi Kyrill, the patched gcc generates correct asm for me for the test > case. (I'll then build the whole system to see if other it-block > related bugs are gone too.) > > One short question, the newly generated RTL for > x = x | (a) > will be > orr %0, %1, #1; it ; mov%D2\\t%0, %1 (b) > > The cond in (a) should be the reverse of cond in(b), right? yes, the first C-like expression is just some pseudocode. I guess it would be better written as: x = x | . Thanks for trying it out. I bootstrapped and tested this patch on trunk and GCC 5. I'll be doing the same on the 4.9 branch. Kyrill > Thanks for your quick fix. > > Han > > On Thu, Jan 21, 2016 at 9:51 AM, Kyrill Tkachov > wrote: >> Hi all, >> >> In this wrong-code PR the pattern for performing >> x = x | for -mrestrict-it is buggy and ends up writing 1 to the >> result register rather than orring it. >> >> The offending pattern is *thumb2_ior_scc_strict_it. >> My proposed solution is to rewrite it as a splitter, remove the >> alternative for the case where operands[1] and 0 are the same reg >> that emits the bogus: >> it ; mov%0, #1; it ; orr %0, %1 >> >> to emit the RTL equivalent to: >> orr %0, %1, #1; it ; mov%D2\\t%0, %1 >> while marking operand 0 as an earlyclobber operand so that it doesn't >> get assigned the same register as operand 1. >> >> This way we avoid the wrong-code, make the sequence better (by eliminating >> the move of #1 into a register >> and relaxing the constraints from 'l' to 'r' since only the register move >> has to be conditional). >> and still stay within the rules for arm_restrict_it. >> >> Bootstrapped and tested on arm-none-linux-gnueabihf configured >> --with-arch=armv8-a and --with-mode=thumb. >> >> Ok for trunk, GCC 5 and 4.9? >> >> Han, can you please try this out to see if it solves the problem on your end >> as well? >> >> Thanks, >> Kyrill >> >> 2016-01-21 Kyrylo Tkachov >> >> PR target/69403 >> * config/arm/thumb2.md (*thumb2_ior_scc_strict_it): Convert to >> define_insn_and_split. Ensure operands[1] and operands[0] do not >> get assigned the same register. >> >> 2016-01-21 Kyrylo Tkachov >> >> PR target/69403 >> * gcc.c-torture/execute/pr69403.c: New test. > >