From: Evandro Menezes <e.menezes@samsung.com>
To: James Greenhalgh <james.greenhalgh@arm.com>, gcc-patches@gcc.gnu.org
Cc: nd@arm.com, richard.earnshaw@arm.com, marcus.shawcroft@arm.com
Subject: Re: [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS
Date: Wed, 27 Jan 2016 21:49:00 -0000 [thread overview]
Message-ID: <56A93B60.60202@samsung.com> (raw)
In-Reply-To: <1453824287-37678-1-git-send-email-james.greenhalgh@arm.com>
On 01/26/16 10:04, James Greenhalgh wrote:
> Hi,
>
> In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction
> available when compiling with -march=armv8.1-a are only usable with
> a register number in the range 0 to 15 for operand 3, as gas will point
> out:
>
> Error: register number out of range 0 to 15 at
> operand 3 -- `sqrdmlsh v2.4h,v4.4h,v23.h[5]'
>
> This patch teaches GCC to avoid registers outside of this range when
> appropriate, in the same fashion as we do for other instructions with
> this limitation.
>
> Tested on an internal testsuite targeting Neon intrinsics.
>
> OK?
>
> Thanks,
> James
>
> ---
> 2016-01-25 James Greenhalgh <james.greenhalgh@arm.com>
>
> * config/aarch64/aarch64.md
> (arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
> constraints for operand 3.
> (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
>
LGTM
--
Evandro Menezes
next prev parent reply other threads:[~2016-01-27 21:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-26 16:05 James Greenhalgh
2016-01-27 21:49 ` Evandro Menezes [this message]
2016-02-08 12:52 ` James Greenhalgh
2016-02-15 10:49 ` James Greenhalgh
2016-02-16 8:47 ` Marcus Shawcroft
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