* [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS
@ 2016-01-26 16:05 James Greenhalgh
2016-01-27 21:49 ` Evandro Menezes
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: James Greenhalgh @ 2016-01-26 16:05 UTC (permalink / raw)
To: gcc-patches; +Cc: nd, richard.earnshaw, marcus.shawcroft
[-- Attachment #1: Type: text/plain, Size: 836 bytes --]
Hi,
In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction
available when compiling with -march=armv8.1-a are only usable with
a register number in the range 0 to 15 for operand 3, as gas will point
out:
Error: register number out of range 0 to 15 at
operand 3 -- `sqrdmlsh v2.4h,v4.4h,v23.h[5]'
This patch teaches GCC to avoid registers outside of this range when
appropriate, in the same fashion as we do for other instructions with
this limitation.
Tested on an internal testsuite targeting Neon intrinsics.
OK?
Thanks,
James
---
2016-01-25 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md
(arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
constraints for operand 3.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0001-Patch-AArch64-Restrict-16-bit-sqrdml-sa-h-instructio.patch --]
[-- Type: text/x-patch; name=0001-Patch-AArch64-Restrict-16-bit-sqrdml-sa-h-instructio.patch, Size: 1733 bytes --]
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index e1f5682..0b46e78 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3240,7 +3240,7 @@
[(match_operand:VDQHS 1 "register_operand" "0")
(match_operand:VDQHS 2 "register_operand" "w")
(vec_select:<VEL>
- (match_operand:<VCOND> 3 "register_operand" "w")
+ (match_operand:<VCOND> 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
@@ -3258,7 +3258,7 @@
[(match_operand:SD_HSI 1 "register_operand" "0")
(match_operand:SD_HSI 2 "register_operand" "w")
(vec_select:<VEL>
- (match_operand:<VCOND> 3 "register_operand" "w")
+ (match_operand:<VCOND> 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
@@ -3278,7 +3278,7 @@
[(match_operand:VDQHS 1 "register_operand" "0")
(match_operand:VDQHS 2 "register_operand" "w")
(vec_select:<VEL>
- (match_operand:<VCONQ> 3 "register_operand" "w")
+ (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
@@ -3296,7 +3296,7 @@
[(match_operand:SD_HSI 1 "register_operand" "0")
(match_operand:SD_HSI 2 "register_operand" "w")
(vec_select:<VEL>
- (match_operand:<VCONQ> 3 "register_operand" "w")
+ (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS
2016-01-26 16:05 [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS James Greenhalgh
@ 2016-01-27 21:49 ` Evandro Menezes
2016-02-08 12:52 ` James Greenhalgh
2016-02-16 8:47 ` Marcus Shawcroft
2 siblings, 0 replies; 5+ messages in thread
From: Evandro Menezes @ 2016-01-27 21:49 UTC (permalink / raw)
To: James Greenhalgh, gcc-patches; +Cc: nd, richard.earnshaw, marcus.shawcroft
On 01/26/16 10:04, James Greenhalgh wrote:
> Hi,
>
> In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction
> available when compiling with -march=armv8.1-a are only usable with
> a register number in the range 0 to 15 for operand 3, as gas will point
> out:
>
> Error: register number out of range 0 to 15 at
> operand 3 -- `sqrdmlsh v2.4h,v4.4h,v23.h[5]'
>
> This patch teaches GCC to avoid registers outside of this range when
> appropriate, in the same fashion as we do for other instructions with
> this limitation.
>
> Tested on an internal testsuite targeting Neon intrinsics.
>
> OK?
>
> Thanks,
> James
>
> ---
> 2016-01-25 James Greenhalgh <james.greenhalgh@arm.com>
>
> * config/aarch64/aarch64.md
> (arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
> constraints for operand 3.
> (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
>
LGTM
--
Evandro Menezes
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS
2016-01-26 16:05 [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS James Greenhalgh
2016-01-27 21:49 ` Evandro Menezes
@ 2016-02-08 12:52 ` James Greenhalgh
2016-02-15 10:49 ` James Greenhalgh
2016-02-16 8:47 ` Marcus Shawcroft
2 siblings, 1 reply; 5+ messages in thread
From: James Greenhalgh @ 2016-02-08 12:52 UTC (permalink / raw)
To: gcc-patches; +Cc: nd, richard.earnshaw, marcus.shawcroft
On Tue, Jan 26, 2016 at 04:04:47PM +0000, James Greenhalgh wrote:
>
> Hi,
>
> In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction
> available when compiling with -march=armv8.1-a are only usable with
> a register number in the range 0 to 15 for operand 3, as gas will point
> out:
>
> Error: register number out of range 0 to 15 at
> operand 3 -- `sqrdmlsh v2.4h,v4.4h,v23.h[5]'
>
> This patch teaches GCC to avoid registers outside of this range when
> appropriate, in the same fashion as we do for other instructions with
> this limitation.
>
> Tested on an internal testsuite targeting Neon intrinsics.
>
> OK?
*ping*
Thanks,
James
> ---
> 2016-01-25 James Greenhalgh <james.greenhalgh@arm.com>
>
> * config/aarch64/aarch64.md
> (arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
> constraints for operand 3.
> (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
>
> diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
> index e1f5682..0b46e78 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -3240,7 +3240,7 @@
> [(match_operand:VDQHS 1 "register_operand" "0")
> (match_operand:VDQHS 2 "register_operand" "w")
> (vec_select:<VEL>
> - (match_operand:<VCOND> 3 "register_operand" "w")
> + (match_operand:<VCOND> 3 "register_operand" "<vwx>")
> (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
> SQRDMLH_AS))]
> "TARGET_SIMD_RDMA"
> @@ -3258,7 +3258,7 @@
> [(match_operand:SD_HSI 1 "register_operand" "0")
> (match_operand:SD_HSI 2 "register_operand" "w")
> (vec_select:<VEL>
> - (match_operand:<VCOND> 3 "register_operand" "w")
> + (match_operand:<VCOND> 3 "register_operand" "<vwx>")
> (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
> SQRDMLH_AS))]
> "TARGET_SIMD_RDMA"
> @@ -3278,7 +3278,7 @@
> [(match_operand:VDQHS 1 "register_operand" "0")
> (match_operand:VDQHS 2 "register_operand" "w")
> (vec_select:<VEL>
> - (match_operand:<VCONQ> 3 "register_operand" "w")
> + (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
> (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
> SQRDMLH_AS))]
> "TARGET_SIMD_RDMA"
> @@ -3296,7 +3296,7 @@
> [(match_operand:SD_HSI 1 "register_operand" "0")
> (match_operand:SD_HSI 2 "register_operand" "w")
> (vec_select:<VEL>
> - (match_operand:<VCONQ> 3 "register_operand" "w")
> + (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
> (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
> SQRDMLH_AS))]
> "TARGET_SIMD_RDMA"
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS
2016-02-08 12:52 ` James Greenhalgh
@ 2016-02-15 10:49 ` James Greenhalgh
0 siblings, 0 replies; 5+ messages in thread
From: James Greenhalgh @ 2016-02-15 10:49 UTC (permalink / raw)
To: gcc-patches; +Cc: nd, richard.earnshaw, marcus.shawcroft
On Mon, Feb 08, 2016 at 12:52:00PM +0000, James Greenhalgh wrote:
> On Tue, Jan 26, 2016 at 04:04:47PM +0000, James Greenhalgh wrote:
> >
> > Hi,
> >
> > In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction
> > available when compiling with -march=armv8.1-a are only usable with
> > a register number in the range 0 to 15 for operand 3, as gas will point
> > out:
> >
> > Error: register number out of range 0 to 15 at
> > operand 3 -- `sqrdmlsh v2.4h,v4.4h,v23.h[5]'
> >
> > This patch teaches GCC to avoid registers outside of this range when
> > appropriate, in the same fashion as we do for other instructions with
> > this limitation.
> >
> > Tested on an internal testsuite targeting Neon intrinsics.
> >
> > OK?
>
> *ping*
*ping^2*
Thanks,
James
> > ---
> > 2016-01-25 James Greenhalgh <james.greenhalgh@arm.com>
> >
> > * config/aarch64/aarch64.md
> > (arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
> > constraints for operand 3.
> > (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
> >
>
> > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
> > index e1f5682..0b46e78 100644
> > --- a/gcc/config/aarch64/aarch64-simd.md
> > +++ b/gcc/config/aarch64/aarch64-simd.md
> > @@ -3240,7 +3240,7 @@
> > [(match_operand:VDQHS 1 "register_operand" "0")
> > (match_operand:VDQHS 2 "register_operand" "w")
> > (vec_select:<VEL>
> > - (match_operand:<VCOND> 3 "register_operand" "w")
> > + (match_operand:<VCOND> 3 "register_operand" "<vwx>")
> > (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
> > SQRDMLH_AS))]
> > "TARGET_SIMD_RDMA"
> > @@ -3258,7 +3258,7 @@
> > [(match_operand:SD_HSI 1 "register_operand" "0")
> > (match_operand:SD_HSI 2 "register_operand" "w")
> > (vec_select:<VEL>
> > - (match_operand:<VCOND> 3 "register_operand" "w")
> > + (match_operand:<VCOND> 3 "register_operand" "<vwx>")
> > (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
> > SQRDMLH_AS))]
> > "TARGET_SIMD_RDMA"
> > @@ -3278,7 +3278,7 @@
> > [(match_operand:VDQHS 1 "register_operand" "0")
> > (match_operand:VDQHS 2 "register_operand" "w")
> > (vec_select:<VEL>
> > - (match_operand:<VCONQ> 3 "register_operand" "w")
> > + (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
> > (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
> > SQRDMLH_AS))]
> > "TARGET_SIMD_RDMA"
> > @@ -3296,7 +3296,7 @@
> > [(match_operand:SD_HSI 1 "register_operand" "0")
> > (match_operand:SD_HSI 2 "register_operand" "w")
> > (vec_select:<VEL>
> > - (match_operand:<VCONQ> 3 "register_operand" "w")
> > + (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
> > (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
> > SQRDMLH_AS))]
> > "TARGET_SIMD_RDMA"
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS
2016-01-26 16:05 [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS James Greenhalgh
2016-01-27 21:49 ` Evandro Menezes
2016-02-08 12:52 ` James Greenhalgh
@ 2016-02-16 8:47 ` Marcus Shawcroft
2 siblings, 0 replies; 5+ messages in thread
From: Marcus Shawcroft @ 2016-02-16 8:47 UTC (permalink / raw)
To: James Greenhalgh; +Cc: gcc-patches, nd, Richard Earnshaw, Marcus Shawcroft
On 26 January 2016 at 16:04, James Greenhalgh <james.greenhalgh@arm.com> wrote:
> 2016-01-25 James Greenhalgh <james.greenhalgh@arm.com>
>
> * config/aarch64/aarch64.md
> (arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
> constraints for operand 3.
> (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
>
OK /Marcus
^ permalink raw reply [flat|nested] 5+ messages in thread
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2016-01-26 16:05 [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS James Greenhalgh
2016-01-27 21:49 ` Evandro Menezes
2016-02-08 12:52 ` James Greenhalgh
2016-02-15 10:49 ` James Greenhalgh
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