From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 49027 invoked by alias); 29 Jan 2016 17:07:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 48954 invoked by uid 89); 29 Jan 2016 17:07:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.0 required=5.0 tests=BAYES_50,KAM_LOTSOFHASH,RP_MATCHES_RCVD,SPF_PASS autolearn=no version=3.3.2 spammy=op_type, sk:arm_out, 437, 877,7 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 29 Jan 2016 17:07:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 634AC49 for ; Fri, 29 Jan 2016 09:06:30 -0800 (PST) Received: from [10.2.206.221] (e107157-lin.cambridge.arm.com [10.2.206.221]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4ECDA3F2E5 for ; Fri, 29 Jan 2016 09:07:12 -0800 (PST) Subject: Re: [RFC][PATCH , ARM 2/8] Add RTL patterns for thumb1 push/pop To: gcc-patches@gcc.gnu.org References: <000e01d13f7f$22ca8830$685f9890$@foss.arm.com> From: "Andre Vieira (lists)" Message-ID: <56AB9C3E.6080100@arm.com> Date: Fri, 29 Jan 2016 17:07:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <000e01d13f7f$22ca8830$685f9890$@foss.arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2016-01/txt/msg02328.txt.bz2 On 26/12/15 01:45, Thomas Preud'homme wrote: > [Sending on behalf of Andre Vieira] > > Hello, > > This patch adds RTL patterns for the push and pop instructions for thumb1. These are needed by subsequent patches in the series. > > *** gcc/ChangeLog *** > 2015-10-27 Andre Vieira > Thomas Preud'homme > > * gcc/config/arm/arm-ldmstm.nl (constr thumb): Enabled > stackpointer to be written/read. > * gcc/config/arm/ldmstm.md: Regenerated. > * gcc/config/arm/thumb1.md (*thumb1_pop_single): New. > (*thumb1_load_multiple_operation): New. > * gcc/config/arm/arm.c (thumb_pop): Fix of comment. > > > diff --git a/gcc/config/arm/arm-ldmstm.ml b/gcc/config/arm/arm-ldmstm.ml > index 62982df594d5d4a1407df359e927c66986a9788c..f3ee741e93927d8d44a9eccec8970b46a8984216 100644 > --- a/gcc/config/arm/arm-ldmstm.ml > +++ b/gcc/config/arm/arm-ldmstm.ml > @@ -63,7 +63,7 @@ let rec final_offset addrmode nregs = > | DB -> -4 * nregs > > let constr thumb = > - if thumb then "l" else "rk" > + if thumb then "lk" else "rk" > > let inout_constr op_type = > match op_type with > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index 06a6184ee0c4ed1a7cec1de4c1786e297cc57872..2223101fbf96bceb4beb3a7d6cb04162481dc3bf 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -23773,8 +23773,8 @@ thumb1_emit_multi_reg_push (unsigned long mask, unsigned long real_regs) > return insn; > } > > -/* Emit code to push or pop registers to or from the stack. F is the > - assembly file. MASK is the registers to pop. */ > +/* Emit code to pop registers from the stack. F is the assembly file. > + MASK is the registers to pop. */ > static void > thumb_pop (FILE *f, unsigned long mask) > { > diff --git a/gcc/config/arm/ldmstm.md b/gcc/config/arm/ldmstm.md > index ebb09ab86e799f3606e0988980edf3cd0189272b..8c0472e07799bd9d08759e35b6b98f3536d3d013 100644 > --- a/gcc/config/arm/ldmstm.md > +++ b/gcc/config/arm/ldmstm.md > @@ -43,7 +43,7 @@ > (define_insn "*thumb_ldm4_ia" > [(match_parallel 0 "load_multiple_operation" > [(set (match_operand:SI 1 "low_register_operand" "") > - (mem:SI (match_operand:SI 5 "s_register_operand" "l"))) > + (mem:SI (match_operand:SI 5 "s_register_operand" "lk"))) > (set (match_operand:SI 2 "low_register_operand" "") > (mem:SI (plus:SI (match_dup 5) > (const_int 4)))) > @@ -80,7 +80,7 @@ > > (define_insn "*thumb_ldm4_ia_update" > [(match_parallel 0 "load_multiple_operation" > - [(set (match_operand:SI 5 "s_register_operand" "+&l") > + [(set (match_operand:SI 5 "s_register_operand" "+&lk") > (plus:SI (match_dup 5) (const_int 16))) > (set (match_operand:SI 1 "low_register_operand" "") > (mem:SI (match_dup 5))) > @@ -133,7 +133,7 @@ > > (define_insn "*thumb_stm4_ia_update" > [(match_parallel 0 "store_multiple_operation" > - [(set (match_operand:SI 5 "s_register_operand" "+&l") > + [(set (match_operand:SI 5 "s_register_operand" "+&lk") > (plus:SI (match_dup 5) (const_int 16))) > (set (mem:SI (match_dup 5)) > (match_operand:SI 1 "low_register_operand" "")) > @@ -491,7 +491,7 @@ > (define_insn "*thumb_ldm3_ia" > [(match_parallel 0 "load_multiple_operation" > [(set (match_operand:SI 1 "low_register_operand" "") > - (mem:SI (match_operand:SI 4 "s_register_operand" "l"))) > + (mem:SI (match_operand:SI 4 "s_register_operand" "lk"))) > (set (match_operand:SI 2 "low_register_operand" "") > (mem:SI (plus:SI (match_dup 4) > (const_int 4)))) > @@ -522,7 +522,7 @@ > > (define_insn "*thumb_ldm3_ia_update" > [(match_parallel 0 "load_multiple_operation" > - [(set (match_operand:SI 4 "s_register_operand" "+&l") > + [(set (match_operand:SI 4 "s_register_operand" "+&lk") > (plus:SI (match_dup 4) (const_int 12))) > (set (match_operand:SI 1 "low_register_operand" "") > (mem:SI (match_dup 4))) > @@ -568,7 +568,7 @@ > > (define_insn "*thumb_stm3_ia_update" > [(match_parallel 0 "store_multiple_operation" > - [(set (match_operand:SI 4 "s_register_operand" "+&l") > + [(set (match_operand:SI 4 "s_register_operand" "+&lk") > (plus:SI (match_dup 4) (const_int 12))) > (set (mem:SI (match_dup 4)) > (match_operand:SI 1 "low_register_operand" "")) > @@ -877,7 +877,7 @@ > (define_insn "*thumb_ldm2_ia" > [(match_parallel 0 "load_multiple_operation" > [(set (match_operand:SI 1 "low_register_operand" "") > - (mem:SI (match_operand:SI 3 "s_register_operand" "l"))) > + (mem:SI (match_operand:SI 3 "s_register_operand" "lk"))) > (set (match_operand:SI 2 "low_register_operand" "") > (mem:SI (plus:SI (match_dup 3) > (const_int 4))))])] > @@ -902,7 +902,7 @@ > > (define_insn "*thumb_ldm2_ia_update" > [(match_parallel 0 "load_multiple_operation" > - [(set (match_operand:SI 3 "s_register_operand" "+&l") > + [(set (match_operand:SI 3 "s_register_operand" "+&lk") > (plus:SI (match_dup 3) (const_int 8))) > (set (match_operand:SI 1 "low_register_operand" "") > (mem:SI (match_dup 3))) > @@ -941,7 +941,7 @@ > > (define_insn "*thumb_stm2_ia_update" > [(match_parallel 0 "store_multiple_operation" > - [(set (match_operand:SI 3 "s_register_operand" "+&l") > + [(set (match_operand:SI 3 "s_register_operand" "+&lk") > (plus:SI (match_dup 3) (const_int 8))) > (set (mem:SI (match_dup 3)) > (match_operand:SI 1 "low_register_operand" "")) > diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md > index 7e3bcb465385031b7350397fb8fb0e0c0a467fb0..d2a0420a2e9c71bb954d134fb88a86d694cf786d 100644 > --- a/gcc/config/arm/thumb1.md > +++ b/gcc/config/arm/thumb1.md > @@ -1819,4 +1819,32 @@ > }" > [(set_attr "type" "mov_reg")] > ) > + > +(define_insn "*thumb1_load_multiple_with_writeback" > + [(match_parallel 0 "load_multiple_operation" > + [(set (match_operand:SI 1 "s_register_operand" "+kl") > + (plus:SI (match_dup 1) > + (match_operand:SI 2 "const_int_I_operand" "I"))) > + (set (match_operand:SI 3 "s_register_operand" "=kl") > + (mem:SI (match_dup 1)))])] > + "TARGET_THUMB1 && (reload_in_progress || reload_completed)" > + { > + arm_output_multireg_pop (operands, /*return_pc=*/ false, > + /*cond=*/ const_true_rtx, > + /*reverse=*/ false, > + /*update=*/ true); > + return ""; > + } > + [(set_attr "type" "load4")] > +) > + > +;; Pop a single register as its size is preferred over a post-incremental load > +(define_insn "*thumb1_pop_single" > + [(set (match_operand:SI 0 "low_register_operand" "=l") > + (mem:SI (post_inc:SI (reg:SI SP_REGNUM))))] > + "TARGET_THUMB1 && (reload_in_progress || reload_completed)" > + "pop\t{%0}" > + [(set_attr "type" "load1") > + (set_attr "length" "2")] > +) > > > We welcome any comment. > > Cheers, > > Andre > Hi, Dropping this patch from the series as I realized it not required for subsequent patches. Cheers, Andre