From: Evandro Menezes <e.menezes@samsung.com>
To: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
nd <nd@arm.com>, Marcus Shawcroft <Marcus.Shawcroft@arm.com>,
Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>,
James Greenhalgh <James.Greenhalgh@arm.com>
Subject: Re: [PATCH][AArch64] Replace insn to zero up DF register
Date: Tue, 01 Mar 2016 19:08:00 -0000 [thread overview]
Message-ID: <56D5E8B6.1090900@samsung.com> (raw)
In-Reply-To: <AM3PR08MB00883516D1FA6B9AB80AEA9E83BB0@AM3PR08MB0088.eurprd08.prod.outlook.com>
On 03/01/16 13:02, Wilco Dijkstra wrote:
> Evandro Menezes wrote:
>> The meaning of these attributes are not clear to me. Is there a
>> reference somewhere about which insns are FP or SIMD or neither?
> The meaning should be clear, "fp" is a floating point instruction, "simd" a SIMD one
> as defined in ARM-ARM.
>
>> Indeed, I had to add the Y for the f_mcr insn to match it with nosimd.
>> However, I didn't feel that it should be moved to the right, since it's
>> already disparaged. Am I missing something detail?
> It might not matter for this specific case, but I have seen reload forcing the very
> first alternative without looking at any costs or preferences - as long as it is legal.
> This suggests we need to order alternatives from most preferred alternative to least
> preferred one.
>
> I think it is good enough for commit, James?
Methinks that my issue with those attributes is that I'm not as fluent
in AArch64 as I'd like to be.
Please, feel free to edit the patch changing the order then.
Thank you,
--
Evandro Menezes
next prev parent reply other threads:[~2016-03-01 19:08 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-22 13:52 Wilco Dijkstra
2016-01-27 23:14 ` Evandro Menezes
2016-02-26 12:37 ` Wilco Dijkstra
2016-02-26 22:43 ` Evandro Menezes
2016-02-29 18:07 ` Wilco Dijkstra
2016-02-29 23:11 ` Evandro Menezes
2016-03-01 19:02 ` Wilco Dijkstra
2016-03-01 19:08 ` Evandro Menezes [this message]
2016-03-09 21:36 ` Evandro Menezes
2016-03-10 13:23 ` James Greenhalgh
2016-03-10 16:27 ` Evandro Menezes
2016-03-10 16:32 ` Evandro Menezes
2016-03-10 16:37 ` James Greenhalgh
2016-04-25 19:20 ` [PATCH][AArch64] Replace insn to zero up SIMD registers Evandro Menezes
2016-04-26 13:25 ` Wilco Dijkstra
2016-04-27 19:55 ` Evandro Menezes
-- strict thread matches above, loose matches on Subject: below --
2015-10-19 23:41 [PATCH][AArch64] Replace insn to zero up DF register Evandro Menezes
2015-10-19 23:52 ` Andrew Pinski
2015-10-20 0:33 ` Andrew Pinski
2015-10-20 14:46 ` Andrew Pinski
2015-10-28 18:49 ` Evandro Menezes
2015-10-30 10:26 ` Marcus Shawcroft
2015-11-09 22:59 ` Evandro Menezes
2015-12-03 21:01 ` Evandro Menezes
2015-11-19 22:01 ` Evandro Menezes
2015-12-16 21:30 ` Evandro Menezes
2016-01-13 0:06 ` Evandro Menezes
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