From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 1543 invoked by alias); 11 Apr 2016 13:27:19 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 1517 invoked by uid 89); 11 Apr 2016 13:27:18 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Earnshaw, earnshaw, tst, Hx-languages-length:1881 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 11 Apr 2016 13:27:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 254C8254; Mon, 11 Apr 2016 06:25:54 -0700 (PDT) Received: from [10.2.206.200] (e100706-lin.cambridge.arm.com [10.2.206.200]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5141A3F246; Mon, 11 Apr 2016 06:27:06 -0700 (PDT) Message-ID: <570BA628.4070606@foss.arm.com> Date: Mon, 11 Apr 2016 13:27:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "Richard Earnshaw (lists)" , GCC Patches CC: Ramana Radhakrishnan Subject: Re: [PATCH][ARM] PR target/70566 Check that condition register is dead in tst-imm -> lsls-imm Thumb2 peepholes References: <570673FB.7020803@foss.arm.com> <57077A47.2070100@arm.com> In-Reply-To: <57077A47.2070100@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2016-04/txt/msg00471.txt.bz2 On 08/04/16 10:30, Richard Earnshaw (lists) wrote: > On 07/04/16 15:51, Kyrill Tkachov wrote: >> Hi all, >> >> In this wrong-code PR we have a Thumb2 peephole transforming: >> tst r3, #2 >> bne .L3 >> beq .L6 >> >> into: >> lsls r3, r3, #30 // LSLS is shorter than TST in Thumb2 >> bmi .L3 >> beq .L6 >> >> that is, the branch following the extract+compare has its condition >> properly changed but the >> following branch doesn't get updated to check the opposite condition of >> MI (PL). >> Since the peepholes in thumb2.md only see the compare and a single >> branch the solution, >> suggested by Richard, is to guard those peepholes on the condition that >> the condition register >> is dead after the first branch. This patch does that and with it we no >> longer perform the transformation >> on the testcase. I've checked manually that we still perform the >> peephole when the condition register >> is indeed dead after the sequence. >> >> Bootstrapped and tested on on arm-none-linux-gnueabihf with >> --with-mode=thumb as this affects only >> Thumb2 codegen. >> >> Ok for trunk? >> >> This PR also affects GCC 5 and 4.9 so I'll be testing the patch there as >> well. >> >> Thanks, >> Kyrill >> >> >> 2016-04-07 Kyrylo Tkachov >> >> PR target/70566 >> * config/arm/thumb2.md (tst + branch-> lsls + branch >> peephole below *orsi_not_shiftsi_si): Require that condition >> register is dead after the peephole. >> (second peephole after the above): Likewise. >> >> 2016-04-07 Kyrylo Tkachov >> >> PR target/70566 >> * gcc.c-torture/execute/pr70566.c: New test. > > OK. Thanks, the patch has passed bootstrap and test on the GCC 5 and 4.9 branches. Is it ok to backport it there as well? Thanks, Kyrill > > R.