From: Evandro Menezes <e.menezes@samsung.com>
To: James Greenhalgh <james.greenhalgh@arm.com>
Cc: Wilco Dijkstra <Wilco.Dijkstra@arm.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
nd <nd@arm.com>, Marcus Shawcroft <Marcus.Shawcroft@arm.com>,
Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>,
richard.earnshaw@arm.com
Subject: Re: [PATCH][AArch64] Replace insn to zero up SIMD registers
Date: Mon, 25 Apr 2016 19:20:00 -0000 [thread overview]
Message-ID: <571E6DD9.9010401@samsung.com> (raw)
In-Reply-To: <20160310163736.GA8272@arm.com>
[-- Attachment #1: Type: text/plain, Size: 1183 bytes --]
On 03/10/16 10:37, James Greenhalgh wrote:
> On Thu, Mar 10, 2016 at 10:32:15AM -0600, Evandro Menezes wrote:
>>> I agree to postpone until GCC 7.
>>>
>>> [AArch64] Replace insn to zero up SIMD registers
>>>
>>> gcc/
>>> * config/aarch64/aarch64.md
>>> (*movhf_aarch64): Add "movi %0, #0" to zero up register.
>>> (*movsf_aarch64): Likewise and add "simd" attributes.
>>> (*movdf_aarch64): Likewise.
>>>
>>> This patch removes the FP attributes from the HF, SF, DF, TF moves.
> Thanks for sticking with it. This is OK for GCC 7 when development
> opens.
>
> Remember to mention the most recent changes in your Changelog entry
> (Remove "fp" attribute from *movhf_aarch64 and *movtf_aarch64).
gcc/
* config/aarch64/aarch64.md
(*movhf_aarch64): Add "movi %0, #0" to zero up register and
remove the "fp" attributes.
(*movsf_aarch64): Add "movi %0, #0" to zero up register and
add the "simd" attributes.
(*movdf_aarch64): Likewise.
(*movtf_aarch64): Remove the "fp" attributes.
OK to commit?
Thank you,
--
Evandro Menezes
[-- Attachment #2: 0001-AArch64-Replace-insn-to-zero-up-SIMD-registers.patch --]
[-- Type: text/x-patch, Size: 3973 bytes --]
From b319dead6f72eb36ebedbf27547b2f86f2f9d41f Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.menezes@samsung.com>
Date: Mon, 19 Oct 2015 18:31:48 -0500
Subject: [PATCH] [AArch64] Replace insn to zero up SIMD registers
gcc/
* config/aarch64/aarch64.md
(*movhf_aarch64): Add "movi %0, #0" to zero up register and
remove the "fp" attributes.
(*movsf_aarch64): Add "movi %0, #0" to zero up register and
add the "simd" attributes.
(*movdf_aarch64): Likewise.
(*movtf_aarch64): Remove the "fp" attributes.
---
gcc/config/aarch64/aarch64.md | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index f423284..9b282f1 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1178,11 +1178,12 @@
)
(define_insn "*movhf_aarch64"
- [(set (match_operand:HF 0 "nonimmediate_operand" "=w, ?r,w,w,m,r,m ,r")
- (match_operand:HF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))]
+ [(set (match_operand:HF 0 "nonimmediate_operand" "=w,w ,?r,w,w,m,r,m ,r")
+ (match_operand:HF 1 "general_operand" "Y ,?rY, w,w,m,w,m,rY,r"))]
"TARGET_FLOAT && (register_operand (operands[0], HFmode)
|| aarch64_reg_or_fp_zero (operands[1], HFmode))"
"@
+ movi\\t%0.4h, #0
mov\\t%0.h[0], %w1
umov\\t%w0, %1.h[0]
mov\\t%0.h[0], %1.h[0]
@@ -1191,18 +1192,18 @@
ldrh\\t%w0, %1
strh\\t%w1, %0
mov\\t%w0, %w1"
- [(set_attr "type" "neon_from_gp,neon_to_gp,neon_move,\
+ [(set_attr "type" "neon_move,neon_from_gp,neon_to_gp,neon_move,\
f_loads,f_stores,load1,store1,mov_reg")
- (set_attr "simd" "yes,yes,yes,*,*,*,*,*")
- (set_attr "fp" "*,*,*,yes,yes,*,*,*")]
+ (set_attr "simd" "yes,yes,yes,yes,*,*,*,*,*")]
)
(define_insn "*movsf_aarch64"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r")
- (match_operand:SF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r")
+ (match_operand:SF 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))]
"TARGET_FLOAT && (register_operand (operands[0], SFmode)
|| aarch64_reg_or_fp_zero (operands[1], SFmode))"
"@
+ movi\\t%0.2s, #0
fmov\\t%s0, %w1
fmov\\t%w0, %s1
fmov\\t%s0, %s1
@@ -1212,16 +1213,18 @@
ldr\\t%w0, %1
str\\t%w1, %0
mov\\t%w0, %w1"
- [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\
- f_loads,f_stores,load1,store1,mov_reg")]
+ [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,\
+ f_loads,f_stores,load1,store1,mov_reg")
+ (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")]
)
(define_insn "*movdf_aarch64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r")
- (match_operand:DF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r")
+ (match_operand:DF 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))]
"TARGET_FLOAT && (register_operand (operands[0], DFmode)
|| aarch64_reg_or_fp_zero (operands[1], DFmode))"
"@
+ movi\\t%d0, #0
fmov\\t%d0, %x1
fmov\\t%x0, %d1
fmov\\t%d0, %d1
@@ -1231,8 +1234,9 @@
ldr\\t%x0, %1
str\\t%x1, %0
mov\\t%x0, %x1"
- [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\
- f_loadd,f_stored,load1,store1,mov_reg")]
+ [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,\
+ f_loadd,f_stored,load1,store1,mov_reg")
+ (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")]
)
(define_insn "*movtf_aarch64"
@@ -1257,7 +1261,6 @@
[(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\
f_loadd,f_stored,load2,store2,store2")
(set_attr "length" "4,8,8,8,4,4,4,4,4,4,4")
- (set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*,*")
(set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")]
)
--
2.6.3
next prev parent reply other threads:[~2016-04-25 19:20 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-22 13:52 [PATCH][AArch64] Replace insn to zero up DF register Wilco Dijkstra
2016-01-27 23:14 ` Evandro Menezes
2016-02-26 12:37 ` Wilco Dijkstra
2016-02-26 22:43 ` Evandro Menezes
2016-02-29 18:07 ` Wilco Dijkstra
2016-02-29 23:11 ` Evandro Menezes
2016-03-01 19:02 ` Wilco Dijkstra
2016-03-01 19:08 ` Evandro Menezes
2016-03-09 21:36 ` Evandro Menezes
2016-03-10 13:23 ` James Greenhalgh
2016-03-10 16:27 ` Evandro Menezes
2016-03-10 16:32 ` Evandro Menezes
2016-03-10 16:37 ` James Greenhalgh
2016-04-25 19:20 ` Evandro Menezes [this message]
2016-04-26 13:25 ` [PATCH][AArch64] Replace insn to zero up SIMD registers Wilco Dijkstra
2016-04-27 19:55 ` Evandro Menezes
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=571E6DD9.9010401@samsung.com \
--to=e.menezes@samsung.com \
--cc=Kyrylo.Tkachov@arm.com \
--cc=Marcus.Shawcroft@arm.com \
--cc=Wilco.Dijkstra@arm.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=james.greenhalgh@arm.com \
--cc=nd@arm.com \
--cc=richard.earnshaw@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).