From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25391 invoked by alias); 28 Apr 2016 18:50:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 25382 invoked by uid 89); 28 Apr 2016 18:50:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=AWL,BAYES_00 autolearn=ham version=3.3.2 spammy=cbn, alternatives, chs, recognition X-HELO: mailrelay7.public.one.com Received: from mailrelay7.public.one.com (HELO mailrelay7.public.one.com) (91.198.169.215) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Thu, 28 Apr 2016 18:50:18 +0000 X-HalOne-Cookie: 01191e44417d14534978a11c8d34f5df81f640e5 X-HalOne-ID: 0a46c486-0d72-11e6-bb5b-b82a72cffc46 Received: from localhost.localdomain (unknown [91.135.11.213]) by smtpfilter4.public.one.com (Halon Mail Gateway) with ESMTPSA; Thu, 28 Apr 2016 18:50:12 +0000 (UTC) Subject: Re: [PATCHv2 5/7] gcc/arc: Add nps400 bitops support To: Andrew Burgess , gcc-patches@gcc.gnu.org References: <0a3b33f107ff2e178bac719c5ed2939bd887abfd.1461238348.git.andrew.burgess@embecosm.com> Cc: noamca@mellanox.com, Claudiu.Zissulescu@synopsys.com From: Joern Wolfgang Rennecke Message-ID: <57225B63.8070802@amylaar.uk> Date: Thu, 28 Apr 2016 18:50:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.1.0 MIME-Version: 1.0 In-Reply-To: <0a3b33f107ff2e178bac719c5ed2939bd887abfd.1461238348.git.andrew.burgess@embecosm.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2016-04/txt/msg01888.txt.bz2 On 21/04/16 12:39, Andrew Burgess wrote: > Add support for nps400 bit operation instructions. There's a new flag > -mbitops that turns this feature on. There are new instructions, some > changes to existing instructions, a new register class to support the > new instructions, and some new expand and peephole optimisations. > > gcc/ChangeLog: > > * config/arc/arc.c (arc_conditional_register_usage): Take > TARGET_RRQ_CLASS into account. > (arc_print_operand): Support printing 'p' and 's' operands. > * config/arc/arc.h (TARGET_NPS_BITOPS_DEFAULT): Provide default > as 0. > (TARGET_RRQ_CLASS): Define. > (IS_POWEROF2_OR_0_P): Define. > * config/arc/arc.md (*movsi_insn): Add w/Clo, w/Chi, and w/Cbi > alternatives. > (*tst_movb): New define_insn. > (*tst): Avoid recognition if it could prevent '*tst_movb' > combination; replace c/CnL with c/Chs alternative. > (*tst_bitfield_tst): New define_insn. > (*tst_bitfield_asr): New define_insn. > (*tst_bitfield): New define_insn. > (andsi3_i): Add Rrq variant. > (extzv): New define_expand. > (insv): New define_expand. > (*insv_i): New define_insn. > (*movb): New define_insn. > (*movb_signed): New define_insn. > (*movb_high): New define_insn. > (*movb_high_signed): New define_insn. > (*movb_high_signed + 1): New define_split pattern. > (*mrgb): New define_insn. > (*mrgb + 1): New define_peephole2 pattern. > (*mrgb + 2): New define_peephole2 pattern. > * config/arc/arc.opt (mbitops): New option for nps400, uses > TARGET_NPS_BITOPS_DEFAULT. > * config/arc/constraints.md (q): Make register class conditional. > (Rrq): New register constraint. > (Chs): New constraint. > (Clo): New constraint. > (Chi): New constraint. > (Cbf): New constraint. > (Cbn): New constraint. > (C18): New constraint. > (Cbi): New constraint. > > gcc/testsuite/ChangeLog: > > * gcc.target/arc/extzv-1.c: New file. > * gcc.target/arc/insv-1.c: New file. > * gcc.target/arc/insv-2.c: New file. > * gcc.target/arc/movb-1.c: New file. > * gcc.target/arc/movb-2.c: New file. > * gcc.target/arc/movb-3.c: New file. > * gcc.target/arc/movb-4.c: New file. > * gcc.target/arc/movb-5.c: New file. > * gcc.target/arc/movb_cl-1.c: New file. > * gcc.target/arc/movb_cl-2.c: New file. > * gcc.target/arc/movbi_cl-1.c: New file. > * gcc.target/arc/movl-1.c: New file. > Thanks. I have applied this patch.