From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 129789 invoked by alias); 13 May 2016 08:39:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 129771 invoked by uid 89); 13 May 2016 08:39:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=2.3 required=5.0 tests=BAYES_50,GAPPY_SUBJECT,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=minus, TEST_VRND2, arm_v8_neon_ok, test_vrnd2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 13 May 2016 08:38:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1AFCD3A; Fri, 13 May 2016 01:39:08 -0700 (PDT) Received: from [10.2.206.198] (e104437-lin.cambridge.arm.com [10.2.206.198]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E863C3F21A; Fri, 13 May 2016 01:38:53 -0700 (PDT) Subject: Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests. To: Christophe Lyon References: <1462973041-7911-1-git-send-email-christophe.lyon@linaro.org> <1462973041-7911-10-git-send-email-christophe.lyon@linaro.org> <5734428F.5020102@foss.arm.com> Cc: "gcc-patches@gcc.gnu.org" From: Jiong Wang Message-ID: <5735929C.2060206@foss.arm.com> Date: Fri, 13 May 2016 08:39:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2016-05/txt/msg00943.txt.bz2 On 12/05/16 13:56, Christophe Lyon wrote: > On 12 May 2016 at 10:45, Jiong Wang wrote: >> >> On 11/05/16 14:23, Christophe Lyon wrote: >>> 2016-05-02 Christophe Lyon >>> >>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New. >>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: >>> New. >>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: >>> New. >>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: >>> New. >>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: >>> New. >>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: >>> New. >>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: >>> New. >>> >>> Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737 >>> >>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c >>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c >>> new file mode 100644 >>> index 0000000..5f492d4 >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c >>> @@ -0,0 +1,16 @@ >>> +/* { dg-require-effective-target arm_v8_neon_ok } */ >>> +/* { dg-add-options arm_v8_neon } */ >>> + >>> +#include >>> +#include "arm-neon-ref.h" >>> +#include "compute-ref-data.h" >>> + >>> +/* Expected results. */ >>> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; >>> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, >>> + 0xc1600000, 0xc1500000 }; >>> + >>> +#define INSN vrnd >>> +#define TEST_MSG "VRND" >>> + >>> +#include "vrndX.inc" >>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc >>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc >>> new file mode 100644 >>> index 0000000..629240d >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc >>> @@ -0,0 +1,43 @@ >>> +#define FNNAME1(NAME) exec_ ## NAME >>> +#define FNNAME(NAME) FNNAME1 (NAME) >>> + >>> +void FNNAME (INSN) (void) >>> +{ >>> + /* vector_res = vrndX (vector), then store the result. */ >>> +#define TEST_VRND2(INSN, Q, T1, T2, W, N) \ >>> + VECT_VAR (vector_res, T1, W, N) = \ >>> + INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N)); \ >>> + vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N), \ >>> + VECT_VAR (vector_res, T1, W, N)) >>> + >>> + /* Two auxliary macros are necessary to expand INSN. */ >>> +#define TEST_VRND1(INSN, Q, T1, T2, W, N) \ >>> + TEST_VRND2 (INSN, Q, T1, T2, W, N) >>> + >>> +#define TEST_VRND(Q, T1, T2, W, N) \ >>> + TEST_VRND1 (INSN, Q, T1, T2, W, N) >>> + >>> + DECL_VARIABLE (vector, float, 32, 2); >>> + DECL_VARIABLE (vector, float, 32, 4); >>> + >>> + DECL_VARIABLE (vector_res, float, 32, 2); >>> + DECL_VARIABLE (vector_res, float, 32, 4); >>> + >>> + clean_results (); >>> + >>> + VLOAD (vector, buffer, , float, f, 32, 2); >>> + VLOAD (vector, buffer, q, float, f, 32, 4); >>> + >>> + TEST_VRND ( , float, f, 32, 2); >>> + TEST_VRND (q, float, f, 32, 4); >>> + >>> + CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, ""); >>> + CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, ""); >>> +} >>> + >>> +int >>> +main (void) >>> +{ >>> + FNNAME (INSN) (); >>> + return 0; >>> +} >>> >> Hi Christophe, >> >> I have a question on how test inputs are selected? >> >> For example vrndm is round to integral, towards minus infinity while vrnda >> is to nearest with ties to even, has these differences been tested? >> > Hi Jiong, > > For this particular case, no, I didn't specifically chose input values to check > these differences. > > This can be done as a follow-up? I think it's fine as this patch series itself is anyway a step forward on making sure all intrinsics are tested. Thanks. Regards, Jiong