From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 63919 invoked by alias); 16 May 2016 13:25:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 63904 invoked by uid 89); 16 May 2016 13:25:20 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=4057, sk:christo X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 16 May 2016 13:25:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 017EF3C; Mon, 16 May 2016 06:25:25 -0700 (PDT) Received: from [10.2.206.43] (e100706-lin.cambridge.arm.com [10.2.206.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 380F63F218; Mon, 16 May 2016 06:25:08 -0700 (PDT) Message-ID: <5739CA32.4000306@foss.arm.com> Date: Mon, 16 May 2016 13:25:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Christophe Lyon , gcc-patches@gcc.gnu.org Subject: Re: [Patch ARM/AArch64 01/11] Fix typo in vreinterpret.c test comment. References: <1462973041-7911-1-git-send-email-christophe.lyon@linaro.org> <1462973041-7911-2-git-send-email-christophe.lyon@linaro.org> In-Reply-To: <1462973041-7911-2-git-send-email-christophe.lyon@linaro.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2016-05/txt/msg01109.txt.bz2 On 11/05/16 14:23, Christophe Lyon wrote: > 2016-05-02 Christophe Lyon > > * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Fix typo in comment. Ok (I agree it's obvious) Thanks, Kyrill > Change-Id: I7244c0dc0a5ab2dbcec65b40c050f72f92707139 > > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c > index 9e45e25..d4e5768 100644 > --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c > @@ -405,7 +405,7 @@ VECT_VAR_DECL(expected_q_f32_9,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4, > VECT_VAR_DECL(expected_q_f32_10,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2, > 0xfff5fff4, 0xfff7fff6 }; > > -/* Expected results for vreinterpretq_xx_f32. */ > +/* Expected results for vreinterpret_xx_f32. */ > VECT_VAR_DECL(expected_xx_f32_1,int,8,8) [] = { 0x0, 0x0, 0x80, 0xc1, > 0x0, 0x0, 0x70, 0xc1 }; > VECT_VAR_DECL(expected_xx_f32_2,int,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };