From: Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>
To: Christophe Lyon <christophe.lyon@linaro.org>, gcc-patches@gcc.gnu.org
Subject: Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.
Date: Thu, 19 May 2016 16:22:00 -0000 [thread overview]
Message-ID: <573DE84A.1070503@foss.arm.com> (raw)
In-Reply-To: <1462973041-7911-10-git-send-email-christophe.lyon@linaro.org>
Hi Christophe,
On 11/05/16 14:23, Christophe Lyon wrote:
> 2016-05-02 Christophe Lyon <christophe.lyon@linaro.org>
>
> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: New.
> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: New.
> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: New.
> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: New.
> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: New.
> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: New.
Drop the gcc/testsuite from the ChangeLog entry. Just "* gcc.target/aarch64/..."
Ok with the fixed ChangeLog.
Thanks,
Kyrill
> Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> new file mode 100644
> index 0000000..5f492d4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> + 0xc1600000, 0xc1500000 };
> +
> +#define INSN vrnd
> +#define TEST_MSG "VRND"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
> new file mode 100644
> index 0000000..629240d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
> @@ -0,0 +1,43 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1 (NAME)
> +
> +void FNNAME (INSN) (void)
> +{
> + /* vector_res = vrndX (vector), then store the result. */
> +#define TEST_VRND2(INSN, Q, T1, T2, W, N) \
> + VECT_VAR (vector_res, T1, W, N) = \
> + INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N)); \
> + vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N), \
> + VECT_VAR (vector_res, T1, W, N))
> +
> + /* Two auxliary macros are necessary to expand INSN. */
> +#define TEST_VRND1(INSN, Q, T1, T2, W, N) \
> + TEST_VRND2 (INSN, Q, T1, T2, W, N)
> +
> +#define TEST_VRND(Q, T1, T2, W, N) \
> + TEST_VRND1 (INSN, Q, T1, T2, W, N)
> +
> + DECL_VARIABLE (vector, float, 32, 2);
> + DECL_VARIABLE (vector, float, 32, 4);
> +
> + DECL_VARIABLE (vector_res, float, 32, 2);
> + DECL_VARIABLE (vector_res, float, 32, 4);
> +
> + clean_results ();
> +
> + VLOAD (vector, buffer, , float, f, 32, 2);
> + VLOAD (vector, buffer, q, float, f, 32, 4);
> +
> + TEST_VRND ( , float, f, 32, 2);
> + TEST_VRND (q, float, f, 32, 4);
> +
> + CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
> + CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
> +}
> +
> +int
> +main (void)
> +{
> + FNNAME (INSN) ();
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
> new file mode 100644
> index 0000000..816fd28d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> + 0xc1600000, 0xc1500000 };
> +
> +#define INSN vrnda
> +#define TEST_MSG "VRNDA"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
> new file mode 100644
> index 0000000..029880c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> + 0xc1600000, 0xc1500000 };
> +
> +#define INSN vrndm
> +#define TEST_MSG "VRNDM"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
> new file mode 100644
> index 0000000..571243c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> + 0xc1600000, 0xc1500000 };
> +
> +#define INSN vrndn
> +#define TEST_MSG "VRNDN"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c
> new file mode 100644
> index 0000000..ff4771c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> + 0xc1600000, 0xc1500000 };
> +
> +#define INSN vrndp
> +#define TEST_MSG "VRNDP"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c
> new file mode 100644
> index 0000000..ff2357b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
> + 0xc1600000, 0xc1500000 };
> +
> +#define INSN vrndx
> +#define TEST_MSG "VRNDX"
> +
> +#include "vrndX.inc"
next prev parent reply other threads:[~2016-05-19 16:22 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-11 13:24 [Patch ARM/AArch64 00/11][testsuite] AdvSIMD intrinsics update Christophe Lyon
2016-05-11 13:24 ` [Patch ARM/AArch64 11/11] Add missing tests for vreinterpret, operating of fp16 type Christophe Lyon
2016-05-13 15:17 ` James Greenhalgh
2016-05-19 16:24 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 07/11] Add missing vget_lane fp16 tests Christophe Lyon
2016-05-13 14:38 ` James Greenhalgh
2016-05-16 13:41 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 04/11] Add forgotten vsliq_n_u64 test Christophe Lyon
2016-05-13 14:09 ` James Greenhalgh
2016-05-13 14:22 ` Christophe Lyon
2016-05-16 13:27 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 10/11] Add missing tests for intrinsics operating on poly64 and poly128 types Christophe Lyon
2016-05-13 15:16 ` James Greenhalgh
2016-05-19 16:23 ` Kyrill Tkachov
2016-05-23 9:12 ` Christophe Lyon
2016-05-11 13:24 ` [Patch ARM/AArch64 08/11] Add missing vstX_lane fp16 tests Christophe Lyon
2016-05-13 14:53 ` James Greenhalgh
2016-05-19 16:20 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests Christophe Lyon
2016-05-12 8:45 ` Jiong Wang
2016-05-12 12:56 ` Christophe Lyon
2016-05-13 8:39 ` Jiong Wang
2016-05-13 14:56 ` James Greenhalgh
2016-05-19 16:22 ` Kyrill Tkachov [this message]
2016-05-11 13:24 ` [Patch ARM/AArch64 06/11] Add missing vtst_p8 and vtstq_p8 tests Christophe Lyon
2016-05-13 14:37 ` James Greenhalgh
2016-05-13 14:41 ` Christophe Lyon
2016-05-13 14:48 ` James Greenhalgh
2016-05-19 11:54 ` Christophe Lyon
2016-05-20 13:49 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 05/11] Add missing vreinterpretq_p{8,16} tests Christophe Lyon
2016-05-13 14:15 ` James Greenhalgh
2016-05-16 13:31 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 03/11] AdvSIMD tests: be more verbose Christophe Lyon
2016-05-13 14:03 ` James Greenhalgh
2016-05-16 13:26 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 02/11] We can remove useless #ifdefs from these tests: vmul, vshl and vtst Christophe Lyon
2016-05-13 13:56 ` James Greenhalgh
2016-05-16 13:25 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 01/11] Fix typo in vreinterpret.c test comment Christophe Lyon
2016-05-13 13:53 ` James Greenhalgh
2016-05-16 13:25 ` Kyrill Tkachov
2016-05-13 15:32 ` [Patch ARM/AArch64 00/11][testsuite] AdvSIMD intrinsics update James Greenhalgh
[not found] <20160607154025.GC6963@e103625-lin.cambridge.arm.com>
[not found] ` <AM3PR08MB00886D803EBB28921F1C9E96835D0@AM3PR08MB0088.eurprd08.prod.outlook.com>
2016-06-08 7:37 ` [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests Christophe Lyon
2016-06-08 8:47 ` Christophe Lyon
2016-06-08 9:08 ` Christophe Lyon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=573DE84A.1070503@foss.arm.com \
--to=kyrylo.tkachov@foss.arm.com \
--cc=christophe.lyon@linaro.org \
--cc=gcc-patches@gcc.gnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).