From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 111217 invoked by alias); 19 May 2016 16:22:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 111189 invoked by uid 89); 19 May 2016 16:22:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.4 required=5.0 tests=BAYES_00,GAPPY_SUBJECT,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 19 May 2016 16:22:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A8C082F; Thu, 19 May 2016 09:22:54 -0700 (PDT) Received: from [10.2.206.43] (e100706-lin.cambridge.arm.com [10.2.206.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5882B3F21A; Thu, 19 May 2016 09:22:35 -0700 (PDT) Message-ID: <573DE84A.1070503@foss.arm.com> Date: Thu, 19 May 2016 16:22:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Christophe Lyon , gcc-patches@gcc.gnu.org Subject: Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests. References: <1462973041-7911-1-git-send-email-christophe.lyon@linaro.org> <1462973041-7911-10-git-send-email-christophe.lyon@linaro.org> In-Reply-To: <1462973041-7911-10-git-send-email-christophe.lyon@linaro.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2016-05/txt/msg01526.txt.bz2 Hi Christophe, On 11/05/16 14:23, Christophe Lyon wrote: > 2016-05-02 Christophe Lyon > > * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New. > * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: New. > * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: New. > * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: New. > * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: New. > * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: New. > * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: New. Drop the gcc/testsuite from the ChangeLog entry. Just "* gcc.target/aarch64/..." Ok with the fixed ChangeLog. Thanks, Kyrill > Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737 > > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c > new file mode 100644 > index 0000000..5f492d4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c > @@ -0,0 +1,16 @@ > +/* { dg-require-effective-target arm_v8_neon_ok } */ > +/* { dg-add-options arm_v8_neon } */ > + > +#include > +#include "arm-neon-ref.h" > +#include "compute-ref-data.h" > + > +/* Expected results. */ > +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; > +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, > + 0xc1600000, 0xc1500000 }; > + > +#define INSN vrnd > +#define TEST_MSG "VRND" > + > +#include "vrndX.inc" > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc > new file mode 100644 > index 0000000..629240d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc > @@ -0,0 +1,43 @@ > +#define FNNAME1(NAME) exec_ ## NAME > +#define FNNAME(NAME) FNNAME1 (NAME) > + > +void FNNAME (INSN) (void) > +{ > + /* vector_res = vrndX (vector), then store the result. */ > +#define TEST_VRND2(INSN, Q, T1, T2, W, N) \ > + VECT_VAR (vector_res, T1, W, N) = \ > + INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N)); \ > + vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N), \ > + VECT_VAR (vector_res, T1, W, N)) > + > + /* Two auxliary macros are necessary to expand INSN. */ > +#define TEST_VRND1(INSN, Q, T1, T2, W, N) \ > + TEST_VRND2 (INSN, Q, T1, T2, W, N) > + > +#define TEST_VRND(Q, T1, T2, W, N) \ > + TEST_VRND1 (INSN, Q, T1, T2, W, N) > + > + DECL_VARIABLE (vector, float, 32, 2); > + DECL_VARIABLE (vector, float, 32, 4); > + > + DECL_VARIABLE (vector_res, float, 32, 2); > + DECL_VARIABLE (vector_res, float, 32, 4); > + > + clean_results (); > + > + VLOAD (vector, buffer, , float, f, 32, 2); > + VLOAD (vector, buffer, q, float, f, 32, 4); > + > + TEST_VRND ( , float, f, 32, 2); > + TEST_VRND (q, float, f, 32, 4); > + > + CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, ""); > + CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, ""); > +} > + > +int > +main (void) > +{ > + FNNAME (INSN) (); > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c > new file mode 100644 > index 0000000..816fd28d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c > @@ -0,0 +1,16 @@ > +/* { dg-require-effective-target arm_v8_neon_ok } */ > +/* { dg-add-options arm_v8_neon } */ > + > +#include > +#include "arm-neon-ref.h" > +#include "compute-ref-data.h" > + > +/* Expected results. */ > +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; > +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, > + 0xc1600000, 0xc1500000 }; > + > +#define INSN vrnda > +#define TEST_MSG "VRNDA" > + > +#include "vrndX.inc" > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c > new file mode 100644 > index 0000000..029880c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c > @@ -0,0 +1,16 @@ > +/* { dg-require-effective-target arm_v8_neon_ok } */ > +/* { dg-add-options arm_v8_neon } */ > + > +#include > +#include "arm-neon-ref.h" > +#include "compute-ref-data.h" > + > +/* Expected results. */ > +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; > +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, > + 0xc1600000, 0xc1500000 }; > + > +#define INSN vrndm > +#define TEST_MSG "VRNDM" > + > +#include "vrndX.inc" > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c > new file mode 100644 > index 0000000..571243c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c > @@ -0,0 +1,16 @@ > +/* { dg-require-effective-target arm_v8_neon_ok } */ > +/* { dg-add-options arm_v8_neon } */ > + > +#include > +#include "arm-neon-ref.h" > +#include "compute-ref-data.h" > + > +/* Expected results. */ > +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; > +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, > + 0xc1600000, 0xc1500000 }; > + > +#define INSN vrndn > +#define TEST_MSG "VRNDN" > + > +#include "vrndX.inc" > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c > new file mode 100644 > index 0000000..ff4771c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c > @@ -0,0 +1,16 @@ > +/* { dg-require-effective-target arm_v8_neon_ok } */ > +/* { dg-add-options arm_v8_neon } */ > + > +#include > +#include "arm-neon-ref.h" > +#include "compute-ref-data.h" > + > +/* Expected results. */ > +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; > +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, > + 0xc1600000, 0xc1500000 }; > + > +#define INSN vrndp > +#define TEST_MSG "VRNDP" > + > +#include "vrndX.inc" > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c > new file mode 100644 > index 0000000..ff2357b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c > @@ -0,0 +1,16 @@ > +/* { dg-require-effective-target arm_v8_neon_ok } */ > +/* { dg-add-options arm_v8_neon } */ > + > +#include > +#include "arm-neon-ref.h" > +#include "compute-ref-data.h" > + > +/* Expected results. */ > +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; > +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, > + 0xc1600000, 0xc1500000 }; > + > +#define INSN vrndx > +#define TEST_MSG "VRNDX" > + > +#include "vrndX.inc"