From: Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>
To: Christophe Lyon <christophe.lyon@linaro.org>, gcc-patches@gcc.gnu.org
Subject: Re: [Patch ARM/AArch64 11/11] Add missing tests for vreinterpret, operating of fp16 type.
Date: Thu, 19 May 2016 16:24:00 -0000 [thread overview]
Message-ID: <573DE8CD.5070902@foss.arm.com> (raw)
In-Reply-To: <1462973041-7911-12-git-send-email-christophe.lyon@linaro.org>
On 11/05/16 14:24, Christophe Lyon wrote:
> 2016-05-04 Christophe Lyon <christophe.lyon@linaro.org>
>
> * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add fp16 tests.
> * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: Likewise.
Ok.
Thanks for working on these!
Kyrill
> Change-Id: Ic8061f1a5f3e042844a33a70c0f42a5f92c43c98
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> index 2570f73..0de2ab3 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> @@ -21,6 +21,8 @@ VECT_VAR_DECL(expected_s8_8,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> 0xf4, 0xf5, 0xf6, 0xf7 };
> VECT_VAR_DECL(expected_s8_9,int,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
> 0xf2, 0xff, 0xf3, 0xff };
> +VECT_VAR_DECL(expected_s8_10,int,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
> + 0x00, 0xcb, 0x80, 0xca };
>
> /* Expected results for vreinterpret_s16_xx. */
> VECT_VAR_DECL(expected_s16_1,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> @@ -32,6 +34,7 @@ VECT_VAR_DECL(expected_s16_6,int,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
> VECT_VAR_DECL(expected_s16_7,int,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
> VECT_VAR_DECL(expected_s16_8,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> VECT_VAR_DECL(expected_s16_9,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_s16_10,int,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
>
> /* Expected results for vreinterpret_s32_xx. */
> VECT_VAR_DECL(expected_s32_1,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
> @@ -43,6 +46,7 @@ VECT_VAR_DECL(expected_s32_6,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> VECT_VAR_DECL(expected_s32_7,int,32,2) [] = { 0xfffffff0, 0xffffffff };
> VECT_VAR_DECL(expected_s32_8,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
> VECT_VAR_DECL(expected_s32_9,int,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
> +VECT_VAR_DECL(expected_s32_10,int,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
>
> /* Expected results for vreinterpret_s64_xx. */
> VECT_VAR_DECL(expected_s64_1,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
> @@ -54,6 +58,7 @@ VECT_VAR_DECL(expected_s64_6,int,64,1) [] = { 0xfffffff1fffffff0 };
> VECT_VAR_DECL(expected_s64_7,int,64,1) [] = { 0xfffffffffffffff0 };
> VECT_VAR_DECL(expected_s64_8,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
> VECT_VAR_DECL(expected_s64_9,int,64,1) [] = { 0xfff3fff2fff1fff0 };
> +VECT_VAR_DECL(expected_s64_10,int,64,1) [] = { 0xca80cb00cb80cc00 };
>
> /* Expected results for vreinterpret_u8_xx. */
> VECT_VAR_DECL(expected_u8_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> @@ -74,6 +79,8 @@ VECT_VAR_DECL(expected_u8_8,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> 0xf4, 0xf5, 0xf6, 0xf7 };
> VECT_VAR_DECL(expected_u8_9,uint,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
> 0xf2, 0xff, 0xf3, 0xff };
> +VECT_VAR_DECL(expected_u8_10,uint,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
> + 0x00, 0xcb, 0x80, 0xca };
>
> /* Expected results for vreinterpret_u16_xx. */
> VECT_VAR_DECL(expected_u16_1,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> @@ -85,6 +92,7 @@ VECT_VAR_DECL(expected_u16_6,uint,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
> VECT_VAR_DECL(expected_u16_7,uint,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
> VECT_VAR_DECL(expected_u16_8,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> VECT_VAR_DECL(expected_u16_9,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_u16_10,uint,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
>
> /* Expected results for vreinterpret_u32_xx. */
> VECT_VAR_DECL(expected_u32_1,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
> @@ -96,6 +104,7 @@ VECT_VAR_DECL(expected_u32_6,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
> VECT_VAR_DECL(expected_u32_7,uint,32,2) [] = { 0xfffffff0, 0xffffffff };
> VECT_VAR_DECL(expected_u32_8,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
> VECT_VAR_DECL(expected_u32_9,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
> +VECT_VAR_DECL(expected_u32_10,uint,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
>
> /* Expected results for vreinterpret_u64_xx. */
> VECT_VAR_DECL(expected_u64_1,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
> @@ -107,6 +116,7 @@ VECT_VAR_DECL(expected_u64_6,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
> VECT_VAR_DECL(expected_u64_7,uint,64,1) [] = { 0xfffffff1fffffff0 };
> VECT_VAR_DECL(expected_u64_8,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
> VECT_VAR_DECL(expected_u64_9,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
> +VECT_VAR_DECL(expected_u64_10,uint,64,1) [] = { 0xca80cb00cb80cc00 };
>
> /* Expected results for vreinterpret_p8_xx. */
> VECT_VAR_DECL(expected_p8_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> @@ -127,6 +137,8 @@ VECT_VAR_DECL(expected_p8_8,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
> 0xff, 0xff, 0xff, 0xff };
> VECT_VAR_DECL(expected_p8_9,poly,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
> 0xf2, 0xff, 0xf3, 0xff };
> +VECT_VAR_DECL(expected_p8_10,poly,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
> + 0x00, 0xcb, 0x80, 0xca };
>
> /* Expected results for vreinterpret_p16_xx. */
> VECT_VAR_DECL(expected_p16_1,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> @@ -138,6 +150,7 @@ VECT_VAR_DECL(expected_p16_6,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> VECT_VAR_DECL(expected_p16_7,poly,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
> VECT_VAR_DECL(expected_p16_8,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
> VECT_VAR_DECL(expected_p16_9,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> +VECT_VAR_DECL(expected_p16_10,poly,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
>
> /* Expected results for vreinterpretq_s8_xx. */
> VECT_VAR_DECL(expected_q_s8_1,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
> @@ -176,6 +189,10 @@ VECT_VAR_DECL(expected_q_s8_9,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
> 0xf2, 0xff, 0xf3, 0xff,
> 0xf4, 0xff, 0xf5, 0xff,
> 0xf6, 0xff, 0xf7, 0xff };
> +VECT_VAR_DECL(expected_q_s8_10,int,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
> + 0x00, 0xcb, 0x80, 0xca,
> + 0x00, 0xca, 0x80, 0xc9,
> + 0x00, 0xc9, 0x80, 0xc8 };
>
> /* Expected results for vreinterpretq_s16_xx. */
> VECT_VAR_DECL(expected_q_s16_1,int,16,8) [] = { 0xf1f0, 0xf3f2,
> @@ -214,6 +231,10 @@ VECT_VAR_DECL(expected_q_s16_9,int,16,8) [] = { 0xfff0, 0xfff1,
> 0xfff2, 0xfff3,
> 0xfff4, 0xfff5,
> 0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected_q_s16_10,int,16,8) [] = { 0xcc00, 0xcb80,
> + 0xcb00, 0xca80,
> + 0xca00, 0xc980,
> + 0xc900, 0xc880 };
>
> /* Expected results for vreinterpretq_s32_xx. */
> VECT_VAR_DECL(expected_q_s32_1,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
> @@ -234,6 +255,8 @@ VECT_VAR_DECL(expected_q_s32_8,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
> 0xfbfaf9f8, 0xfffefdfc };
> VECT_VAR_DECL(expected_q_s32_9,int,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
> 0xfff5fff4, 0xfff7fff6 };
> +VECT_VAR_DECL(expected_q_s32_10,int,32,4) [] = { 0xcb80cc00, 0xca80cb00,
> + 0xc980ca00, 0xc880c900 };
>
> /* Expected results for vreinterpretq_s64_xx. */
> VECT_VAR_DECL(expected_q_s64_1,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
> @@ -254,6 +277,8 @@ VECT_VAR_DECL(expected_q_s64_8,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
> 0xfffefdfcfbfaf9f8 };
> VECT_VAR_DECL(expected_q_s64_9,int,64,2) [] = { 0xfff3fff2fff1fff0,
> 0xfff7fff6fff5fff4 };
> +VECT_VAR_DECL(expected_q_s64_10,int,64,2) [] = { 0xca80cb00cb80cc00,
> + 0xc880c900c980ca00 };
>
> /* Expected results for vreinterpretq_u8_xx. */
> VECT_VAR_DECL(expected_q_u8_1,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> @@ -292,6 +317,10 @@ VECT_VAR_DECL(expected_q_u8_9,uint,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
> 0xf2, 0xff, 0xf3, 0xff,
> 0xf4, 0xff, 0xf5, 0xff,
> 0xf6, 0xff, 0xf7, 0xff };
> +VECT_VAR_DECL(expected_q_u8_10,uint,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
> + 0x00, 0xcb, 0x80, 0xca,
> + 0x00, 0xca, 0x80, 0xc9,
> + 0x00, 0xc9, 0x80, 0xc8 };
>
> /* Expected results for vreinterpretq_u16_xx. */
> VECT_VAR_DECL(expected_q_u16_1,uint,16,8) [] = { 0xf1f0, 0xf3f2,
> @@ -330,6 +359,10 @@ VECT_VAR_DECL(expected_q_u16_9,uint,16,8) [] = { 0xfff0, 0xfff1,
> 0xfff2, 0xfff3,
> 0xfff4, 0xfff5,
> 0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected_q_u16_10,uint,16,8) [] = { 0xcc00, 0xcb80,
> + 0xcb00, 0xca80,
> + 0xca00, 0xc980,
> + 0xc900, 0xc880 };
>
> /* Expected results for vreinterpretq_u32_xx. */
> VECT_VAR_DECL(expected_q_u32_1,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
> @@ -350,6 +383,8 @@ VECT_VAR_DECL(expected_q_u32_8,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
> 0xfbfaf9f8, 0xfffefdfc };
> VECT_VAR_DECL(expected_q_u32_9,uint,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
> 0xfff5fff4, 0xfff7fff6 };
> +VECT_VAR_DECL(expected_q_u32_10,uint,32,4) [] = { 0xcb80cc00, 0xca80cb00,
> + 0xc980ca00, 0xc880c900 };
>
> /* Expected results for vreinterpretq_u64_xx. */
> VECT_VAR_DECL(expected_q_u64_1,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
> @@ -370,7 +405,8 @@ VECT_VAR_DECL(expected_q_u64_8,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
> 0xfffefdfcfbfaf9f8 };
> VECT_VAR_DECL(expected_q_u64_9,uint,64,2) [] = { 0xfff3fff2fff1fff0,
> 0xfff7fff6fff5fff4 };
> -
> +VECT_VAR_DECL(expected_q_u64_10,uint,64,2) [] = { 0xca80cb00cb80cc00,
> + 0xc880c900c980ca00 };
>
> /* Expected results for vreinterpretq_p8_xx. */
> VECT_VAR_DECL(expected_q_p8_1,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> @@ -409,6 +445,10 @@ VECT_VAR_DECL(expected_q_p8_9,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
> 0xf2, 0xff, 0xf3, 0xff,
> 0xf4, 0xff, 0xf5, 0xff,
> 0xf6, 0xff, 0xf7, 0xff };
> +VECT_VAR_DECL(expected_q_p8_10,poly,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
> + 0x00, 0xcb, 0x80, 0xca,
> + 0x00, 0xca, 0x80, 0xc9,
> + 0x00, 0xc9, 0x80, 0xc8 };
>
> /* Expected results for vreinterpretq_p16_xx. */
> VECT_VAR_DECL(expected_q_p16_1,poly,16,8) [] = { 0xf1f0, 0xf3f2,
> @@ -447,6 +487,10 @@ VECT_VAR_DECL(expected_q_p16_9,poly,16,8) [] = { 0xf1f0, 0xf3f2,
> 0xf5f4, 0xf7f6,
> 0xf9f8, 0xfbfa,
> 0xfdfc, 0xfffe };
> +VECT_VAR_DECL(expected_q_p16_10,poly,16,8) [] = { 0xcc00, 0xcb80,
> + 0xcb00, 0xca80,
> + 0xca00, 0xc980,
> + 0xc900, 0xc880 };
>
> /* Expected results for vreinterpret_f32_xx. */
> VECT_VAR_DECL(expected_f32_1,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
> @@ -459,6 +503,7 @@ VECT_VAR_DECL(expected_f32_7,hfloat,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> VECT_VAR_DECL(expected_f32_8,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
> VECT_VAR_DECL(expected_f32_9,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
> VECT_VAR_DECL(expected_f32_10,hfloat,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
> +VECT_VAR_DECL(expected_f32_11,hfloat,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
>
> /* Expected results for vreinterpretq_f32_xx. */
> VECT_VAR_DECL(expected_q_f32_1,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
> @@ -481,6 +526,8 @@ VECT_VAR_DECL(expected_q_f32_9,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
> 0xfbfaf9f8, 0xfffefdfc };
> VECT_VAR_DECL(expected_q_f32_10,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
> 0xfff5fff4, 0xfff7fff6 };
> +VECT_VAR_DECL(expected_q_f32_11,hfloat,32,4) [] = { 0xcb80cc00, 0xca80cb00,
> + 0xc980ca00, 0xc880c900 };
>
> /* Expected results for vreinterpret_xx_f32. */
> VECT_VAR_DECL(expected_xx_f32_1,int,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
> @@ -496,6 +543,7 @@ VECT_VAR_DECL(expected_xx_f32_8,uint,64,1) [] = { 0xc1700000c1800000 };
> VECT_VAR_DECL(expected_xx_f32_9,poly,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
> 0x0, 0x0, 0x70, 0xc1 };
> VECT_VAR_DECL(expected_xx_f32_10,poly,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
> +VECT_VAR_DECL(expected_xx_f32_11,hfloat,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
>
> /* Expected results for vreinterpretq_xx_f32. */
> VECT_VAR_DECL(expected_q_xx_f32_1,int,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
> @@ -524,6 +572,62 @@ VECT_VAR_DECL(expected_q_xx_f32_9,poly,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
> 0x0, 0x0, 0x50, 0xc1 };
> VECT_VAR_DECL(expected_q_xx_f32_10,poly,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
> 0x0, 0xc160, 0x0, 0xc150 };
> +VECT_VAR_DECL(expected_q_xx_f32_11,hfloat,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
> + 0x0, 0xc160, 0x0, 0xc150 };
> +
> +/* Expected results for vreinterpret_f16_xx. */
> +VECT_VAR_DECL(expected_f16_1,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> +VECT_VAR_DECL(expected_f16_2,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_f16_3,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
> +VECT_VAR_DECL(expected_f16_4,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
> +VECT_VAR_DECL(expected_f16_5,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> +VECT_VAR_DECL(expected_f16_6,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_f16_7,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
> +VECT_VAR_DECL(expected_f16_8,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
> +VECT_VAR_DECL(expected_f16_9,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
> +VECT_VAR_DECL(expected_f16_10,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +
> +/* Expected results for vreinterpretq_f16_xx. */
> +VECT_VAR_DECL(expected_q_f16_1,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
> + 0xf5f4, 0xf7f6,
> + 0xf9f8, 0xfbfa,
> + 0xfdfc, 0xfffe };
> +VECT_VAR_DECL(expected_q_f16_2,hfloat,16,8) [] = { 0xfff0, 0xfff1,
> + 0xfff2, 0xfff3,
> + 0xfff4, 0xfff5,
> + 0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected_q_f16_3,hfloat,16,8) [] = { 0xfff0, 0xffff,
> + 0xfff1, 0xffff,
> + 0xfff2, 0xffff,
> + 0xfff3, 0xffff };
> +VECT_VAR_DECL(expected_q_f16_4,hfloat,16,8) [] = { 0xfff0, 0xffff,
> + 0xffff, 0xffff,
> + 0xfff1, 0xffff,
> + 0xffff, 0xffff };
> +VECT_VAR_DECL(expected_q_f16_5,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
> + 0xf5f4, 0xf7f6,
> + 0xf9f8, 0xfbfa,
> + 0xfdfc, 0xfffe };
> +VECT_VAR_DECL(expected_q_f16_6,hfloat,16,8) [] = { 0xfff0, 0xfff1,
> + 0xfff2, 0xfff3,
> + 0xfff4, 0xfff5,
> + 0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected_q_f16_7,hfloat,16,8) [] = { 0xfff0, 0xffff,
> + 0xfff1, 0xffff,
> + 0xfff2, 0xffff,
> + 0xfff3, 0xffff };
> +VECT_VAR_DECL(expected_q_f16_8,hfloat,16,8) [] = { 0xfff0, 0xffff,
> + 0xffff, 0xffff,
> + 0xfff1, 0xffff,
> + 0xffff, 0xffff };
> +VECT_VAR_DECL(expected_q_f16_9,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
> + 0xf5f4, 0xf7f6,
> + 0xf9f8, 0xfbfa,
> + 0xfdfc, 0xfffe };
> +VECT_VAR_DECL(expected_q_f16_10,hfloat,16,8) [] = { 0xfff0, 0xfff1,
> + 0xfff2, 0xfff3,
> + 0xfff4, 0xfff5,
> + 0xfff6, 0xfff7 };
>
> #define TEST_MSG "VREINTERPRET/VREINTERPRETQ"
>
> @@ -561,7 +665,9 @@ void exec_vreinterpret (void)
>
> /* Initialize input "vector" from "buffer". */
> TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
> + VLOAD(vector, buffer, , float, f, 16, 4);
> VLOAD(vector, buffer, , float, f, 32, 2);
> + VLOAD(vector, buffer, q, float, f, 16, 8);
> VLOAD(vector, buffer, q, float, f, 32, 4);
>
> /* vreinterpret_s8_xx. */
> @@ -574,6 +680,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(, int, s, 8, 8, uint, u, 64, 1, expected_s8_7);
> TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 8, 8, expected_s8_8);
> TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 16, 4, expected_s8_9);
> + TEST_VREINTERPRET(, int, s, 8, 8, float, f, 16, 4, expected_s8_10);
>
> /* vreinterpret_s16_xx. */
> TEST_VREINTERPRET(, int, s, 16, 4, int, s, 8, 8, expected_s16_1);
> @@ -585,6 +692,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(, int, s, 16, 4, uint, u, 64, 1, expected_s16_7);
> TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 8, 8, expected_s16_8);
> TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 16, 4, expected_s16_9);
> + TEST_VREINTERPRET(, int, s, 16, 4, float, f, 16, 4, expected_s16_10);
>
> /* vreinterpret_s32_xx. */
> TEST_VREINTERPRET(, int, s, 32, 2, int, s, 8, 8, expected_s32_1);
> @@ -596,6 +704,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(, int, s, 32, 2, uint, u, 64, 1, expected_s32_7);
> TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 8, 8, expected_s32_8);
> TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 16, 4, expected_s32_9);
> + TEST_VREINTERPRET(, int, s, 32, 2, float, f, 16, 4, expected_s32_10);
>
> /* vreinterpret_s64_xx. */
> TEST_VREINTERPRET(, int, s, 64, 1, int, s, 8, 8, expected_s64_1);
> @@ -607,6 +716,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(, int, s, 64, 1, uint, u, 64, 1, expected_s64_7);
> TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 8, 8, expected_s64_8);
> TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 16, 4, expected_s64_9);
> + TEST_VREINTERPRET(, int, s, 64, 1, float, f, 16, 4, expected_s64_10);
>
> /* vreinterpret_u8_xx. */
> TEST_VREINTERPRET(, uint, u, 8, 8, int, s, 8, 8, expected_u8_1);
> @@ -618,6 +728,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(, uint, u, 8, 8, uint, u, 64, 1, expected_u8_7);
> TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 8, 8, expected_u8_8);
> TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 16, 4, expected_u8_9);
> + TEST_VREINTERPRET(, uint, u, 8, 8, float, f, 16, 4, expected_u8_10);
>
> /* vreinterpret_u16_xx. */
> TEST_VREINTERPRET(, uint, u, 16, 4, int, s, 8, 8, expected_u16_1);
> @@ -629,6 +740,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(, uint, u, 16, 4, uint, u, 64, 1, expected_u16_7);
> TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 8, 8, expected_u16_8);
> TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 16, 4, expected_u16_9);
> + TEST_VREINTERPRET(, uint, u, 16, 4, float, f, 16, 4, expected_u16_10);
>
> /* vreinterpret_u32_xx. */
> TEST_VREINTERPRET(, uint, u, 32, 2, int, s, 8, 8, expected_u32_1);
> @@ -640,6 +752,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(, uint, u, 32, 2, uint, u, 64, 1, expected_u32_7);
> TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 8, 8, expected_u32_8);
> TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 16, 4, expected_u32_9);
> + TEST_VREINTERPRET(, uint, u, 32, 2, float, f, 16, 4, expected_u32_10);
>
> /* vreinterpret_u64_xx. */
> TEST_VREINTERPRET(, uint, u, 64, 1, int, s, 8, 8, expected_u64_1);
> @@ -651,6 +764,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(, uint, u, 64, 1, uint, u, 32, 2, expected_u64_7);
> TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 8, 8, expected_u64_8);
> TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 16, 4, expected_u64_9);
> + TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 16, 4, expected_u64_10);
>
> /* vreinterpret_p8_xx. */
> TEST_VREINTERPRET_POLY(, poly, p, 8, 8, int, s, 8, 8, expected_p8_1);
> @@ -662,6 +776,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 32, 2, expected_p8_7);
> TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 64, 1, expected_p8_8);
> TEST_VREINTERPRET_POLY(, poly, p, 8, 8, poly, p, 16, 4, expected_p8_9);
> + TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 16, 4, expected_p8_10);
>
> /* vreinterpret_p16_xx. */
> TEST_VREINTERPRET_POLY(, poly, p, 16, 4, int, s, 8, 8, expected_p16_1);
> @@ -673,6 +788,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 32, 2, expected_p16_7);
> TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 64, 1, expected_p16_8);
> TEST_VREINTERPRET_POLY(, poly, p, 16, 4, poly, p, 8, 8, expected_p16_9);
> + TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 16, 4, expected_p16_10);
>
> /* vreinterpretq_s8_xx. */
> TEST_VREINTERPRET(q, int, s, 8, 16, int, s, 16, 8, expected_q_s8_1);
> @@ -684,6 +800,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(q, int, s, 8, 16, uint, u, 64, 2, expected_q_s8_7);
> TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 8, 16, expected_q_s8_8);
> TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 16, 8, expected_q_s8_9);
> + TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 16, 8, expected_q_s8_10);
>
> /* vreinterpretq_s16_xx. */
> TEST_VREINTERPRET(q, int, s, 16, 8, int, s, 8, 16, expected_q_s16_1);
> @@ -695,6 +812,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(q, int, s, 16, 8, uint, u, 64, 2, expected_q_s16_7);
> TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 8, 16, expected_q_s16_8);
> TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 16, 8, expected_q_s16_9);
> + TEST_VREINTERPRET(q, int, s, 16, 8, float, f, 16, 8, expected_q_s16_10);
>
> /* vreinterpretq_s32_xx. */
> TEST_VREINTERPRET(q, int, s, 32, 4, int, s, 8, 16, expected_q_s32_1);
> @@ -706,6 +824,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(q, int, s, 32, 4, uint, u, 64, 2, expected_q_s32_7);
> TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 8, 16, expected_q_s32_8);
> TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 16, 8, expected_q_s32_9);
> + TEST_VREINTERPRET(q, int, s, 32, 4, float, f, 16, 8, expected_q_s32_10);
>
> /* vreinterpretq_s64_xx. */
> TEST_VREINTERPRET(q, int, s, 64, 2, int, s, 8, 16, expected_q_s64_1);
> @@ -717,6 +836,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(q, int, s, 64, 2, uint, u, 64, 2, expected_q_s64_7);
> TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 8, 16, expected_q_s64_8);
> TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 16, 8, expected_q_s64_9);
> + TEST_VREINTERPRET(q, int, s, 64, 2, float, f, 16, 8, expected_q_s64_10);
>
> /* vreinterpretq_u8_xx. */
> TEST_VREINTERPRET(q, uint, u, 8, 16, int, s, 8, 16, expected_q_u8_1);
> @@ -728,6 +848,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(q, uint, u, 8, 16, uint, u, 64, 2, expected_q_u8_7);
> TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 8, 16, expected_q_u8_8);
> TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 16, 8, expected_q_u8_9);
> + TEST_VREINTERPRET(q, uint, u, 8, 16, float, f, 16, 8, expected_q_u8_10);
>
> /* vreinterpretq_u16_xx. */
> TEST_VREINTERPRET(q, uint, u, 16, 8, int, s, 8, 16, expected_q_u16_1);
> @@ -739,6 +860,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(q, uint, u, 16, 8, uint, u, 64, 2, expected_q_u16_7);
> TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 8, 16, expected_q_u16_8);
> TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 16, 8, expected_q_u16_9);
> + TEST_VREINTERPRET(q, uint, u, 16, 8, float, f, 16, 8, expected_q_u16_10);
>
> /* vreinterpretq_u32_xx. */
> TEST_VREINTERPRET(q, uint, u, 32, 4, int, s, 8, 16, expected_q_u32_1);
> @@ -750,6 +872,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(q, uint, u, 32, 4, uint, u, 64, 2, expected_q_u32_7);
> TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 8, 16, expected_q_u32_8);
> TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 16, 8, expected_q_u32_9);
> + TEST_VREINTERPRET(q, uint, u, 32, 4, float, f, 16, 8, expected_q_u32_10);
>
> /* vreinterpretq_u64_xx. */
> TEST_VREINTERPRET(q, uint, u, 64, 2, int, s, 8, 16, expected_q_u64_1);
> @@ -761,6 +884,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(q, uint, u, 64, 2, uint, u, 32, 4, expected_q_u64_7);
> TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 8, 16, expected_q_u64_8);
> TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 16, 8, expected_q_u64_9);
> + TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 16, 8, expected_q_u64_10);
>
> /* vreinterpretq_p8_xx. */
> TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 8, 16, expected_q_p8_1);
> @@ -772,6 +896,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 32, 4, expected_q_p8_7);
> TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 64, 2, expected_q_p8_8);
> TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, poly, p, 16, 8, expected_q_p8_9);
> + TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 16, 8, expected_q_p8_10);
>
> /* vreinterpretq_p16_xx. */
> TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 8, 16, expected_q_p16_1);
> @@ -783,6 +908,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 32, 4, expected_q_p16_7);
> TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 64, 2, expected_q_p16_8);
> TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, poly, p, 8, 16, expected_q_p16_9);
> + TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 16, 8, expected_q_p16_10);
>
> /* vreinterpret_f32_xx. */
> TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 8, 8, expected_f32_1);
> @@ -795,6 +921,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET_FP(, float, f, 32, 2, uint, u, 64, 1, expected_f32_8);
> TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 8, 8, expected_f32_9);
> TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 16, 4, expected_f32_10);
> + TEST_VREINTERPRET_FP(, float, f, 32, 2, float, f, 16, 4, expected_f32_11);
>
> /* vreinterpretq_f32_xx. */
> TEST_VREINTERPRET_FP(q, float, f, 32, 4, int, s, 8, 16, expected_q_f32_1);
> @@ -807,6 +934,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET_FP(q, float, f, 32, 4, uint, u, 64, 2, expected_q_f32_8);
> TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 8, 16, expected_q_f32_9);
> TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 16, 8, expected_q_f32_10);
> + TEST_VREINTERPRET_FP(q, float, f, 32, 4, float, f, 16, 8, expected_q_f32_11);
>
> /* vreinterpret_xx_f32. */
> TEST_VREINTERPRET(, int, s, 8, 8, float, f, 32, 2, expected_xx_f32_1);
> @@ -819,6 +947,7 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 32, 2, expected_xx_f32_8);
> TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 32, 2, expected_xx_f32_9);
> TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 32, 2, expected_xx_f32_10);
> + TEST_VREINTERPRET_FP(, float, f, 16, 4, float, f, 32, 2, expected_xx_f32_11);
>
> /* vreinterpretq_xx_f32. */
> TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 32, 4, expected_q_xx_f32_1);
> @@ -831,6 +960,31 @@ void exec_vreinterpret (void)
> TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 32, 4, expected_q_xx_f32_8);
> TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 32, 4, expected_q_xx_f32_9);
> TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 32, 4, expected_q_xx_f32_10);
> + TEST_VREINTERPRET_FP(q, float, f, 16, 8, float, f, 32, 4, expected_q_xx_f32_11);
> +
> + /* vreinterpret_f16_xx. */
> + TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 8, 8, expected_f16_1);
> + TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 16, 4, expected_f16_2);
> + TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 32, 2, expected_f16_3);
> + TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 64, 1, expected_f16_4);
> + TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 8, 8, expected_f16_5);
> + TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 16, 4, expected_f16_6);
> + TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 32, 2, expected_f16_7);
> + TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 64, 1, expected_f16_8);
> + TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 8, 8, expected_f16_9);
> + TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 16, 4, expected_f16_10);
> +
> + /* vreinterpretq_f16_xx. */
> + TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 8, 16, expected_q_f16_1);
> + TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 16, 8, expected_q_f16_2);
> + TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 32, 4, expected_q_f16_3);
> + TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 64, 2, expected_q_f16_4);
> + TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 8, 16, expected_q_f16_5);
> + TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 16, 8, expected_q_f16_6);
> + TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 32, 4, expected_q_f16_7);
> + TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 64, 2, expected_q_f16_8);
> + TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 8, 16, expected_q_f16_9);
> + TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 16, 8, expected_q_f16_10);
> }
>
> int main (void)
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
> index a049cb3..8ba5272 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
> @@ -30,6 +30,8 @@ VECT_VAR_DECL(vreint_expected_q_p128_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
> 0xfff7fff6fff5fff4 };
> VECT_VAR_DECL(vreint_expected_q_p128_f32,poly,64,2) [] = { 0xc1700000c1800000,
> 0xc1500000c1600000 };
> +VECT_VAR_DECL(vreint_expected_q_p128_f16,poly,64,2) [] = { 0xca80cb00cb80cc00,
> + 0xc880c900c980ca00 };
>
> /* Expected results: vreinterpretq_*_p128. */
> VECT_VAR_DECL(vreint_expected_q_s8_p128,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
> @@ -68,6 +70,10 @@ VECT_VAR_DECL(vreint_expected_q_p64_p128,uint,64,2) [] = { 0xfffffffffffffff0,
> 0xfffffffffffffff1 };
> VECT_VAR_DECL(vreint_expected_q_f32_p128,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
> 0xfffffff1, 0xffffffff };
> +VECT_VAR_DECL(vreint_expected_q_f16_p128,hfloat,16,8) [] = { 0xfff0, 0xffff,
> + 0xffff, 0xffff,
> + 0xfff1, 0xffff,
> + 0xffff, 0xffff };
>
> int main (void)
> {
> @@ -80,6 +86,7 @@ int main (void)
>
> TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vreint_vector, buffer);
> VLOAD(vreint_vector, buffer, q, poly, p, 64, 2);
> + VLOAD(vreint_vector, buffer, q, float, f, 16, 8);
> VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
>
> /* vreinterpretq_p128_* tests. */
> @@ -108,6 +115,7 @@ int main (void)
> TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 64, 2, vreint_expected_q_p128_u64);
> TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 8, 16, vreint_expected_q_p128_p8);
> TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 16, 8, vreint_expected_q_p128_p16);
> + TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 16, 8, vreint_expected_q_p128_f16);
> TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 32, 4, vreint_expected_q_p128_f32);
>
> /* vreinterpretq_*_p128 tests. */
> @@ -145,6 +153,7 @@ int main (void)
> TEST_VREINTERPRET_FROM_P128(q, uint, u, 64, 2, poly, p, 128, 1, vreint_expected_q_u64_p128);
> TEST_VREINTERPRET_FROM_P128(q, poly, p, 8, 16, poly, p, 128, 1, vreint_expected_q_p8_p128);
> TEST_VREINTERPRET_FROM_P128(q, poly, p, 16, 8, poly, p, 128, 1, vreint_expected_q_p16_p128);
> + TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 16, 8, poly, p, 128, 1, vreint_expected_q_f16_p128);
> TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 32, 4, poly, p, 128, 1, vreint_expected_q_f32_p128);
>
> return 0;
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
> index 79f3cd6..b000797 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
> @@ -19,6 +19,7 @@ VECT_VAR_DECL(vreint_expected_p64_u64,poly,64,1) [] = { 0xfffffffffffffff0 };
> VECT_VAR_DECL(vreint_expected_p64_p8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
> VECT_VAR_DECL(vreint_expected_p64_p16,poly,64,1) [] = { 0xfff3fff2fff1fff0 };
> VECT_VAR_DECL(vreint_expected_p64_f32,poly,64,1) [] = { 0xc1700000c1800000 };
> +VECT_VAR_DECL(vreint_expected_p64_f16,poly,64,1) [] = { 0xca80cb00cb80cc00 };
>
> /* Expected results: vreinterpretq_p64_*. */
> VECT_VAR_DECL(vreint_expected_q_p64_s8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
> @@ -43,6 +44,8 @@ VECT_VAR_DECL(vreint_expected_q_p64_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
> 0xfff7fff6fff5fff4 };
> VECT_VAR_DECL(vreint_expected_q_p64_f32,poly,64,2) [] = { 0xc1700000c1800000,
> 0xc1500000c1600000 };
> +VECT_VAR_DECL(vreint_expected_q_p64_f16,poly,64,2) [] = { 0xca80cb00cb80cc00,
> + 0xc880c900c980ca00 };
>
> /* Expected results: vreinterpret_*_p64. */
> VECT_VAR_DECL(vreint_expected_s8_p64,int,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
> @@ -59,6 +62,7 @@ VECT_VAR_DECL(vreint_expected_p8_p64,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
> 0xff, 0xff, 0xff, 0xff };
> VECT_VAR_DECL(vreint_expected_p16_p64,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
> VECT_VAR_DECL(vreint_expected_f32_p64,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
> +VECT_VAR_DECL(vreint_expected_f16_p64,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
>
> /* Expected results: vreinterpretq_*_p64. */
> VECT_VAR_DECL(vreint_expected_q_s8_p64,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
> @@ -95,6 +99,10 @@ VECT_VAR_DECL(vreint_expected_q_p16_p64,poly,16,8) [] = { 0xfff0, 0xffff,
> 0xffff, 0xffff };
> VECT_VAR_DECL(vreint_expected_q_f32_p64,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
> 0xfffffff1, 0xffffffff };
> +VECT_VAR_DECL(vreint_expected_q_f16_p64,hfloat,16,8) [] = { 0xfff0, 0xffff,
> + 0xffff, 0xffff,
> + 0xfff1, 0xffff,
> + 0xffff, 0xffff };
>
> int main (void)
> {
> @@ -124,6 +132,8 @@ int main (void)
> TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vreint_vector, buffer);
> VLOAD(vreint_vector, buffer, , poly, p, 64, 1);
> VLOAD(vreint_vector, buffer, q, poly, p, 64, 2);
> + VLOAD(vreint_vector, buffer, , float, f, 16, 4);
> + VLOAD(vreint_vector, buffer, q, float, f, 16, 8);
> VLOAD(vreint_vector, buffer, , float, f, 32, 2);
> VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
>
> @@ -140,6 +150,7 @@ int main (void)
> TEST_VREINTERPRET(, poly, p, 64, 1, uint, u, 64, 1, vreint_expected_p64_u64);
> TEST_VREINTERPRET(, poly, p, 64, 1, poly, p, 8, 8, vreint_expected_p64_p8);
> TEST_VREINTERPRET(, poly, p, 64, 1, poly, p, 16, 4, vreint_expected_p64_p16);
> + TEST_VREINTERPRET(, poly, p, 64, 1, float, f, 16, 4, vreint_expected_p64_f16);
> TEST_VREINTERPRET(, poly, p, 64, 1, float, f, 32, 2, vreint_expected_p64_f32);
>
> /* vreinterpretq_p64_* tests. */
> @@ -155,6 +166,7 @@ int main (void)
> TEST_VREINTERPRET(q, poly, p, 64, 2, uint, u, 64, 2, vreint_expected_q_p64_u64);
> TEST_VREINTERPRET(q, poly, p, 64, 2, poly, p, 8, 16, vreint_expected_q_p64_p8);
> TEST_VREINTERPRET(q, poly, p, 64, 2, poly, p, 16, 8, vreint_expected_q_p64_p16);
> + TEST_VREINTERPRET(q, poly, p, 64, 2, float, f, 16, 8, vreint_expected_q_p64_f16);
> TEST_VREINTERPRET(q, poly, p, 64, 2, float, f, 32, 4, vreint_expected_q_p64_f32);
>
> /* vreinterpret_*_p64 tests. */
> @@ -171,6 +183,7 @@ int main (void)
> TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 64, 1, vreint_expected_u64_p64);
> TEST_VREINTERPRET(, poly, p, 8, 8, poly, p, 64, 1, vreint_expected_p8_p64);
> TEST_VREINTERPRET(, poly, p, 16, 4, poly, p, 64, 1, vreint_expected_p16_p64);
> + TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 64, 1, vreint_expected_f16_p64);
> TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 64, 1, vreint_expected_f32_p64);
> TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 64, 2, vreint_expected_q_s8_p64);
> TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 64, 2, vreint_expected_q_s16_p64);
> @@ -182,6 +195,7 @@ int main (void)
> TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 64, 2, vreint_expected_q_u64_p64);
> TEST_VREINTERPRET(q, poly, p, 8, 16, poly, p, 64, 2, vreint_expected_q_p8_p64);
> TEST_VREINTERPRET(q, poly, p, 16, 8, poly, p, 64, 2, vreint_expected_q_p16_p64);
> + TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 64, 2, vreint_expected_q_f16_p64);
> TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 64, 2, vreint_expected_q_f32_p64);
>
> return 0;
next prev parent reply other threads:[~2016-05-19 16:24 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-11 13:24 [Patch ARM/AArch64 00/11][testsuite] AdvSIMD intrinsics update Christophe Lyon
2016-05-11 13:24 ` [Patch ARM/AArch64 10/11] Add missing tests for intrinsics operating on poly64 and poly128 types Christophe Lyon
2016-05-13 15:16 ` James Greenhalgh
2016-05-19 16:23 ` Kyrill Tkachov
2016-05-23 9:12 ` Christophe Lyon
2016-05-11 13:24 ` [Patch ARM/AArch64 04/11] Add forgotten vsliq_n_u64 test Christophe Lyon
2016-05-13 14:09 ` James Greenhalgh
2016-05-13 14:22 ` Christophe Lyon
2016-05-16 13:27 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 11/11] Add missing tests for vreinterpret, operating of fp16 type Christophe Lyon
2016-05-13 15:17 ` James Greenhalgh
2016-05-19 16:24 ` Kyrill Tkachov [this message]
2016-05-11 13:24 ` [Patch ARM/AArch64 07/11] Add missing vget_lane fp16 tests Christophe Lyon
2016-05-13 14:38 ` James Greenhalgh
2016-05-16 13:41 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 08/11] Add missing vstX_lane " Christophe Lyon
2016-05-13 14:53 ` James Greenhalgh
2016-05-19 16:20 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 06/11] Add missing vtst_p8 and vtstq_p8 tests Christophe Lyon
2016-05-13 14:37 ` James Greenhalgh
2016-05-13 14:41 ` Christophe Lyon
2016-05-13 14:48 ` James Greenhalgh
2016-05-19 11:54 ` Christophe Lyon
2016-05-20 13:49 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests Christophe Lyon
2016-05-12 8:45 ` Jiong Wang
2016-05-12 12:56 ` Christophe Lyon
2016-05-13 8:39 ` Jiong Wang
2016-05-13 14:56 ` James Greenhalgh
2016-05-19 16:22 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 05/11] Add missing vreinterpretq_p{8,16} tests Christophe Lyon
2016-05-13 14:15 ` James Greenhalgh
2016-05-16 13:31 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 01/11] Fix typo in vreinterpret.c test comment Christophe Lyon
2016-05-13 13:53 ` James Greenhalgh
2016-05-16 13:25 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 03/11] AdvSIMD tests: be more verbose Christophe Lyon
2016-05-13 14:03 ` James Greenhalgh
2016-05-16 13:26 ` Kyrill Tkachov
2016-05-11 13:24 ` [Patch ARM/AArch64 02/11] We can remove useless #ifdefs from these tests: vmul, vshl and vtst Christophe Lyon
2016-05-13 13:56 ` James Greenhalgh
2016-05-16 13:25 ` Kyrill Tkachov
2016-05-13 15:32 ` [Patch ARM/AArch64 00/11][testsuite] AdvSIMD intrinsics update James Greenhalgh
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