From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 54104 invoked by alias); 24 May 2016 08:24:31 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 53682 invoked by uid 89); 24 May 2016 08:24:30 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY autolearn=no version=3.3.2 spammy=19926, 4683, 4686, HX-HELO:eggs.gnu.org X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Tue, 24 May 2016 08:24:15 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b57dF-00010p-A5 for gcc-patches@gcc.gnu.org; Tue, 24 May 2016 04:24:06 -0400 Received: from foss.arm.com ([217.140.101.70]:54210) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b57dF-0000yf-10 for gcc-patches@gcc.gnu.org; Tue, 24 May 2016 04:24:05 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8457C3C for ; Tue, 24 May 2016 01:24:27 -0700 (PDT) Received: from [10.2.206.198] (e104437-lin.cambridge.arm.com [10.2.206.198]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 845AE3F5C4 for ; Tue, 24 May 2016 01:24:04 -0700 (PDT) From: Jiong Wang Subject: [AArch64, 6/6] Reimplement vpadd intrinsics & extend rtl patterns to all modes To: GCC Patches References: <57430251.6060902@foss.arm.com> <57430271.3070504@foss.arm.com> <5743029C.60208@foss.arm.com> <574302DA.6090803@foss.arm.com> <574302FC.5050701@foss.arm.com> <5743031A.8060307@foss.arm.com> Message-ID: <57440FA3.7080409@foss.arm.com> Date: Tue, 24 May 2016 08:24:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <5743031A.8060307@foss.arm.com> Content-Type: multipart/mixed; boundary="------------030008090106030804010901" X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 217.140.101.70 X-IsSubscribed: yes X-SW-Source: 2016-05/txt/msg01863.txt.bz2 This is a multi-part message in MIME format. --------------030008090106030804010901 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 844 These intrinsics was implemented by inline assembly using "faddp" instruction. There was a pattern "aarch64_addpv4sf" which supportsV4SF mode only while we can extend this pattern to support VDQF mode, then we can reimplement these intrinsics through builtlins. gcc/ 2016-05-23 Jiong Wang * config/aarch64/aarch64-builtins.def (faddp): New builtins for modes in VDQF. * config/aarch64/aarch64-simd.md (aarch64_faddp): New. (arch64_addpv4sf): Delete. (reduc_plus_scal_v4sf): Use "gen_aarch64_faddpv4sf" instead of "gen_aarch64_addpv4sf". * gcc/config/aarch64/iterators.md (UNSPEC_FADDP): New. * config/aarch64/arm_neon.h (vpadd_f32): Remove inline assembly. Use builtin. (vpaddq_f32): Likewise. (vpaddq_f64): Likewise. --------------030008090106030804010901 Content-Type: text/x-patch; name="0006-6.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0006-6.patch" Content-length: 5329 >From d97a40ac2e69403b64bcf53596581b49b86ef40c Mon Sep 17 00:00:00 2001 From: "Jiong.Wang" Date: Mon, 23 May 2016 12:13:13 +0100 Subject: [PATCH 6/6] 6 --- gcc/config/aarch64/aarch64-builtins.def | 3 ++ gcc/config/aarch64/aarch64-simd.md | 23 ++++++++------- gcc/config/aarch64/arm_neon.h | 51 ++++++++++++--------------------- gcc/config/aarch64/iterators.md | 1 + 4 files changed, 34 insertions(+), 44 deletions(-) diff --git a/gcc/config/aarch64/aarch64-builtins.def b/gcc/config/aarch64/aarch64-builtins.def index 40baebe..37d8183 100644 --- a/gcc/config/aarch64/aarch64-builtins.def +++ b/gcc/config/aarch64/aarch64-builtins.def @@ -468,3 +468,6 @@ /* Implemented by fabd_3. */ BUILTIN_VALLF (BINOP, fabd, 3) + + /* Implemented by aarch64_faddp. */ + BUILTIN_VDQF (BINOP, faddp, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 71dd74a..9b9f8df 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1992,6 +1992,16 @@ } ) +(define_insn "aarch64_faddp" + [(set (match_operand:VDQF 0 "register_operand" "=w") + (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w") + (match_operand:VDQF 2 "register_operand" "w")] + UNSPEC_FADDP))] + "TARGET_SIMD" + "faddp\t%0., %1., %2." + [(set_attr "type" "neon_fp_reduc_add_")] +) + (define_insn "aarch64_reduc_plus_internal" [(set (match_operand:VDQV 0 "register_operand" "=w") (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] @@ -2019,15 +2029,6 @@ [(set_attr "type" "neon_fp_reduc_add_")] ) -(define_insn "aarch64_addpv4sf" - [(set (match_operand:V4SF 0 "register_operand" "=w") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] - UNSPEC_FADDV))] - "TARGET_SIMD" - "faddp\\t%0.4s, %1.4s, %1.4s" - [(set_attr "type" "neon_fp_reduc_add_s_q")] -) - (define_expand "reduc_plus_scal_v4sf" [(set (match_operand:SF 0 "register_operand") (unspec:V4SF [(match_operand:V4SF 1 "register_operand")] @@ -2036,8 +2037,8 @@ { rtx elt = GEN_INT (ENDIAN_LANE_N (V4SFmode, 0)); rtx scratch = gen_reg_rtx (V4SFmode); - emit_insn (gen_aarch64_addpv4sf (scratch, operands[1])); - emit_insn (gen_aarch64_addpv4sf (scratch, scratch)); + emit_insn (gen_aarch64_faddpv4sf (scratch, operands[1], operands[1])); + emit_insn (gen_aarch64_faddpv4sf (scratch, scratch, scratch)); emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt)); DONE; }) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index ae4c429..a37ceeb 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -8225,17 +8225,6 @@ vpadalq_u32 (uint64x2_t a, uint32x4_t b) return result; } -__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -vpadd_f32 (float32x2_t a, float32x2_t b) -{ - float32x2_t result; - __asm__ ("faddp %0.2s,%1.2s,%2.2s" - : "=w"(result) - : "w"(a), "w"(b) - : /* No clobbers */); - return result; -} - __extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) vpaddl_s8 (int8x8_t a) { @@ -8368,28 +8357,6 @@ vpaddlq_u32 (uint32x4_t a) return result; } -__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vpaddq_f32 (float32x4_t a, float32x4_t b) -{ - float32x4_t result; - __asm__ ("faddp %0.4s,%1.4s,%2.4s" - : "=w"(result) - : "w"(a), "w"(b) - : /* No clobbers */); - return result; -} - -__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -vpaddq_f64 (float64x2_t a, float64x2_t b) -{ - float64x2_t result; - __asm__ ("faddp %0.2d,%1.2d,%2.2d" - : "=w"(result) - : "w"(a), "w"(b) - : /* No clobbers */); - return result; -} - __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) vpaddq_s8 (int8x16_t a, int8x16_t b) { @@ -18629,6 +18596,24 @@ vnegq_s64 (int64x2_t __a) /* vpadd */ +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vpadd_f32 (float32x2_t __a, float32x2_t __b) +{ + return __builtin_aarch64_faddpv2sf (__a, __b); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vpaddq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_aarch64_faddpv4sf (__a, __b); +} + +__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) +vpaddq_f64 (float64x2_t __a, float64x2_t __b) +{ + return __builtin_aarch64_faddpv2df (__a, __b); +} + __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vpadd_s8 (int8x8_t __a, int8x8_t __b) { diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 2264459..7323091 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -219,6 +219,7 @@ UNSPEC_FMIN ; Used in aarch64-simd.md. UNSPEC_FMINNMV ; Used in aarch64-simd.md. UNSPEC_FMINV ; Used in aarch64-simd.md. + UNSPEC_FADDP ; Used in aarch64-simd.md. UNSPEC_FADDV ; Used in aarch64-simd.md. UNSPEC_ADDV ; Used in aarch64-simd.md. UNSPEC_SCVTF ; Used in aarch64-simd.md. -- 1.9.1 --------------030008090106030804010901--