[PATCH][AArch64] Model CSEL instruction in Cortex-A57 scheduling model

[Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>]

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Hi all,

This small patch adds handling of the CSEL-type instructions to the Cortex-A57 scheduling model.
It is treated the same as simple ALU instructions.

With this patch I didn't see any overall differences in SPEC2006.

Bootstrapped and tested on arm-none-linux-gnueabihf and aarch64-linux-gnu.

Ok for trunk?

The patch is very simple and the csel value isn't used in any arm instructions so I think
just an aarch64 approval for this should be enough.

Thanks,
Kyrill

2016-06-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/arm/cortex-a57.md (cortex_a57_alu):
     Handle csel type.

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diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
index 37912db464315a0d70835b81991e8e07a4d9db89..c8cf80f4ba7ed99b46c920c2d0ad3299050ec473 100644
--- a/gcc/config/arm/cortex-a57.md
+++ b/gcc/config/arm/cortex-a57.md
@@ -297,7 +297,7 @@ (define_insn_reservation "cortex_a57_alu" 2
        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
 			alu_sreg,alus_sreg,logic_reg,logics_reg,\
 			adc_imm,adcs_imm,adc_reg,adcs_reg,\
-			adr,bfm,clz,rbit,rev,alu_dsp_reg,\
+			adr,bfm,clz,csel,rbit,rev,alu_dsp_reg,\
 			rotate_imm,shift_imm,shift_reg,\
 			mov_imm,mov_reg,\
 			mvn_imm,mvn_reg,\