diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 22ecd52f67238724d55271a3732f8d706f6b683d..b4f327022b966db718bdce74ce3d28e3dae568a2 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -129,6 +129,7 @@ ARM_CORE("cortex-a35", cortexa35, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53) ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) +ARM_CORE("cortex-a73", cortexa73, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73) ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1) ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A), xgene1) @@ -136,3 +137,6 @@ ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCH /* V8 big.LITTLE implementations */ ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) +ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73) +ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73) + diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 7264bff9a349a3b2dd84d5a7cee8860cd24cbfcc..c665f65a3f0398148fb073861de6edc86ea19de5 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -229,6 +229,9 @@ EnumValue Enum(processor_type) String(cortex-a72) Value(cortexa72) EnumValue +Enum(processor_type) String(cortex-a73) Value(cortexa73) + +EnumValue Enum(processor_type) String(exynos-m1) Value(exynosm1) EnumValue @@ -243,6 +246,12 @@ Enum(processor_type) String(cortex-a57.cortex-a53) Value(cortexa57cortexa53) EnumValue Enum(processor_type) String(cortex-a72.cortex-a53) Value(cortexa72cortexa53) +EnumValue +Enum(processor_type) String(cortex-a73.cortex-a35) Value(cortexa73cortexa35) + +EnumValue +Enum(processor_type) String(cortex-a73.cortex-a53) Value(cortexa73cortexa53) + Enum Name(arm_arch) Type(int) Known ARM architectures (for use with the -march= option): diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index a337304340a5322840f2ba863d703188f051f4fa..50710232d45db3a87ff83cd9728495c01697e904 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -16,13 +16,15 @@ (define_attr "tune" arm1156t2s,arm1156t2fs,cortexm1, cortexm0,cortexm0plus,cortexm1smallmultiply, cortexm0smallmultiply,cortexm0plussmallmultiply,genericv7a, - cortexa5,cortexa7,cortexr8,cortexa8, + cortexa5,cortexa7,cortexa8, cortexa9,cortexa12,cortexa15, cortexa17,cortexr4,cortexr4f, - cortexr5,cortexr7,cortexm7, - cortexm4,cortexm3,marvell_pj4, - cortexa15cortexa7,cortexa17cortexa7,cortexa32, - cortexa35,cortexa53,cortexa57, - cortexa72,exynosm1,qdf24xx, - xgene1,cortexa57cortexa53,cortexa72cortexa53" + cortexr5,cortexr7,cortexr8, + cortexm7,cortexm4,cortexm3, + marvell_pj4,cortexa15cortexa7,cortexa17cortexa7, + cortexa32,cortexa35,cortexa53, + cortexa57,cortexa72,cortexa73, + exynosm1,qdf24xx,xgene1, + cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35, + cortexa73cortexa53" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 50f2e89095a4489962736894560b7a0eeaed1ad7..0adf83dac67a36f1fc50a3a85cc99a2a9b73da77 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2066,6 +2066,29 @@ const struct tune_params arm_cortex_a12_tune = tune_params::SCHED_AUTOPREF_OFF }; +const struct tune_params arm_cortex_a73_tune = +{ + arm_9e_rtx_costs, + &cortexa57_extra_costs, + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ + 1, /* Constant limit. */ + 2, /* Max cond insns. */ + 8, /* Memset max inline. */ + 2, /* Issue rate. */ + ARM_PREFETCH_NOT_BENEFICIAL, + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_TRUE, + tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_ALL, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_TRUE, + FUSE_OPS (tune_params::FUSE_AES_AESMC | tune_params::FUSE_MOVW_MOVT), + tune_params::SCHED_AUTOPREF_FULL +}; + /* armv7m tuning. On Cortex-M4 cores for example, MOVW/MOVT take a single cycle to execute each. An LDR from the constant pool also takes two cycles to execute, but mildly increases pipelining opportunity (consecutive diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index 18a35a828fd34e6d8810d123f914224f2a8288ea..6039655a491af56538d544240dc4d4048150388f 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -72,6 +72,9 @@ |mcpu=cortex-a57.cortex-a53 \ |mcpu=cortex-a72 \ |mcpu=cortex-a72.cortex-a53 \ + |mcpu=cortex-a73 \ + |mcpu=cortex-a73.cortex-a35 \ + |mcpu=cortex-a73.cortex-a53 \ |mcpu=exynos-m1 \ |mcpu=qdf24xx \ |mcpu=xgene1 \ @@ -102,6 +105,9 @@ |mcpu=cortex-a57.cortex-a53 \ |mcpu=cortex-a72 \ |mcpu=cortex-a72.cortex-a53 \ + |mcpu=cortex-a73 \ + |mcpu=cortex-a73.cortex-a35 \ + |mcpu=cortex-a73.cortex-a53 \ |mcpu=exynos-m1 \ |mcpu=qdf24xx \ |mcpu=xgene1 \ diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile index b0ecc2fe45da581b6f1cf1a3e1aea7d428c0e533..1b34b5444aaddf4234b3aa9041cb758b4328e02a 100644 --- a/gcc/config/arm/t-aprofile +++ b/gcc/config/arm/t-aprofile @@ -93,6 +93,9 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57.cortex-a53 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a72 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a72.cortex-a53 +MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73 +MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a35 +MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a53 MULTILIB_MATCHES += march?armv8-a=mcpu?exynos-m1 MULTILIB_MATCHES += march?armv8-a=mcpu?qdf24xx MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 0e18dc27aa2c80eb7abc65c7528da1ea1b1a2bf7..5e9d92eadb1b850031b19a3045ef9fdd515494ff 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14102,7 +14102,7 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, -@samp{cortex-a72}, @samp{cortex-r4}, +@samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-m7}, @samp{cortex-m4}, @@ -14123,7 +14123,8 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: @samp{cortex-a15.cortex-a7}, @samp{cortex-a17.cortex-a7}, -@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}. +@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, +@samp{cortex-a72.cortex-a35}, @samp{cortex-a73.cortex-a53}. @option{-mtune=generic-@var{arch}} specifies that GCC should tune the performance for a blend of processors within architecture @var{arch}.