This patch adds instruction scheduling support for the Power9 processor. Bootstrap/regression tested on powerpc64/powerpc64le with no new failures. Ok for trunk? Ok for backport to GCC 6 branch after successful bootstrap/regtest there? -Pat 2016-06-21 Pat Haugen * config/rs6000/power8.md (power8-fp): Include dfp type. * config/rs6000/power6.md (power6-fp): Likewise. * config/rs6000/htm.md (various insns): Change type atribute to htmsimple and set power9_alu2 appropriately. * config/rs6000/power9.md: New file. * config/rs6000/t-rs6000 (MD_INCLUDES): Add power9.md. * config/rs6000/power7.md (power7-fp): Include dfp type. * config/rs6000/rs6000.c (power9_cost): Update costs, cache size and prefetch streams. (rs6000_option_override_internal): Remove temporary code setting tuning to power8. Don't set rs6000_sched_groups for power9. (last_scheduled_insn): Change to rtx_insn *. (divCnt, vec_load_pendulum): New variables. (rs6000_adjust_cost): Add Power9 to test for store->load separation. (rs6000_issue_rate): Set issue rate for Power9. (is_power9_pairable_vec_type): New. (rs6000_sched_reorder2): Add Power9 code to group fixed point divide insns and group/alternate vector operations with vector loads. (insn_must_be_first_in_group): Remove Power9. (insn_must_be_last_in_group): Likewise. (force_new_group): Likewise. (rs6000_sched_init): Fix initialization of last_scheduled_insn. Initialize divCnt/vec_load_pendulum. (_rs6000_sched_context, rs6000_init_sched_context, rs6000_set_sched_context): Handle context save/restore of new variables. * config/rs6000/vsx.md (various insns): Set power9_alu2 attribute. * config/rs6000/altivec.md (various insns): Likewise. * config/rs6000/dfp.md (various insns): Change type attribute to dfp. * config/rs6000/crypto.md (crypto_vshasigma): Change type and set power9_alu2. * config/rs6000/rs6000.md ('type' attribute): Add htmsimple/dfp types. Define "power9_alu2" and "mnemonic" attributes. Include power9.md. (*cmp_fpr, *fpmask): Set power9_alu2 attribute. (*cmp_hw): Change type to veccmp.