From: Pat Haugen <pthaugen@linux.vnet.ibm.com>
To: Segher Boessenkool <segher@kernel.crashing.org>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
David Edelsohn <dje.gcc@gmail.com>
Subject: Re: [PATCH, rs6000] Scheduling update
Date: Mon, 27 Jun 2016 14:58:00 -0000 [thread overview]
Message-ID: <57713E11.7040404@linux.vnet.ibm.com> (raw)
In-Reply-To: <20160622191044.GA15865@gate.crashing.org>
[-- Attachment #1: Type: text/plain, Size: 5186 bytes --]
On 06/22/2016 02:10 PM, Segher Boessenkool wrote:
> The "power9_alu2" attribute is writing part of the scheduling description
> inside the machine description proper. Can this be reduced, maybe by
> adding an attribute describing something about the insns that makes them
> be handled by the alu2? I realise it isn't all so regular :-(
>> > +; 2 cycle FP ops
>> > +(define_attr "power9_fp_2cyc" "no,yes"
>> > + (cond [(eq_attr "mnemonic" "fabs,fcpsgn,fmr,fmrgow,fnabs,fneg,\
>> > + xsabsdp,xscpsgndp,xsnabsdp,xsnegdp,\
>> > + xsabsqp,xscpsgnqp,xsnabsqp,xsnegqp")
>> > + (const_string "yes")]
>> > + (const_string "no")))
> Eww. Can we have an attribute for the FP move instructions, instead?
> Maybe a value "fpmove" for the "type", even?
The following patch adds new insn 'type' values that will be used for the Power9 patch to overcome the items listed above. There is no functional change to existing processor types. Bootstrap/regtested on powerpc64/powerpc64le with no new failures. Ok for trunk? Ok for backport to GCC 6 branch after successful bootstrap/regtest there?
-Pat
2016-06-27 Pat Haugen <pthaugen@us.ibm.com>
* config/rs6000/rs6000.md ('type' attribute): Add
vec_logical,veccmp_fx,vec_extend,vecmove insn types.
(*abs<mode>2_fpr, *nabs<mode>2_fpr, *neg<mode>2_fpr, *extendsfdf2_fpr,
copysign<mode>3_fcpsgn, trunc<mode>df2_internal1, neg<mode>2_internal,
p8_fmrgow_<mode>, pack<mode>): Change type to fpsimple.
(*xxsel<mode>, copysign<mode>3_hard, neg<mode>2_hw, abs<mode>2_hw,
*nabs<mode>2_hw): Change type to vecmove.
(*and<mode>3_internal, *bool<mode>3_internal, *boolc<mode>3_internal,
*boolcc<mode>3_internal, *eqv<mode>3_internal,
*one_cmpl<mode>3_internal, *ieee_128bit_vsx_neg<mode>2_internal,
*ieee_128bit_vsx_abs<mode>2_internal,
*ieee_128bit_vsx_nabs<mode>2_internal, extendkftf2, trunctfkf2,
*ieee128_mfvsrd_64bit, *ieee128_mfvsrd_32bit, *ieee128_mtvsrd_64bit,
*ieee128_mtvsrd_32bit): Change type to vec_logical.
(mov<mode>_hardfloat, *mov<mode>_hardfloat32, *mov<mode>_hardfloat64,
*movdi_internal32, *movdi_internal64): Update insn types.
* config/rs6000/vsx.md (*vsx_le_undo_permute_<mode>,
vsx_extract_<mode>): Change type to vec_logical.
(*vsx_xxsel<mode>, *vsx_xxsel<mode>_uns): Change type to vecmove.
(vsx_sign_extend_qi_<mode>, *vsx_sign_extend_hi_<mode>,
*vsx_sign_extend_si_v2di): Change type to vec_extend.
* config/rs6000/altivec.md (*altivec_mov<mode>, *altivec_movti): Change
type to vec_logical.
(*altivec_eq<mode>, *altivec_gt<mode>, *altivec_gtu<mode>,
*altivec_vcmpequ<VI_char>_p, *altivec_vcmpgts<VI_char>_p,
*altivec_vcmpgtu<VI_char>_p): Change type to veccmp_fx.
(*altivec_vsel<mode>, *altivec_vsel<mode>_uns): Change type to vecmove.
* config/rs6000/dfp.md (*negdd2_fpr, *absdd2_fpr, *nabsdd2_fpr,
negtd2, *abstd2_fpr, *nabstd2_fpr): Change type to fpsimple.
* config/rs6000/40x.md (ppc405-float): Add fpsimple.
* config/rs6000/440.md (ppc440-fp): Add fpsimple.
* config/rs6000/476.md (ppc476-fp): Add fpsimple.
* config/rs6000/601.md (ppc601-fp): Add fpsimple.
* config/rs6000/603.md (ppc603-fp): Add fpsimple.
* config/rs6000/6xx.md (ppc604-fp): Add fpsimple.
* config/rs6000/7xx.md (ppc750-fp): Add fpsimple.
(ppc7400-vecsimple): Add vec_logical, vecmove, veccmp_fx.
* config/rs6000/7450.md (ppc7450-fp): Add fpsimple.
(ppc7450-vecsimple): Add vec_logical, vecmove.
(ppc7450-veccmp): Add veccmp_fx.
* config/rs6000/8540.md (ppc8540_simple_vector): Add vec_logical,
vecmove.
(ppc8540_vector_compare): Add veccmp_fx.
* config/rs6000/a2.md (ppca2-fp): Add fpsimple.
* config/rs6000/cell.md (cell-fp): Add fpsimple.
(cell-vecsimple): Add vec_logical, vecmove.
(cell-veccmp): Add veccmp_fx.
* config/rs6000/e300c2c3.md (ppce300c3_fp): Add fpsimple.
* config/rs6000/e6500.md (e6500_vecsimple): Add vec_logical, vecmove,
veccmp_fx.
* config/rs6000/mpc.md (mpccore-fp): Add fpsimple.
* config/rs6000/power4.md (power4-fp): Add fpsimple.
(power4-vecsimple): Add vec_logical, vecmove.
(power4-veccmp): Add veccmp_fx.
* config/rs6000/power5.md (power5-fp): Add fpsimple.
* config/rs6000/power6.md (power6-fp): Add fpsimple.
(power6-vecsimple): Add vec_logical, vecmove.
(power6-veccmp): Add veccmp_fx.
* config/rs6000/power7.md (power7-fp): Add fpsimple.
(power7-vecsimple): Add vec_logical, vecmove, veccmp_fx.
* config/rs6000/power8.md (power8-fp): Add fpsimple.
(power8-vecsimple): Add vec_logical, vecmove, veccmp_fx.
* config/rs6000/rs64.md (rs64a-fp): Add fpsimple.
* config/rs6000/titan.md (titan_fp): Add fpsimple.
* config/rs6000/xfpu.md (fp-default, fp-addsub-s, fp-addsub-d): Add
fpsimple.
* config/rs6000/rs6000.c (rs6000_adjust_cost): Add TYPE_FPSIMPLE.
[-- Attachment #2: insn_types.diff --]
[-- Type: text/x-patch, Size: 34643 bytes --]
Index: config/rs6000/476.md
===================================================================
--- config/rs6000/476.md (revision 237783)
+++ config/rs6000/476.md (working copy)
@@ -124,7 +124,7 @@ (define_insn_reservation "ppc476-fpcompa
ppc476_f_pipe+ppc476_i_pipe")
(define_insn_reservation "ppc476-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc476"))
"ppc476_issue_fp,\
ppc476_f_pipe")
Index: config/rs6000/e300c2c3.md
===================================================================
--- config/rs6000/e300c2c3.md (revision 237783)
+++ config/rs6000/e300c2c3.md (working copy)
@@ -150,7 +150,7 @@ (define_insn_reservation "ppce300c3_fpco
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fp" 3
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
Index: config/rs6000/power8.md
===================================================================
--- config/rs6000/power8.md (revision 237783)
+++ config/rs6000/power8.md (working copy)
@@ -317,7 +317,7 @@ (define_bypass 4 "power8-branch" "power8
; VS Unit (includes FP/VSX/VMX/DFP/Crypto)
(define_insn_reservation "power8-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
@@ -350,7 +350,8 @@ (define_insn_reservation "power8-dsqrt"
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-vecsimple" 2
- (and (eq_attr "type" "vecperm,vecsimple,veccmp")
+ (and (eq_attr "type" "vecperm,vecsimple,vec_logical,vecmove,veccmp,
+ veccmp_fx")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
Index: config/rs6000/6xx.md
===================================================================
--- config/rs6000/6xx.md (revision 237783)
+++ config/rs6000/6xx.md (working copy)
@@ -160,7 +160,7 @@ (define_insn_reservation "ppc604-fpcompa
"fpu_6xx")
(define_insn_reservation "ppc604-fp" 3
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx")
Index: config/rs6000/8540.md
===================================================================
--- config/rs6000/8540.md (revision 237783)
+++ config/rs6000/8540.md (working copy)
@@ -190,7 +190,7 @@ (define_insn_reservation "ppc8540_brinc"
;; Simple vector
(define_insn_reservation "ppc8540_simple_vector" 1
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,vec_logical,vecmove")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
@@ -202,7 +202,7 @@ (define_insn_reservation "ppc8540_simple
;; Vector compare
(define_insn_reservation "ppc8540_vector_compare" 1
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmp_fx")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
Index: config/rs6000/7450.md
===================================================================
--- config/rs6000/7450.md (revision 237783)
+++ config/rs6000/7450.md (working copy)
@@ -120,7 +120,7 @@ (define_insn_reservation "ppc7450-fpcomp
"ppc7450_du,fpu_7450")
(define_insn_reservation "ppc7450-fp" 5
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,fpu_7450")
@@ -162,7 +162,7 @@ (define_insn_reservation "ppc7450-jmpreg
;; Altivec
(define_insn_reservation "ppc7450-vecsimple" 1
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,vec_logical,vecmove")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,vecsmpl_7450")
@@ -172,7 +172,7 @@ (define_insn_reservation "ppc7450-veccom
"ppc7450_du,ppc7450_vec_du,veccmplx_7450")
(define_insn_reservation "ppc7450-veccmp" 2
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmp_fx")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,veccmplx_7450")
Index: config/rs6000/440.md
===================================================================
--- config/rs6000/440.md (revision 237783)
+++ config/rs6000/440.md (working copy)
@@ -107,7 +107,7 @@ (define_insn_reservation "ppc440-fpcompa
"ppc440_issue,ppc440_f_pipe+ppc440_i_pipe")
(define_insn_reservation "ppc440-fp" 5
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe")
Index: config/rs6000/power6.md
===================================================================
--- config/rs6000/power6.md (revision 237783)
+++ config/rs6000/power6.md (working copy)
@@ -500,7 +500,7 @@ (define_insn_reservation "power6-mtcr" 4
(define_bypass 9 "power6-mtcr" "power6-branch")
(define_insn_reservation "power6-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power6"))
"FPU_power6")
@@ -556,7 +556,7 @@ (define_insn_reservation "power6-vecstor
"LSF_power6")
(define_insn_reservation "power6-vecsimple" 3
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,vec_logical,vecmove")
(eq_attr "cpu" "power6"))
"FPU_power6")
@@ -568,7 +568,7 @@ (define_bypass 5 "power6-vecsimple" "pow
(define_bypass 4 "power6-vecsimple" "power6-vecstore" )
(define_insn_reservation "power6-veccmp" 1
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmp_fx")
(eq_attr "cpu" "power6"))
"FPU_power6")
Index: config/rs6000/rs64.md
===================================================================
--- config/rs6000/rs64.md (revision 237783)
+++ config/rs6000/rs64.md (working copy)
@@ -111,7 +111,7 @@ (define_insn_reservation "rs64a-fpcompar
"mciu_rs64,fpu_rs64,bpu_rs64")
(define_insn_reservation "rs64a-fp" 4
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "rs64a"))
"mciu_rs64,fpu_rs64")
Index: config/rs6000/e6500.md
===================================================================
--- config/rs6000/e6500.md (revision 237783)
+++ config/rs6000/e6500.md (working copy)
@@ -205,7 +205,7 @@ (define_insn_reservation "e6500_cr_logic
;; VSFX.
(define_insn_reservation "e6500_vecsimple" 1
- (and (eq_attr "type" "vecsimple,veccmp")
+ (and (eq_attr "type" "vecsimple,vec_logical,vecmove,veccmp,veccmp_fx")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_vec")
Index: config/rs6000/40x.md
===================================================================
--- config/rs6000/40x.md (revision 237783)
+++ config/rs6000/40x.md (working copy)
@@ -119,6 +119,6 @@ (define_insn_reservation "ppc403-cr" 2
"bpu_40x")
(define_insn_reservation "ppc405-float" 11
- (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,dmul,sdiv,ddiv")
+ (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,fpsimple,dmul,sdiv,ddiv")
(eq_attr "cpu" "ppc405"))
"fpu_405*10")
Index: config/rs6000/power4.md
===================================================================
--- config/rs6000/power4.md (revision 237783)
+++ config/rs6000/power4.md (working copy)
@@ -381,7 +381,7 @@ (define_insn_reservation "power4-mtcr" 4
; Basic FP latency is 6 cycles
(define_insn_reservation "power4-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power4"))
"fpq_power4")
@@ -410,7 +410,7 @@ (define_insn_reservation "power4-isync"
; VMX
(define_insn_reservation "power4-vecsimple" 2
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,vec_logical,vecmove")
(eq_attr "cpu" "power4"))
"vq_power4")
@@ -421,7 +421,7 @@ (define_insn_reservation "power4-veccomp
; vecfp compare
(define_insn_reservation "power4-veccmp" 8
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmp_fx")
(eq_attr "cpu" "power4"))
"vq_power4")
Index: config/rs6000/xfpu.md
===================================================================
--- config/rs6000/xfpu.md (revision 237783)
+++ config/rs6000/xfpu.md (working copy)
@@ -55,7 +55,7 @@ (define_cpu_unit "Xfpu_issue,Xfpu_addsub
(define_insn_reservation "fp-default" 2
(and (and
- (eq_attr "type" "fp")
+ (eq_attr "type" "fp,fpsimple")
(eq_attr "fp_type" "fp_default"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2")
@@ -67,14 +67,14 @@ (define_insn_reservation "fp-compare" 6
(define_insn_reservation "fp-addsub-s" 14
(and (and
- (eq_attr "type" "fp")
+ (eq_attr "type" "fp,fpsimple")
(eq_attr "fp_type" "fp_addsub_s"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_addsub")
(define_insn_reservation "fp-addsub-d" 18
(and (and
- (eq_attr "type" "fp")
+ (eq_attr "type" "fp,fpsimple")
(eq_attr "fp_type" "fp_addsub_d"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_addsub")
Index: config/rs6000/603.md
===================================================================
--- config/rs6000/603.md (revision 237783)
+++ config/rs6000/603.md (working copy)
@@ -105,7 +105,7 @@ (define_insn_reservation "ppc603-fpcompa
"(fpu_603+iu_603*2),bpu_603")
(define_insn_reservation "ppc603-fp" 3
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc603"))
"fpu_603")
Index: config/rs6000/mpc.md
===================================================================
--- config/rs6000/mpc.md (revision 237783)
+++ config/rs6000/mpc.md (working copy)
@@ -81,7 +81,7 @@ (define_insn_reservation "mpccore-fpcomp
"fpu_mpc,bpu_mpc")
(define_insn_reservation "mpccore-fp" 4
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "mpccore"))
"fpu_mpc*2")
Index: config/rs6000/cell.md
===================================================================
--- config/rs6000/cell.md (revision 237783)
+++ config/rs6000/cell.md (working copy)
@@ -306,7 +306,7 @@ (define_insn_reservation "cell-mtcrf" 1
; Basic FP latency is 10 cycles, thoughput is 1/cycle
(define_insn_reservation "cell-fp" 10
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*8")
@@ -329,7 +329,7 @@ (define_insn_reservation "cell-sqrt" 84
; VMX
(define_insn_reservation "cell-vecsimple" 4
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,vec_logical,vecmove")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*2")
@@ -341,7 +341,7 @@ (define_insn_reservation "cell-veccomple
;; TODO: add support for recording instructions
(define_insn_reservation "cell-veccmp" 4
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmp_fx")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*2")
Index: config/rs6000/power7.md
===================================================================
--- config/rs6000/power7.md (revision 237783)
+++ config/rs6000/power7.md (working copy)
@@ -292,7 +292,7 @@ (define_insn_reservation "power7-branch"
; VS Unit (includes FP/VSX/VMX/DFP)
(define_insn_reservation "power7-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power7"))
"DU_power7,VSU_power7")
@@ -324,7 +324,7 @@ (define_insn_reservation "power7-dsqrt"
"DU_power7,VSU_power7")
(define_insn_reservation "power7-vecsimple" 2
- (and (eq_attr "type" "vecsimple,veccmp")
+ (and (eq_attr "type" "vecsimple,vec_logical,vecmove,veccmp,veccmp_fx")
(eq_attr "cpu" "power7"))
"DU_power7,vsu1_power7")
Index: config/rs6000/7xx.md
===================================================================
--- config/rs6000/7xx.md (revision 237783)
+++ config/rs6000/7xx.md (working copy)
@@ -113,7 +113,7 @@ (define_insn_reservation "ppc750-fpcompa
"ppc750_du,fpu_7xx")
(define_insn_reservation "ppc750-fp" 3
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,fpu_7xx")
@@ -165,7 +165,7 @@ (define_insn_reservation "ppc750-jmpreg"
;; Altivec
(define_insn_reservation "ppc7400-vecsimple" 1
- (and (eq_attr "type" "vecsimple,veccmp")
+ (and (eq_attr "type" "vecsimple,vec_logical,vecmove,veccmp,veccmp_fx")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,ppc7400_vec_du,veccmplx_7xx")
Index: config/rs6000/rs6000.c
===================================================================
--- config/rs6000/rs6000.c (revision 237783)
+++ config/rs6000/rs6000.c (working copy)
@@ -30195,7 +30195,9 @@ rs6000_adjust_cost (rtx_insn *insn, rtx
switch (attr_type)
{
case TYPE_FP:
- if (get_attr_type (dep_insn) == TYPE_FP)
+ case TYPE_FPSIMPLE:
+ if (get_attr_type (dep_insn) == TYPE_FP
+ || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
return 1;
break;
case TYPE_FPLOAD:
Index: config/rs6000/titan.md
===================================================================
--- config/rs6000/titan.md (revision 237783)
+++ config/rs6000/titan.md (working copy)
@@ -156,7 +156,7 @@ (define_insn_reservation "titan_fp_singl
;; Make sure the "titan_fp" rule stays last, as it's a catch all for
;; double-precision and unclassified (e.g. fsel) FP-instructions
(define_insn_reservation "titan_fp" 10
- (and (eq_attr "type" "fpcompare,fp,dmul")
+ (and (eq_attr "type" "fpcompare,fp,fpsimple,dmul")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fp0*2,nothing*8,titan_fpwb")
Index: config/rs6000/vsx.md
===================================================================
--- config/rs6000/vsx.md (revision 237783)
+++ config/rs6000/vsx.md (working copy)
@@ -685,7 +685,7 @@ (define_insn_and_split "*vsx_le_undo_per
}
}
[(set_attr "length" "0,4")
- (set_attr "type" "vecsimple")])
+ (set_attr "type" "vec_logical")])
(define_insn_and_split "*vsx_le_perm_load_<mode>"
[(set (match_operand:VSX_LE_128 0 "vsx_register_operand" "=<VSa>")
@@ -1492,7 +1492,7 @@ (define_insn "*vsx_xxsel<mode>"
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsel %x0,%x3,%x2,%x1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
(define_insn "*vsx_xxsel<mode>_uns"
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>")
@@ -1503,7 +1503,7 @@ (define_insn "*vsx_xxsel<mode>_uns"
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsel %x0,%x3,%x2,%x1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
;; Copy sign
(define_insn "vsx_copysign<mode>3"
@@ -2157,7 +2157,7 @@ (define_insn "vsx_extract_<mode>"
else
gcc_unreachable ();
}
- [(set_attr "type" "vecsimple,mftgpr,mftgpr,vecperm")])
+ [(set_attr "type" "vec_logical,mftgpr,mftgpr,vecperm")])
;; Optimize extracting a single scalar element from memory if the scalar is in
;; the correct location to use a single load.
@@ -2703,7 +2703,7 @@ (define_insn "vsx_sign_extend_qi_<mode>"
UNSPEC_VSX_SIGN_EXTEND))]
"TARGET_P9_VECTOR"
"vextsb2<wd> %0,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vec_extend")])
(define_insn "*vsx_sign_extend_hi_<mode>"
[(set (match_operand:VSINT_84 0 "vsx_register_operand" "=v")
@@ -2712,7 +2712,7 @@ (define_insn "*vsx_sign_extend_hi_<mode>
UNSPEC_VSX_SIGN_EXTEND))]
"TARGET_P9_VECTOR"
"vextsh2<wd> %0,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vec_extend")])
(define_insn "*vsx_sign_extend_si_v2di"
[(set (match_operand:V2DI 0 "vsx_register_operand" "=v")
@@ -2720,4 +2720,4 @@ (define_insn "*vsx_sign_extend_si_v2di"
UNSPEC_VSX_SIGN_EXTEND))]
"TARGET_P9_VECTOR"
"vextsw2d %0,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vec_extend")])
Index: config/rs6000/altivec.md
===================================================================
--- config/rs6000/altivec.md (revision 237783)
+++ config/rs6000/altivec.md (working copy)
@@ -242,7 +242,7 @@ (define_insn "*altivec_mov<mode>"
default: gcc_unreachable ();
}
}
- [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*,*")
+ [(set_attr "type" "vecstore,vecload,vec_logical,store,load,*,vec_logical,*,*")
(set_attr "length" "4,4,4,20,20,20,4,8,32")])
;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode
@@ -268,7 +268,7 @@ (define_insn "*altivec_movti"
default: gcc_unreachable ();
}
}
- [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")])
+ [(set_attr "type" "vecstore,vecload,vec_logical,store,load,*,vec_logical,*")])
;; Load up a vector with the most significant bit set by loading up -1 and
;; doing a shift left
@@ -603,7 +603,7 @@ (define_insn "*altivec_eq<mode>"
(match_operand:VI2 2 "altivec_register_operand" "v")))]
"<VI_unit>"
"vcmpequ<VI_char> %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmp_fx")])
(define_insn "*altivec_gt<mode>"
[(set (match_operand:VI2 0 "altivec_register_operand" "=v")
@@ -611,7 +611,7 @@ (define_insn "*altivec_gt<mode>"
(match_operand:VI2 2 "altivec_register_operand" "v")))]
"<VI_unit>"
"vcmpgts<VI_char> %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmp_fx")])
(define_insn "*altivec_gtu<mode>"
[(set (match_operand:VI2 0 "altivec_register_operand" "=v")
@@ -619,7 +619,7 @@ (define_insn "*altivec_gtu<mode>"
(match_operand:VI2 2 "altivec_register_operand" "v")))]
"<VI_unit>"
"vcmpgtu<VI_char> %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmp_fx")])
(define_insn "*altivec_eqv4sf"
[(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
@@ -654,7 +654,7 @@ (define_insn "*altivec_vsel<mode>"
(match_operand:VM 3 "altivec_register_operand" "v")))]
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
"vsel %0,%3,%2,%1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
(define_insn "*altivec_vsel<mode>_uns"
[(set (match_operand:VM 0 "altivec_register_operand" "=v")
@@ -665,7 +665,7 @@ (define_insn "*altivec_vsel<mode>_uns"
(match_operand:VM 3 "altivec_register_operand" "v")))]
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
"vsel %0,%3,%2,%1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
;; Fused multiply add.
@@ -2283,7 +2283,7 @@ (define_insn "*altivec_vcmpequ<VI_char>_
(match_dup 2)))]
"<VI_unit>"
"vcmpequ<VI_char>. %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmp_fx")])
(define_insn "*altivec_vcmpgts<VI_char>_p"
[(set (reg:CC 74)
@@ -2295,7 +2295,7 @@ (define_insn "*altivec_vcmpgts<VI_char>_
(match_dup 2)))]
"<VI_unit>"
"vcmpgts<VI_char>. %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmp_fx")])
(define_insn "*altivec_vcmpgtu<VI_char>_p"
[(set (reg:CC 74)
@@ -2307,7 +2307,7 @@ (define_insn "*altivec_vcmpgtu<VI_char>_
(match_dup 2)))]
"<VI_unit>"
"vcmpgtu<VI_char>. %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmp_fx")])
(define_insn "*altivec_vcmpeqfp_p"
[(set (reg:CC 74)
Index: config/rs6000/601.md
===================================================================
--- config/rs6000/601.md (revision 237783)
+++ config/rs6000/601.md (working copy)
@@ -86,7 +86,7 @@ (define_insn_reservation "ppc601-fpcompa
"(fpu_ppc601+iu_ppc601*2),nothing*2,bpu_ppc601")
(define_insn_reservation "ppc601-fp" 4
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc601"))
"fpu_ppc601")
Index: config/rs6000/dfp.md
===================================================================
--- config/rs6000/dfp.md (revision 237783)
+++ config/rs6000/dfp.md (working copy)
@@ -89,7 +89,7 @@ (define_insn "*negdd2_fpr"
(neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fneg %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_expand "absdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "")
@@ -102,14 +102,14 @@ (define_insn "*absdd2_fpr"
(abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_insn "*nabsdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fnabs %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_expand "negtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "")
@@ -124,7 +124,7 @@ (define_insn "*negtd2_fpr"
"@
fneg %0,%1
fneg %0,%1\;fmr %L0,%L1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
(define_expand "abstd2"
@@ -140,7 +140,7 @@ (define_insn "*abstd2_fpr"
"@
fabs %0,%1
fabs %0,%1\;fmr %L0,%L1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
(define_insn "*nabstd2_fpr"
@@ -150,7 +150,7 @@ (define_insn "*nabstd2_fpr"
"@
fnabs %0,%1
fnabs %0,%1\;fmr %L0,%L1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
;; Hardware support for decimal floating point operations.
Index: config/rs6000/power5.md
===================================================================
--- config/rs6000/power5.md (revision 237783)
+++ config/rs6000/power5.md (working copy)
@@ -322,7 +322,7 @@ (define_insn_reservation "power5-mtcr" 4
; Basic FP latency is 6 cycles
(define_insn_reservation "power5-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power5"))
"fpq_power5")
Index: config/rs6000/rs6000.md
===================================================================
--- config/rs6000/rs6000.md (revision 237783)
+++ config/rs6000/rs6000.md (working copy)
@@ -183,6 +183,7 @@ (define_attr "type"
brinc,
vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
+ vec_logical,veccmp_fx,vec_extend,vecmove,
htm"
(const_string "integer"))
@@ -4348,7 +4349,7 @@ (define_insn "*abs<mode>2_fpr"
"@
fabs %0,%1
xsabsdp %x0,%x1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_insn "*nabs<mode>2_fpr"
@@ -4360,7 +4361,7 @@ (define_insn "*nabs<mode>2_fpr"
"@
fnabs %0,%1
xsnabsdp %x0,%x1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "neg<mode>2"
@@ -4376,7 +4377,7 @@ (define_insn "*neg<mode>2_fpr"
"@
fneg %0,%1
xsnegdp %x0,%x1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "add<mode>3"
@@ -4537,7 +4538,7 @@ (define_insn_and_split "*extendsfdf2_fpr
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "fp,fp,fpload,fp,fp,fpload,fpload")])
+ [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload")])
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
@@ -4627,7 +4628,7 @@ (define_insn "copysign<mode>3_fcpsgn"
"@
fcpsgn %0,%2,%1
xscpsgndp %x0,%x2,%x1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
;; fsel instruction and some auxiliary computations. Then we just have a
@@ -4840,7 +4841,7 @@ (define_insn "*xxsel<mode>"
(match_operand:SFDF 4 "vsx_register_operand" "<Fv>")))]
"TARGET_P9_MINMAX"
"xxsel %x0,%x1,%x3,%x4"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
\f
;; Conversions to and from floating-point.
@@ -5951,7 +5952,7 @@ (define_insn_and_split "*and<mode>3_inte
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "vec_logical")
(const_string "integer")))
(set (attr "length")
(if_then_else
@@ -5987,7 +5988,7 @@ (define_insn_and_split "*bool<mode>3_int
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "vec_logical")
(const_string "integer")))
(set (attr "length")
(if_then_else
@@ -6025,7 +6026,7 @@ (define_insn_and_split "*boolc<mode>3_in
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "vec_logical")
(const_string "integer")))
(set (attr "length")
(if_then_else
@@ -6085,7 +6086,7 @@ (define_insn_and_split "*boolcc<mode>3_i
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "vec_logical")
(const_string "integer")))
(set (attr "length")
(if_then_else
@@ -6143,7 +6144,7 @@ (define_insn_and_split "*eqv<mode>3_inte
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "vec_logical")
(const_string "integer")))
(set (attr "length")
(if_then_else
@@ -6199,7 +6200,7 @@ (define_insn_and_split "*one_cmpl<mode>3
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "vec_logical")
(const_string "integer")))
(set (attr "length")
(if_then_else
@@ -6514,7 +6515,7 @@ (define_insn "mov<mode>_hardfloat"
mt%0 %1
mf%1 %0
nop"
- [(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*")
+ [(set_attr "type" "*,load,store,fpsimple,fpsimple,vec_logical,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*")
(set_attr "length" "4")])
(define_insn "*mov<mode>_softfloat"
@@ -6649,7 +6650,7 @@ (define_insn "*mov<mode>_hardfloat32"
#
#
#"
- [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,fpload,fpstore,vecsimple,vecsimple,two,store,load,two")
+ [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,vec_logical,vec_logical,two,store,load,two")
(set_attr "length" "4,4,4,4,4,4,4,4,4,8,8,8,8")])
(define_insn "*mov<mode>_softfloat32"
@@ -6694,7 +6695,7 @@ (define_insn "*mov<mode>_hardfloat64"
mffgpr %0,%1
mfvsrd %0,%x1
mtvsrd %x0,%1"
- [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,fpload,fpstore,vecsimple,vecsimple,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
+ [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,vec_logical,vec_logical,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
(set_attr "length" "4")])
(define_insn "*mov<mode>_softfloat64"
@@ -6905,7 +6906,7 @@ (define_insn_and_split "trunc<mode>df2_i
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_insn "trunc<mode>df2_internal2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
@@ -7138,7 +7139,7 @@ (define_insn "neg<mode>2_internal"
else
return \"fneg %0,%1\;fneg %L0,%L1\";
}"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "length" "8")])
(define_expand "abs<mode>2"
@@ -7273,7 +7274,7 @@ (define_insn "*ieee_128bit_vsx_neg<mode>
(use (match_operand:V16QI 2 "register_operand" "v"))]
"TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
"xxlxor %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vec_logical")])
;; IEEE 128-bit absolute value
(define_insn_and_split "ieee_128bit_vsx_abs<mode>2"
@@ -7302,7 +7303,7 @@ (define_insn "*ieee_128bit_vsx_abs<mode>
(use (match_operand:V16QI 2 "register_operand" "v"))]
"TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
"xxlandc %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vec_logical")])
;; IEEE 128-bit negative absolute value
(define_insn_and_split "*ieee_128bit_vsx_nabs<mode>2"
@@ -7335,7 +7336,7 @@ (define_insn "*ieee_128bit_vsx_nabs<mode
(use (match_operand:V16QI 2 "register_operand" "v"))]
"TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
"xxlor %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vec_logical")])
;; Float128 conversion functions. These expand to library function calls.
;; We use expand to convert from IBM double double to IEEE 128-bit
@@ -7491,7 +7492,7 @@ (define_insn "p8_fmrgow_<mode>"
UNSPEC_P8V_FMRGOW))]
"!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"fmrgow %0,%1,%2"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "fpsimple")])
(define_insn "p8_mtvsrwz"
[(set (match_operand:DF 0 "register_operand" "=d")
@@ -7743,9 +7744,9 @@ (define_insn "*movdi_internal32"
#
#"
[(set_attr "type"
- "store, load, *, fpstore, fpload, fp,
- *, fpstore, fpstore, fpload, fpload, vecsimple,
- vecsimple, vecsimple, vecsimple, vecsimple, vecsimple, vecsimple,
+ "store, load, *, fpstore, fpload, fpsimple,
+ *, fpstore, fpstore, fpload, fpload, vec_logical,
+ vecsimple, vecsimple, vecsimple, vec_logical, vec_logical, vecsimple,
vecsimple")])
(define_split
@@ -7829,11 +7830,11 @@ (define_insn "*movdi_internal64"
mfvsrd %0,%x1
mtvsrd %x0,%1"
[(set_attr "type"
- "store, load, *, *, *, *,
- fpstore, fpload, fp, fpstore, fpstore, fpload,
- fpload, vecsimple, vecsimple, vecsimple, vecsimple, vecsimple,
- vecsimple, vecsimple, vecsimple, mfjmpr, mtjmpr, *,
- mftgpr, mffgpr, mftgpr, mffgpr")
+ "store, load, *, *, *, *,
+ fpstore, fpload, fpsimple, fpstore, fpstore, fpload,
+ fpload, vec_logical, vecsimple, vecsimple, vecsimple, vec_logical,
+ vec_logical, vecsimple, vecsimple, mfjmpr, mtjmpr, *,
+ mftgpr, mffgpr, mftgpr, mffgpr")
(set_attr "length"
"4, 4, 4, 4, 4, 20,
@@ -13250,7 +13251,7 @@ (define_insn_and_split "pack<mode>"
operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
}
- [(set_attr "type" "fp,fp")
+ [(set_attr "type" "fpsimple,fp")
(set_attr "length" "4,8")])
(define_insn "unpack<mode>"
@@ -13352,7 +13353,7 @@ (define_insn "copysign<mode>3_hard"
UNSPEC_COPYSIGN))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscpsgnqp %0,%2,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecmove")])
(define_insn "copysign<mode>3_soft"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
@@ -13372,7 +13373,7 @@ (define_insn "neg<mode>2_hw"
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnegqp %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecmove")])
(define_insn "abs<mode>2_hw"
@@ -13381,7 +13382,7 @@ (define_insn "abs<mode>2_hw"
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsabsqp %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecmove")])
(define_insn "*nabs<mode>2_hw"
@@ -13391,7 +13392,7 @@ (define_insn "*nabs<mode>2_hw"
(match_operand:IEEE128 1 "altivec_register_operand" "v"))))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnabsqp %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecmove")])
;; Initially don't worry about doing fusion
(define_insn "*fma<mode>4_hw"
@@ -13461,7 +13462,7 @@ (define_insn_and_split "extendkftf2"
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "*,vecsimple")
+ [(set_attr "type" "*,vec_logical")
(set_attr "length" "0,4")])
(define_insn_and_split "trunctfkf2"
@@ -13477,7 +13478,7 @@ (define_insn_and_split "trunctfkf2"
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "*,vecsimple")
+ [(set_attr "type" "*,vec_logical")
(set_attr "length" "0,4")])
(define_insn "trunc<mode>df2_hw"
@@ -13613,7 +13614,7 @@ (define_insn "*ieee128_mfvsrd_64bit"
mfvsrd %0,%x1
stxsdx %x1,%y0
xxlor %x0,%x1,%x1"
- [(set_attr "type" "mftgpr,fpstore,vecsimple")])
+ [(set_attr "type" "mftgpr,fpstore,vec_logical")])
(define_insn "*ieee128_mfvsrd_32bit"
@@ -13624,7 +13625,7 @@ (define_insn "*ieee128_mfvsrd_32bit"
"@
stxsdx %x1,%y0
xxlor %x0,%x1,%x1"
- [(set_attr "type" "fpstore,vecsimple")])
+ [(set_attr "type" "fpstore,vec_logical")])
(define_insn "*ieee128_mfvsrwz"
[(set (match_operand:SI 0 "reg_or_indexed_operand" "=r,Z")
@@ -13660,7 +13661,7 @@ (define_insn "*ieee128_mtvsrd_64bit"
mtvsrd %x0,%1
lxsdx %x0,%y1
xxlor %x0,%x1,%x1"
- [(set_attr "type" "mffgpr,fpload,vecsimple")])
+ [(set_attr "type" "mffgpr,fpload,vec_logical")])
(define_insn "*ieee128_mtvsrd_32bit"
[(set (match_operand:V2DI 0 "altivec_register_operand" "=v,v")
@@ -13670,7 +13671,7 @@ (define_insn "*ieee128_mtvsrd_32bit"
"@
lxsdx %x0,%y1
xxlor %x0,%x1,%x1"
- [(set_attr "type" "fpload,vecsimple")])
+ [(set_attr "type" "fpload,vec_logical")])
;; IEEE 128-bit instructions with round to odd semantics
(define_insn "*trunc<mode>df2_odd"
Index: config/rs6000/a2.md
===================================================================
--- config/rs6000/a2.md (revision 237783)
+++ config/rs6000/a2.md (working copy)
@@ -81,7 +81,7 @@ (define_insn_reservation "ppca2-load" 5
;; D.8.1
(define_insn_reservation "ppca2-fp" 6
- (and (eq_attr "type" "fp") ;; Ignore fpsimple insn types (SPE only).
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppca2"))
"axu")
next prev parent reply other threads:[~2016-06-27 14:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-21 17:46 Pat Haugen
2016-06-22 19:11 ` Segher Boessenkool
2016-06-27 14:58 ` Pat Haugen [this message]
2016-06-27 20:45 ` Segher Boessenkool
2016-06-27 21:30 ` Pat Haugen
2016-06-27 21:44 ` Segher Boessenkool
2016-06-27 22:21 ` Pat Haugen
2016-06-27 22:43 ` Segher Boessenkool
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