From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 102140 invoked by alias); 26 Sep 2016 13:11:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 102126 invoked by uid 89); 26 Sep 2016 13:11:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=aprofile X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 26 Sep 2016 13:11:31 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 27E6C22E; Mon, 26 Sep 2016 06:11:30 -0700 (PDT) Received: from [10.2.206.221] (e108033-lin.cambridge.arm.com [10.2.206.221]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8A2013F21A; Mon, 26 Sep 2016 06:11:29 -0700 (PDT) Subject: Re: [PATCH 6/17][ARM] Add data processing intrinsics for float16_t. To: Ramana Radhakrishnan , Christophe Lyon References: <573B28A3.9030603@foss.arm.com> <573B2B5E.3000206@foss.arm.com> <57E8EDDB.3010008@foss.arm.com> Cc: gcc-patches From: Matthew Wahab Message-ID: <57E91E80.1090705@foss.arm.com> Date: Mon, 26 Sep 2016 13:19:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2016-09/txt/msg01823.txt.bz2 On 26/09/16 14:03, Ramana Radhakrishnan wrote: > On Mon, Sep 26, 2016 at 1:48 PM, Christophe Lyon > wrote: >> On 26 September 2016 at 11:43, Matthew Wahab wrote: >>> Hello, >>> >>> On 25/09/16 14:00, Christophe Lyon wrote: >>>>>> >>>>>> >>>>>> This patch adds the new intrinsics: >>>>>> vbsl_f16, vbslq_f16, vdup_n_f16, vdupq_n_f16, vdup_lane_f16, >>>>>> vdupq_lane_f16, vext_f16, vextq_f16, vmov_n_f16, vmovq_n_f16, >>>>>> vrev64_f16, vrev64q_f16, vtrn_f16, vtrnq_f16, vuzp_f16, vuzpq_f16, >>>>>> vzip_f16, vzipq_f16. >>>>>> >>>>>> This patch also updates the advsimd-intrinsics testsuite to test the f16 >>>>>> variants for ARM targets. These intrinsics are only implemented in the >>>>>> ARM target so the tests are disabled for AArch64 using an extra >>>>>> condition on a new convenience macro FP16_SUPPORTED. This patch also >>>>>> disables, for the ARM target, the testsuite defined macro vdup_n_f16 as >>>>>> it is no longer needed. >>>> >>>> >>>> Since you committed this patch, I've noticed that libgcc fails to build >>>> when GCC is configured: >>>> --target arm-none-eabi and default cpu >>>> /tmp/9649048_29.tmpdir/ccuBwQJJ.s: Assembler messages: >>>> /tmp/9649048_29.tmpdir/ccuBwQJJ.s:64: Error: selected processor does >>>> not support ARM mode `movwlt r0,32768' >>>> /tmp/9649048_29.tmpdir/ccuBwQJJ.s:65: Error: selected processor does >>>> not support ARM mode `movwge r0,32767' >>>> make[4]: *** [_ssaddHQ.o] Error 1 >>>> make[4]: Leaving directory >>>> >>>> `/tmp/9649048_29.tmpdir/aci-gcc-fsf/builds/gcc-fsf-gccsrc/obj-arm-none-eabi/gcc1/arm-none-eabi/fpu/libgcc' >>>> >>> >>> >>> I can't reproduce the failure, could you send the configure arguments for >>> the build. >>> >> >> If I'm not mistaken, that is: >> --target=arm-none-eabi --disable-nls --disable-libgomp >> --disable-libmudflap --disable-libcilkrts --enable-checking >> --enable-languages=c,c++ --with-newlib >> >> Maybe you've disabled multilibs? > > > I'm pretty sure I built this as part of reviewing all these patches > with --with-mutlib-list=aprofile and didnt' see any failures. Not sure > what's going on here. > I think the problem is that the new patterns use MOVW, which is a Thumb-2 instruction, but don't check for Thumb-2 support in the target. I'm testing a patch to fix this. Matthew