From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 122687 invoked by alias); 11 Nov 2016 16:19:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 122666 invoked by uid 89); 11 Nov 2016 16:19:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.8 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=CC'ing, cc'ing X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 11 Nov 2016 16:19:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E114D16; Fri, 11 Nov 2016 08:19:35 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2B97D3F24D; Fri, 11 Nov 2016 08:19:35 -0800 (PST) Message-ID: <5825EF95.2090109@foss.arm.com> Date: Fri, 11 Nov 2016 16:19:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "Andre Vieira (lists)" , gcc-patches@gcc.gnu.org CC: Ramana Radhakrishnan , Richard Earnshaw Subject: Re: [PATCHv2 6/7, GCC, ARM, V8M] ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_call References: <5796116C.6010100@arm.com> <57961383.7090709@arm.com> <57BD7E9E.6090906@arm.com> <580F8889.6080602@arm.com> <5811D05D.4070909@arm.com> <58233880.4010002@arm.com> <5825B0E8.1020803@foss.arm.com> <5825EE96.5050402@arm.com> <5825EF71.8030307@foss.arm.com> In-Reply-To: <5825EF71.8030307@foss.arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2016-11/txt/msg01136.txt.bz2 And CC'ing Ramana and Richard this time... On 11/11/16 16:18, Kyrill Tkachov wrote: > > On 11/11/16 16:15, Andre Vieira (lists) wrote: >>> Why are you writing 1.0 to clear the register? I think you want >>> CONST0_RTX (DFmode) >>> and CONST0_RTX (SFmode). >>> >>> Also, in this function when you iterate from regno = 0 up to some >>> number, please use >>> regno = R0_REGNUM (minor nit). >>> >>> Thanks, >>> Kyrill >>> >>> >> Hi Kyrill, >> >> So you got me thinking there. I couldn't quite remember why I had chosen >> 1.0 rather than 0 to clear the FP registers. I now know it is because >> vmov (immediate) will not take 0.0, it does take 1.0. > > Ah, you're right (I checked it too). > >> I made the other >> changes you suggested and changed the vmovs in the library function >> wrapper back to #1.0. I also removed the second register for the single >> precision FP clearing, since the vmov from two general registers to two >> single precision registers can take the same general register twice, >> saving on a mov. There is a discrepancy there with the way I clear other >> FP registers, there I do use 0, since I'd need two moves(or a move and a >> shift) to encode 1.0 into a general purpose register, so I made a >> conscious choice of performance over consistency there. > > Hmm, I'll defer to Ramana or Richard on whether we should keep consistent between SP and DP > in libgcc/config/arm/cmse_nonsecure_call.S. > Otherwise the patch looks good to me. > Until this patch is approved by an arm maintainer can you please do a bootstrap and regtest > on an arm-none-linux-gnueabihf target of all the patches in the series. > > Thanks, > Kyrill >> Again no changes to ChangeLog. >> >> Cheers, >> Andre >