* [PATCH 00/14] rs6000: Delete SPE things
@ 2017-06-06 15:56 Segher Boessenkool
2017-06-06 15:57 ` [PATCH 03/14] rs6000: Remove -mfloat-gprs Segher Boessenkool
` (13 more replies)
0 siblings, 14 replies; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:56 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This series removes most SPE things.
Tested (all languages) on powerpc64-linux (power7, {-m32,-m64}); on
powerpc64le-linux (power8, all languages); on AIX (power7, default
languages); on powerpc-linux (compile only) and on powerpc-linux-gnuspe
(compile only).
Is this okay for trunk?
Segher
Segher Boessenkool (14):
rs6000: Remove TARGET_FPRS
rs6000: Remove TARGET_E500_{SINGLE,DOUBLE}
rs6000: Remove -mfloat-gprs
rs6000: Remove rs6000_cbranch_operator
rs6000: Remove output_e500_flip_gt_bit
rs6000: Remove UNSPEC_MV_CR_GT
rs6000: Remove TARGET_SPE and TARGET_SPE_ABI and friends
rs6000: Remove -mspe options
rs6000: Remove reg_or_none500mem_operand
rs6000: Remove spe.md, spe.h, linuxspe.h
rs6000: Remove type attribute "brinc"
rs6000: Remove SPE high registers
rs6000: Remove spe_acc and spefscr
rs6000: Remove rs6000_nonimmediate_operand
gcc/common/config/rs6000/rs6000-common.c | 9 -
gcc/config.gcc | 4 +-
gcc/config/rs6000/8540.md | 6 -
gcc/config/rs6000/darwin.h | 7 +-
gcc/config/rs6000/darwin.md | 16 +-
gcc/config/rs6000/dfp.md | 48 +-
gcc/config/rs6000/e500.h | 45 -
gcc/config/rs6000/e500mc.md | 6 -
gcc/config/rs6000/e500mc64.md | 6 -
gcc/config/rs6000/linuxspe.h | 32 -
gcc/config/rs6000/paired.md | 12 +-
gcc/config/rs6000/predicates.md | 87 +-
gcc/config/rs6000/rs6000-builtin.def | 313 +--
gcc/config/rs6000/rs6000-c.c | 18 +-
gcc/config/rs6000/rs6000-protos.h | 2 -
gcc/config/rs6000/rs6000.c | 1956 +----------------
gcc/config/rs6000/rs6000.h | 235 +-
gcc/config/rs6000/rs6000.md | 354 +--
gcc/config/rs6000/rs6000.opt | 40 -
gcc/config/rs6000/spe.h | 1107 ----------
gcc/config/rs6000/spe.md | 3512 ------------------------------
gcc/config/rs6000/t-rs6000 | 1 -
gcc/config/rs6000/t-rtems | 9 +-
gcc/config/rs6000/vector.md | 95 -
gcc/config/rs6000/vsx.md | 2 +-
gcc/doc/tm.texi | 2 -
gcc/doc/tm.texi.in | 2 -
27 files changed, 305 insertions(+), 7621 deletions(-)
delete mode 100644 gcc/config/rs6000/e500.h
delete mode 100644 gcc/config/rs6000/linuxspe.h
delete mode 100644 gcc/config/rs6000/spe.h
delete mode 100644 gcc/config/rs6000/spe.md
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 04/14] rs6000: Remove rs6000_cbranch_operator
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
2017-06-06 15:57 ` [PATCH 03/14] rs6000: Remove -mfloat-gprs Segher Boessenkool
2017-06-06 15:57 ` [PATCH 02/14] rs6000: Remove TARGET_E500_{SINGLE,DOUBLE} Segher Boessenkool
@ 2017-06-06 15:57 ` Segher Boessenkool
2017-06-06 17:01 ` David Edelsohn
2017-06-06 15:57 ` [PATCH 05/14] rs6000: Remove output_e500_flip_gt_bit Segher Boessenkool
` (10 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:57 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
rs6000_cbranch_operator now is just comparison_operator, so just use
that directly.
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/predicated.md (rs6000_cbranch_operator): Delete.
* config/rs6000/rs6000.md: Replace rs6000_cbranch_operator by
comparison_operator.
---
gcc/config/rs6000/predicates.md | 4 ----
gcc/config/rs6000/rs6000.md | 8 ++++----
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index dd961a7..11aecbd 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1238,10 +1238,6 @@ (define_predicate "branch_comparison_operator"
GET_MODE (XEXP (op, 0))),
1"))))
-;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
-(define_predicate "rs6000_cbranch_operator"
- (match_operand 0 "comparison_operator"))
-
;; Return 1 if OP is an unsigned comparison operator.
(define_predicate "unsigned_comparison_operator"
(match_code "ltu,gtu,leu,geu"))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index efca26c..108ad8f 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11430,7 +11430,7 @@ (define_insn "probe_stack_range<P:mode>"
;; insns, and branches.
(define_expand "cbranch<mode>4"
- [(use (match_operator 0 "rs6000_cbranch_operator"
+ [(use (match_operator 0 "comparison_operator"
[(match_operand:GPR 1 "gpc_reg_operand" "")
(match_operand:GPR 2 "reg_or_short_operand" "")]))
(use (match_operand 3 ""))]
@@ -11453,7 +11453,7 @@ (define_expand "cbranch<mode>4"
}")
(define_expand "cbranch<mode>4"
- [(use (match_operator 0 "rs6000_cbranch_operator"
+ [(use (match_operator 0 "comparison_operator"
[(match_operand:FP 1 "gpc_reg_operand" "")
(match_operand:FP 2 "gpc_reg_operand" "")]))
(use (match_operand 3 ""))]
@@ -11683,7 +11683,7 @@ (define_expand "cstore<mode>4_unsigned_imm"
})
(define_expand "cstore<mode>4"
- [(use (match_operator 1 "rs6000_cbranch_operator"
+ [(use (match_operator 1 "comparison_operator"
[(match_operand:GPR 2 "gpc_reg_operand")
(match_operand:GPR 3 "reg_or_short_operand")]))
(clobber (match_operand:GPR 0 "gpc_reg_operand"))]
@@ -11746,7 +11746,7 @@ (define_expand "cstore<mode>4"
})
(define_expand "cstore<mode>4"
- [(use (match_operator 1 "rs6000_cbranch_operator"
+ [(use (match_operator 1 "comparison_operator"
[(match_operand:FP 2 "gpc_reg_operand")
(match_operand:FP 3 "gpc_reg_operand")]))
(clobber (match_operand:SI 0 "gpc_reg_operand"))]
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 05/14] rs6000: Remove output_e500_flip_gt_bit
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
` (2 preceding siblings ...)
2017-06-06 15:57 ` [PATCH 04/14] rs6000: Remove rs6000_cbranch_operator Segher Boessenkool
@ 2017-06-06 15:57 ` Segher Boessenkool
2017-06-06 17:02 ` David Edelsohn
2017-06-06 15:57 ` [PATCH 01/14] rs6000: Remove TARGET_FPRS Segher Boessenkool
` (9 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:57 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000-protos.h (output_e500_flip_gt_bit): Delete.
* config/rs6000/rs6000.c: Ditto.
---
gcc/config/rs6000/rs6000-protos.h | 1 -
gcc/config/rs6000/rs6000.c | 18 ------------------
2 files changed, 19 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 0344823..2955d97 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -133,7 +133,6 @@ extern void rs6000_emit_sISEL (machine_mode, rtx[]);
extern void rs6000_emit_sCOND (machine_mode, rtx[]);
extern void rs6000_emit_cbranch (machine_mode, rtx[]);
extern char * output_cbranch (rtx, const char *, int, rtx_insn *);
-extern char * output_e500_flip_gt_bit (rtx, rtx);
extern const char * output_probe_stack_range (rtx, rtx);
extern bool rs6000_emit_set_const (rtx, rtx);
extern int rs6000_emit_cmove (rtx, rtx, rtx, rtx);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1ad08d0..a31c608 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -24987,24 +24987,6 @@ output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
return string;
}
-/* Return the string to flip the GT bit on a CR. */
-char *
-output_e500_flip_gt_bit (rtx dst, rtx src)
-{
- static char string[64];
- int a, b;
-
- gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
- && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
-
- /* GT bit. */
- a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
- b = 4 * (REGNO (src) - CR0_REGNO) + 1;
-
- sprintf (string, "crnot %d,%d", a, b);
- return string;
-}
-
/* Return insn for VSX or Altivec comparisons. */
static rtx
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 02/14] rs6000: Remove TARGET_E500_{SINGLE,DOUBLE}
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
2017-06-06 15:57 ` [PATCH 03/14] rs6000: Remove -mfloat-gprs Segher Boessenkool
@ 2017-06-06 15:57 ` Segher Boessenkool
2017-06-06 17:00 ` David Edelsohn
2017-06-06 15:57 ` [PATCH 04/14] rs6000: Remove rs6000_cbranch_operator Segher Boessenkool
` (11 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:57 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
Similarly, TARGET_E500_{SINGLE,DOUBLE} is always false now.
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/predicates.md: Replace TARGET_E500_DOUBLE and
TARGET_E500_SINGLE by 0, simplify.
* config/rs6000/rs6000.c: Ditto.
(rs6000_option_override_internal): Delete CHECK_E500_OPTIONS.
(spe_build_register_parallel): Delete.
* config/rs6000/rs6000.h: Delete TARGET_E500_SINGLE,
TARGET_E500_DOUBLE, and CHECK_E500_OPTIONS.
* config/rs6000/rs6000.md: Replace TARGET_E500_DOUBLE,
TARGET_E500_SINGLE, and <E500_CONVERT> by 0, simplify.
(E500_CONVERT): Delete.
* config/rs6000/spe.md: Remove many patterns and all define_constants.
---
gcc/config/rs6000/predicates.md | 19 +-
gcc/config/rs6000/rs6000.c | 188 +------------
gcc/config/rs6000/rs6000.h | 11 +-
gcc/config/rs6000/rs6000.md | 73 ++---
gcc/config/rs6000/spe.md | 589 ++--------------------------------------
5 files changed, 60 insertions(+), 820 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index a9bf854..dd961a7 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -299,7 +299,7 @@ (define_predicate "const_0_to_15_operand"
(define_predicate "gpc_reg_operand"
(match_operand 0 "register_operand")
{
- if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
+ if (TARGET_SPE && invalid_e500_subreg (op, mode))
return 0;
if (GET_CODE (op) == SUBREG)
@@ -331,7 +331,7 @@ (define_predicate "gpc_reg_operand"
(define_predicate "int_reg_operand"
(match_operand 0 "register_operand")
{
- if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
+ if (TARGET_SPE && invalid_e500_subreg (op, mode))
return 0;
if (GET_CODE (op) == SUBREG)
@@ -357,7 +357,7 @@ (define_predicate "int_reg_operand"
(define_predicate "int_reg_operand_not_pseudo"
(match_operand 0 "register_operand")
{
- if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
+ if (TARGET_SPE && invalid_e500_subreg (op, mode))
return 0;
if (GET_CODE (op) == SUBREG)
@@ -606,7 +606,7 @@ (define_predicate "easy_fp_constant"
return 0;
/* Consider all constants with -msoft-float to be easy. */
- if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
+ if ((TARGET_SOFT_FLOAT
|| (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
&& mode != DImode)
return 1;
@@ -1014,10 +1014,9 @@ (define_predicate "reg_or_mem_operand"
;; Return 1 if the operand is either an easy FP constant or memory or reg.
(define_predicate "reg_or_none500mem_operand"
(if_then_else (match_code "mem")
- (and (match_test "!TARGET_E500_DOUBLE")
- (ior (match_operand 0 "memory_operand")
- (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
- (match_operand 0 "volatile_mem_operand"))))
+ (ior (match_operand 0 "memory_operand")
+ (match_test "macho_lo_sum_memory_operand (op, mode)")
+ (match_operand 0 "volatile_mem_operand"))
(match_operand 0 "gpc_reg_operand")))
;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
@@ -1137,7 +1136,7 @@ (define_predicate "input_operand"
return 1;
/* Do not allow invalid E500 subregs. */
- if ((TARGET_E500_DOUBLE || TARGET_SPE)
+ if (TARGET_SPE
&& GET_CODE (op) == SUBREG
&& invalid_e500_subreg (op, mode))
return 0;
@@ -1205,7 +1204,7 @@ (define_predicate "splat_input_operand"
(define_predicate "rs6000_nonimmediate_operand"
(match_code "reg,subreg,mem")
{
- if ((TARGET_E500_DOUBLE || TARGET_SPE)
+ if (TARGET_SPE
&& GET_CODE (op) == SUBREG
&& invalid_e500_subreg (op, mode))
return 0;
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 4a37a58..8d578f4 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2038,15 +2038,6 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
else if (ALTIVEC_REGNO_P (regno))
reg_size = UNITS_PER_ALTIVEC_WORD;
- /* The value returned for SCmode in the E500 double case is 2 for
- ABI compatibility; storing an SCmode value in a single register
- would require function_arg and rs6000_spe_function_arg to handle
- SCmode so as to pass the value correctly in a pair of
- registers. */
- else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
- && !DECIMAL_FLOAT_MODE_P (mode) && SPE_SIMD_REGNO_P (regno))
- reg_size = UNITS_PER_FP_WORD;
-
else
reg_size = UNITS_PER_WORD;
@@ -2818,12 +2809,6 @@ rs6000_debug_reg_global (void)
fprintf (stderr, DEBUG_FMT_S, "soft_float",
(TARGET_SOFT_FLOAT ? "true" : "false"));
- fprintf (stderr, DEBUG_FMT_S, "e500_single",
- (TARGET_E500_SINGLE ? "true" : "false"));
-
- fprintf (stderr, DEBUG_FMT_S, "e500_double",
- (TARGET_E500_DOUBLE ? "true" : "false"));
-
if (TARGET_LINK_STACK)
fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
@@ -2945,8 +2930,7 @@ rs6000_setup_reg_addr_masks (void)
&& !complex_p
&& !small_int_vsx_p
&& (m2 != DFmode || !TARGET_UPPER_REGS_DF)
- && (m2 != SFmode || !TARGET_UPPER_REGS_SF)
- && !(TARGET_E500_DOUBLE && msize == 8))
+ && (m2 != SFmode || !TARGET_UPPER_REGS_SF))
{
addr_mask |= RELOAD_REG_PRE_INCDEC;
@@ -3694,9 +3678,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
}
}
- if (TARGET_E500_DOUBLE)
- rs6000_class_max_nregs[DFmode][GENERAL_REGS] = 1;
-
/* Calculate which modes to automatically generate code to use a the
reciprocal divide and square root instructions. In the future, possibly
automatically generate the instructions even if the user did not specify
@@ -5103,8 +5084,8 @@ rs6000_option_override_internal (bool global_init_p)
case PROCESSOR_PPCE5500:
case PROCESSOR_PPCE6500:
- rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
- rs6000_double_float = TARGET_E500_DOUBLE;
+ rs6000_single_float = 0;
+ rs6000_double_float = 0;
rs6000_isa_flags &= ~OPTION_MASK_STRING;
@@ -5128,9 +5109,6 @@ rs6000_option_override_internal (bool global_init_p)
"point");
}
- /* Detect invalid option combinations with E500. */
- CHECK_E500_OPTIONS;
-
rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
&& rs6000_cpu != PROCESSOR_POWER5
&& rs6000_cpu != PROCESSOR_POWER6
@@ -8188,36 +8166,6 @@ rs6000_split_v4si_init (rtx operands[])
bool
invalid_e500_subreg (rtx op, machine_mode mode)
{
- if (TARGET_E500_DOUBLE)
- {
- /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
- subreg:TI and reg:TF. Decimal float modes are like integer
- modes (only low part of each register used) for this
- purpose. */
- if (GET_CODE (op) == SUBREG
- && (mode == SImode || mode == DImode || mode == TImode
- || mode == DDmode || mode == TDmode || mode == PTImode)
- && REG_P (SUBREG_REG (op))
- && (GET_MODE (SUBREG_REG (op)) == DFmode
- || GET_MODE (SUBREG_REG (op)) == TFmode
- || GET_MODE (SUBREG_REG (op)) == IFmode
- || GET_MODE (SUBREG_REG (op)) == KFmode))
- return true;
-
- /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
- reg:TI. */
- if (GET_CODE (op) == SUBREG
- && (mode == DFmode || mode == TFmode || mode == IFmode
- || mode == KFmode)
- && REG_P (SUBREG_REG (op))
- && (GET_MODE (SUBREG_REG (op)) == DImode
- || GET_MODE (SUBREG_REG (op)) == TImode
- || GET_MODE (SUBREG_REG (op)) == PTImode
- || GET_MODE (SUBREG_REG (op)) == DDmode
- || GET_MODE (SUBREG_REG (op)) == TDmode))
- return true;
- }
-
if (TARGET_SPE
&& GET_CODE (op) == SUBREG
&& mode == SImode
@@ -8248,13 +8196,6 @@ rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
else if (align < 128)
align = 128;
}
- else if (TARGET_E500_DOUBLE
- && TREE_CODE (type) == REAL_TYPE
- && TYPE_MODE (type) == DFmode)
- {
- if (align < 64)
- align = 64;
- }
}
if (how != align_abi)
@@ -8908,14 +8849,6 @@ rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
case DFmode:
case DDmode:
case DImode:
- /* On e500v2, we may have:
-
- (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
-
- Which gets addressed with evldd instructions. */
- if (TARGET_E500_DOUBLE)
- return SPE_CONST_OFFSET_OK (offset);
-
/* If we are using VSX scalar loads, restrict ourselves to reg+reg
addressing. */
if (VECTOR_MEM_VSX_P (mode))
@@ -8935,10 +8868,6 @@ rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
case TDmode:
case TImode:
case PTImode:
- if (TARGET_E500_DOUBLE)
- return (SPE_CONST_OFFSET_OK (offset)
- && SPE_CONST_OFFSET_OK (offset + 8));
-
extra = 8;
if (!worst_case)
break;
@@ -9027,9 +8956,6 @@ legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
/* quad word addresses are restricted, and we can't use LO_SUM. */
if (mode_supports_vsx_dform_quad (mode))
return false;
- /* Restrict addressing for DI because of our SUBREG hackery. */
- if (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
- return false;
x = XEXP (x, 1);
if (TARGET_ELF || TARGET_MACHO)
@@ -9146,8 +9072,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
>= 0x10000 - extra)
- && !(SPE_VECTOR_MODE (mode)
- || (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)))
+ && !SPE_VECTOR_MODE (mode))
{
HOST_WIDE_INT high_int, low_int;
rtx sum;
@@ -9172,8 +9097,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
return gen_rtx_PLUS (Pmode, XEXP (x, 0),
force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
}
- else if (SPE_VECTOR_MODE (mode)
- || (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD))
+ else if (SPE_VECTOR_MODE (mode))
{
if (mode == DImode)
return x;
@@ -9937,7 +9861,6 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode,
&& CONST_INT_P (XEXP (x, 1))
&& reg_offset_p
&& !SPE_VECTOR_MODE (mode)
- && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
&& (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
{
HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
@@ -10196,8 +10119,7 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
if (!FLOAT128_2REG_P (mode)
&& ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
|| TARGET_POWERPC64
- || (mode != DFmode && mode != DDmode)
- || (TARGET_E500_DOUBLE && mode != DDmode))
+ || (mode != DFmode && mode != DDmode))
&& (TARGET_POWERPC64 || mode != DImode)
&& (mode != TImode || VECTOR_MEM_VSX_P (TImode))
&& mode != PTImode
@@ -11385,10 +11307,9 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
fit into 1, whereas DI still needs two. */
static bool
-rs6000_member_type_forces_blk (const_tree field, machine_mode mode)
+rs6000_member_type_forces_blk (const_tree field, machine_mode)
{
- return ((TARGET_SPE && TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
- || (TARGET_E500_DOUBLE && mode == DFmode));
+ return (TARGET_SPE && TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE);
}
\f
/* Nonzero if we can use a floating-point register to pass this arg. */
@@ -12503,42 +12424,6 @@ rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
0);
}
-static rtx
-spe_build_register_parallel (machine_mode mode, int gregno)
-{
- rtx r1, r3, r5, r7;
-
- switch (mode)
- {
- case DFmode:
- r1 = gen_rtx_REG (DImode, gregno);
- r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
- return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
-
- case DCmode:
- case TFmode:
- r1 = gen_rtx_REG (DImode, gregno);
- r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
- r3 = gen_rtx_REG (DImode, gregno + 2);
- r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
- return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
-
- case TCmode:
- r1 = gen_rtx_REG (DImode, gregno);
- r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
- r3 = gen_rtx_REG (DImode, gregno + 2);
- r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
- r5 = gen_rtx_REG (DImode, gregno + 4);
- r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
- r7 = gen_rtx_REG (DImode, gregno + 6);
- r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
- return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
-
- default:
- gcc_unreachable ();
- }
-}
-
/* Determine where to put a SIMD argument on the SPE. */
static rtx
rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, machine_mode mode,
@@ -12546,23 +12431,6 @@ rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, machine_mode mode,
{
int gregno = cum->sysv_gregno;
- /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
- are passed and returned in a pair of GPRs for ABI compatibility. */
- if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
- || mode == DCmode || mode == TCmode))
- {
- int n_words = rs6000_arg_size (mode, type);
-
- /* Doubles go in an odd/even register pair (r5/r6, etc). */
- if (mode == DFmode)
- gregno += (1 - gregno) & 1;
-
- /* Multi-reg args are not split between registers and stack. */
- if (gregno + n_words - 1 > GP_ARG_MAX_REG)
- return NULL_RTX;
-
- return spe_build_register_parallel (mode, gregno);
- }
if (cum->stdarg)
{
int n_words = rs6000_arg_size (mode, type);
@@ -13055,12 +12923,7 @@ rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
}
}
- else if (TARGET_SPE_ABI && TARGET_SPE
- && (SPE_VECTOR_MODE (mode)
- || (TARGET_E500_DOUBLE && (mode == DFmode
- || mode == DCmode
- || mode == TFmode
- || mode == TCmode))))
+ else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
return rs6000_spe_function_arg (cum, mode, type);
else if (abi == ABI_V4)
@@ -23232,16 +23095,6 @@ rs6000_cannot_change_mode_class (machine_mode from,
return false;
}
- if (TARGET_E500_DOUBLE
- && ((((to) == DFmode) + ((from) == DFmode)) == 1
- || (((to) == TFmode) + ((from) == TFmode)) == 1
- || (((to) == IFmode) + ((from) == IFmode)) == 1
- || (((to) == KFmode) + ((from) == KFmode)) == 1
- || (((to) == DDmode) + ((from) == DDmode)) == 1
- || (((to) == TDmode) + ((from) == TDmode)) == 1
- || (((to) == DImode) + ((from) == DImode)) == 1))
- return true;
-
/* Since the VSX register set includes traditional floating point registers
and altivec registers, just check for the size being different instead of
trying to check whether the modes are vector modes. Otherwise it won't
@@ -24102,7 +23955,7 @@ print_operand (FILE *file, rtx x, int code)
tmp = XEXP (x, 0);
/* Ugly hack because %y is overloaded. */
- if ((TARGET_SPE || TARGET_E500_DOUBLE)
+ if (TARGET_SPE
&& (GET_MODE_SIZE (GET_MODE (x)) == 8
|| FLOAT128_2REG_P (GET_MODE (x))
|| GET_MODE (x) == TImode
@@ -26444,8 +26297,6 @@ rs6000_split_multireg_move (rtx dst, rtx src)
((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
else if (ALTIVEC_REGNO_P (reg))
reg_mode = V16QImode;
- else if (TARGET_E500_DOUBLE && FLOAT128_2REG_P (mode))
- reg_mode = DFmode;
else
reg_mode = word_mode;
reg_mode_size = GET_MODE_SIZE (reg_mode);
@@ -27566,9 +27417,6 @@ spe_func_has_64bit_regs_p (void)
if (SPE_VECTOR_MODE (mode))
return true;
- if (TARGET_E500_DOUBLE
- && (mode == DFmode || FLOAT128_2REG_P (mode)))
- return true;
}
}
}
@@ -28517,7 +28365,6 @@ emit_frame_save (rtx frame_reg, machine_mode mode,
/* Some cases that need register indexed addressing. */
gcc_checking_assert (!((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
|| (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
- || (TARGET_E500_DOUBLE && mode == DFmode)
|| (TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode)
&& !SPE_CONST_OFFSET_OK (offset))));
@@ -28538,8 +28385,7 @@ gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
int_rtx = GEN_INT (offset);
- if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode) && !SPE_CONST_OFFSET_OK (offset))
- || (TARGET_E500_DOUBLE && mode == DFmode))
+ if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode) && !SPE_CONST_OFFSET_OK (offset))
{
offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
emit_move_insn (offset_rtx, int_rtx);
@@ -38644,10 +38490,6 @@ rs6000_function_value (const_tree valtype,
&& TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode))
regno = ALTIVEC_ARG_RETURN;
- else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
- && (mode == DFmode || mode == DCmode
- || FLOAT128_IBM_P (mode) || mode == TCmode))
- return spe_build_register_parallel (mode, GP_ARG_RETURN);
else
regno = GP_ARG_RETURN;
@@ -38680,10 +38522,6 @@ rs6000_libcall_value (machine_mode mode)
regno = ALTIVEC_ARG_RETURN;
else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
return rs6000_complex_function_value (mode);
- else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
- && (mode == DFmode || mode == DCmode
- || FLOAT128_IBM_P (mode) || mode == TCmode))
- return spe_build_register_parallel (mode, GP_ARG_RETURN);
else
regno = GP_ARG_RETURN;
@@ -38786,9 +38624,7 @@ rs6000_dwarf_register_span (rtx reg)
if (TARGET_SPE
&& regno < 32
- && (SPE_VECTOR_MODE (GET_MODE (reg))
- || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
- && mode != SFmode && mode != SDmode && mode != SCmode)))
+ && SPE_VECTOR_MODE (GET_MODE (reg)))
;
else
return NULL_RTX;
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index dec1ab7..66f8170 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -572,9 +572,6 @@ extern int rs6000_vector_align[];
#define TARGET_SPE_ABI 0
#define TARGET_SPE 0
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
-#define TARGET_E500_SINGLE 0
-#define TARGET_E500_DOUBLE 0
-#define CHECK_E500_OPTIONS do { } while (0)
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines or
@@ -1276,13 +1273,9 @@ enum data_align { align_abi, align_opt, align_both };
&& ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
&& FP_REGNO_P (REGNO) \
? V2DFmode \
- : TARGET_E500_DOUBLE && (MODE) == SImode \
- ? SImode \
- : TARGET_E500_DOUBLE && ((MODE) == VOIDmode || (MODE) == DFmode) \
+ : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
? DFmode \
- : !TARGET_E500_DOUBLE && FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
- ? DFmode \
- : !TARGET_E500_DOUBLE && (MODE) == TDmode && FP_REGNO_P (REGNO) \
+ : (MODE) == TDmode && FP_REGNO_P (REGNO) \
? DImode \
: choose_hard_reg_mode ((REGNO), (NREGS), false))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 210077d..efca26c 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -372,8 +372,8 @@ (define_mode_iterator TI2 [TI PTI])
; Any hardware-supported floating-point mode
(define_mode_iterator FP [
- (SF "TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT || TARGET_E500_SINGLE)")
- (DF "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)")
+ (SF "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT")
+ (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
(TF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
(IF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
(KF "TARGET_FLOAT128_TYPE")
@@ -454,8 +454,7 @@ (define_mode_attr f64_av [(DF "wv") (DD "wn")])
(define_mode_attr f64_p9 [(DF "wb") (DD "wn")])
; These modes do not fit in integer registers in 32-bit mode.
-; but on e500v2, the gpr are 64 bit registers
-(define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
+(define_mode_iterator DIFD [DI DF DD])
; Iterator for reciprocal estimate instructions
(define_mode_iterator RECIPF [SF DF V4SF V2DF])
@@ -614,9 +613,6 @@ (define_mode_attr rreg2 [(SF "f")
(define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
(DF "TARGET_FCFID")])
-(define_mode_attr E500_CONVERT [(SF "0")
- (DF "TARGET_E500_DOUBLE")])
-
(define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
(DF "TARGET_DOUBLE_FLOAT")])
@@ -4646,7 +4642,7 @@ (define_insn "*cmp<mode>_fpr"
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand")
(float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand")))]
- "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
if (HONOR_SNANS (SFmode))
operands[1] = force_reg (SFmode, operands[1]);
@@ -4684,7 +4680,7 @@ (define_insn "*extendsfdf2_snan"
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"")
(define_insn "*truncdfsf2_fpr"
@@ -5258,17 +5254,10 @@ (define_expand "floatsidf2"
(clobber (match_dup 4))
(clobber (match_dup 5))
(clobber (match_dup 6))])]
- "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
- if (TARGET_E500_DOUBLE)
- {
- if (!REG_P (operands[1]))
- operands[1] = force_reg (SImode, operands[1]);
- emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
- DONE;
- }
- else if (TARGET_LFIWAX && TARGET_FCFID)
+ if (TARGET_LFIWAX && TARGET_FCFID)
{
emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
DONE;
@@ -5359,17 +5348,10 @@ (define_expand "floatunssidf2"
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
- "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
- if (TARGET_E500_DOUBLE)
- {
- if (!REG_P (operands[1]))
- operands[1] = force_reg (SImode, operands[1]);
- emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
- DONE;
- }
- else if (TARGET_LFIWZX && TARGET_FCFID)
+ if (TARGET_LFIWZX && TARGET_FCFID)
{
emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
DONE;
@@ -5532,10 +5514,10 @@ (define_insn_and_split "*floatuns<QHI:mode><FP_ISA3:mode>2_internal"
(define_expand "fix_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && (<TARGET_FLOAT> || <E500_CONVERT>)"
+ "TARGET_HARD_FLOAT && <TARGET_FLOAT>"
"
{
- if (!<E500_CONVERT> && !TARGET_VSX_SMALL_INTEGER)
+ if (!TARGET_VSX_SMALL_INTEGER)
{
rtx src = force_reg (<MODE>mode, operands[1]);
@@ -5680,11 +5662,10 @@ (define_insn_and_split "*fix_trunc<SFDF:mode><QHI:mode>2_internal"
(define_expand "fixuns_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT
- && ((<TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX) || <E500_CONVERT>)"
+ "TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX"
"
{
- if (!<E500_CONVERT> && !TARGET_VSX_SMALL_INTEGER)
+ if (!TARGET_VSX_SMALL_INTEGER)
{
emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
DONE;
@@ -7432,8 +7413,7 @@ (define_insn "*mov<mode>_softfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
(match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
"! TARGET_POWERPC64
- && (TARGET_SINGLE_FLOAT || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
- || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
+ && (TARGET_SINGLE_FLOAT || TARGET_SOFT_FLOAT)
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"#"
@@ -7565,11 +7545,6 @@ (define_expand "extenddf<mode>2"
{
if (FLOAT128_IEEE_P (<MODE>mode))
rs6000_expand_float128_convert (operands[0], operands[1], false);
- else if (TARGET_E500_DOUBLE)
- {
- gcc_assert (<MODE>mode == TFmode);
- emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
- }
else if (TARGET_VSX)
{
if (<MODE>mode == TFmode)
@@ -7693,11 +7668,6 @@ (define_expand "trunc<mode>sf2"
{
if (FLOAT128_IEEE_P (<MODE>mode))
rs6000_expand_float128_convert (operands[0], operands[1], false);
- else if (TARGET_E500_DOUBLE)
- {
- gcc_assert (<MODE>mode == TFmode);
- emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
- }
else if (<MODE>mode == TFmode)
emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
else if (<MODE>mode == IFmode)
@@ -7777,8 +7747,6 @@ (define_expand "fix_trunc<mode>si2"
{
if (FLOAT128_IEEE_P (<MODE>mode))
rs6000_expand_float128_convert (op0, op1, false);
- else if (TARGET_E500_DOUBLE && <MODE>mode == TFmode)
- emit_insn (gen_spe_fix_trunctfsi2 (op0, op1));
else if (<MODE>mode == TFmode)
emit_insn (gen_fix_trunctfsi2_fprs (op0, op1));
else if (<MODE>mode == IFmode)
@@ -7980,14 +7948,7 @@ (define_expand "abs<mode>2"
}
label = gen_label_rtx ();
- if (TARGET_E500_DOUBLE && <MODE>mode == TFmode)
- {
- if (flag_finite_math_only && !flag_trapping_math)
- emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
- else
- emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
- }
- else if (<MODE>mode == TFmode)
+ if (<MODE>mode == TFmode)
emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
else if (<MODE>mode == TFmode)
emit_insn (gen_absif2_internal (operands[0], operands[1], label));
@@ -9791,7 +9752,6 @@ (define_insn "*movdf_update2"
;; clobber outputs. Although those sets expand to multi-ppc-insn
;; sequences, using get_attr_length here will smash the operands
;; array. Neither is there an early_cobbler_p predicate.
-;; Disallow subregs for E500 so we don't munge frob_di_df_2.
;; Also this optimization interferes with scalars going into
;; altivec registers (the code does reloading through the FPRs).
(define_peephole2
@@ -9799,8 +9759,7 @@ (define_peephole2
(match_operand:DF 1 "any_operand" ""))
(set (match_operand:DF 2 "gpc_reg_operand" "")
(match_dup 0))]
- "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
- && !TARGET_UPPER_REGS_DF
+ "!TARGET_UPPER_REGS_DF
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md
index b6f4e0a..536697b 100644
--- a/gcc/config/rs6000/spe.md
+++ b/gcc/config/rs6000/spe.md
@@ -18,21 +18,6 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-(define_constants
- [(CMPDFEQ_GPR 1006)
- (TSTDFEQ_GPR 1007)
- (CMPDFGT_GPR 1008)
- (TSTDFGT_GPR 1009)
- (CMPDFLT_GPR 1010)
- (TSTDFLT_GPR 1011)
- (CMPTFEQ_GPR 1012)
- (TSTTFEQ_GPR 1013)
- (CMPTFGT_GPR 1014)
- (TSTTFGT_GPR 1015)
- (CMPTFLT_GPR 1016)
- (TSTTFLT_GPR 1017)
- ])
-
;; Modes using a 64-bit register.
(define_mode_iterator SPE64 [DF V4HI V2SF V1DI V2SI])
@@ -42,43 +27,6 @@ (define_mode_iterator SPE64TF [DF V4HI V2SF V1DI V2SI TF])
;; DImode and TImode.
(define_mode_iterator DITI [DI TI])
-;; Floating point conversion instructions.
-
-(define_insn "spe_fixuns_truncdfsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdctuiz %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "spe_extendsfdf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdcfs %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "spe_fix_truncdfsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdctsiz %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "spe_floatunssidf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdcfui %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "spe_floatsidf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdcfsi %0,%1"
- [(set_attr "type" "fp")])
-
;; SPE SIMD instructions
(define_insn "absv2si2"
@@ -2215,8 +2163,7 @@ (define_insn "spe_evstwwox"
(define_insn "*frob_<SPE64:mode>_<DITI:mode>"
[(set (match_operand:SPE64 0 "nonimmediate_operand" "=r,r")
(subreg:SPE64 (match_operand:DITI 1 "input_operand" "r,m") 0))]
- "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode)
- || (TARGET_SPE && <SPE64:MODE>mode != DFmode)"
+ "TARGET_SPE && <SPE64:MODE>mode != DFmode"
{
switch (which_alternative)
{
@@ -2235,8 +2182,7 @@ (define_insn "*frob_<SPE64:mode>_<DITI:mode>"
(define_insn "*frob_<SPE64:mode>_ti_8"
[(set (match_operand:SPE64 0 "nonimmediate_operand" "=r")
(subreg:SPE64 (match_operand:TI 1 "input_operand" "r") 8))]
- "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode)
- || (TARGET_SPE && <SPE64:MODE>mode != DFmode)"
+ "TARGET_SPE && <SPE64:MODE>mode != DFmode"
{
if (WORDS_BIG_ENDIAN)
return "evmergelo %0,%Y1,%Z1";
@@ -2244,23 +2190,10 @@ (define_insn "*frob_<SPE64:mode>_ti_8"
return "evmergelo %0,%Z1,%Y1";
})
-(define_insn "*frob_tf_ti"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=r")
- (subreg:TF (match_operand:TI 1 "gpc_reg_operand" "r") 0))]
- "TARGET_E500_DOUBLE"
-{
- if (WORDS_BIG_ENDIAN)
- return "evmergelo %0,%1,%L1\;evmergelo %L0,%Y1,%Z1";
- else
- return "evmergelo %L0,%Z1,%Y1\;evmergelo %0,%L1,%1";
-}
- [(set_attr "length" "8")])
-
(define_insn "*frob_<mode>_di_2"
[(set (subreg:DI (match_operand:SPE64TF 0 "nonimmediate_operand" "+&r,r") 0)
(match_operand:DI 1 "input_operand" "r,m"))]
- "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
+ "TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
{
switch (which_alternative)
{
@@ -2276,30 +2209,10 @@ (define_insn "*frob_<mode>_di_2"
}
})
-(define_insn "*frob_tf_di_8_2"
- [(set (subreg:DI (match_operand:TF 0 "nonimmediate_operand" "+&r,r") 8)
- (match_operand:DI 1 "input_operand" "r,m"))]
- "TARGET_E500_DOUBLE"
-{
- switch (which_alternative)
- {
- default:
- gcc_unreachable ();
- case 0:
- if (WORDS_BIG_ENDIAN)
- return "evmergelo %L0,%1,%L1";
- else
- return "evmergelo %L0,%L1,%1";
- case 1:
- return "evldd%X1 %L0,%y1";
- }
-})
-
(define_insn "*frob_di_<mode>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=&r")
(subreg:DI (match_operand:SPE64TF 1 "input_operand" "r") 0))]
- "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
+ "TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
{
if (WORDS_BIG_ENDIAN)
return "evmergehi %0,%1,%1\;mr %L0,%1";
@@ -2308,23 +2221,10 @@ (define_insn "*frob_di_<mode>"
}
[(set_attr "length" "8")])
-(define_insn "*frob_ti_tf"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=&r")
- (subreg:TI (match_operand:TF 1 "input_operand" "r") 0))]
- "TARGET_E500_DOUBLE"
-{
- if (WORDS_BIG_ENDIAN)
- return "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1";
- else
- return "evmergehi %Z0,%L1,%L1\;mr %Y0,%L1\;evmergehi %L0,%1,%1\;mr %0,%1";
-}
- [(set_attr "length" "16")])
-
(define_insn "*frob_<DITI:mode>_<SPE64:mode>_2"
[(set (subreg:SPE64 (match_operand:DITI 0 "register_operand" "+&r,r") 0)
(match_operand:SPE64 1 "input_operand" "r,m"))]
- "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode)
- || (TARGET_SPE && <SPE64:MODE>mode != DFmode)"
+ "TARGET_SPE && <SPE64:MODE>mode != DFmode"
"*
{
switch (which_alternative)
@@ -2373,8 +2273,7 @@ (define_insn "*frob_<DITI:mode>_<SPE64:mode>_2"
(define_insn "*frob_ti_<mode>_8_2"
[(set (subreg:SPE64 (match_operand:TI 0 "register_operand" "+&r,r") 8)
(match_operand:SPE64 1 "input_operand" "r,m"))]
- "(TARGET_E500_DOUBLE && <MODE>mode == DFmode)
- || (TARGET_SPE && <MODE>mode != DFmode)"
+ "TARGET_SPE && <MODE>mode != DFmode"
"*
{
switch (which_alternative)
@@ -2412,24 +2311,11 @@ (define_insn "*frob_ti_<mode>_8_2"
}"
[(set_attr "length" "8,8")])
-(define_insn "*frob_ti_tf_2"
- [(set (subreg:TF (match_operand:TI 0 "gpc_reg_operand" "=&r") 0)
- (match_operand:TF 1 "input_operand" "r"))]
- "TARGET_E500_DOUBLE"
-{
- if (WORDS_BIG_ENDIAN)
- return "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1";
- else
- return "evmergehi %Z0,%L1,%L1\;mr %Y0,%L1\;evmergehi %L0,%1,%1\;mr %0,%1";
-}
- [(set_attr "length" "16")])
-
(define_insn "mov_si<mode>_e500_subreg0_be"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 0)
(match_operand:SI 1 "input_operand" "r,m"))]
"WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
"@
evmergelo %0,%1,%0
evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0"
@@ -2439,8 +2325,7 @@ (define_insn "*mov_si<mode>_e500_subreg0_le"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 0)
(match_operand:SI 1 "input_operand" "r,m"))]
"!WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
"@
mr %0,%1
lwz%U1%X1 %0,%1")
@@ -2450,9 +2335,8 @@ (define_insn_and_split "*mov_si<mode>_e500_subreg0_elf_low_be"
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"WORDS_BIG_ENDIAN
- && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
- && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ())"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode
+ && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ()"
"#"
"&& 1"
[(pc)]
@@ -2469,9 +2353,8 @@ (define_insn "*mov_si<mode>_e500_subreg0_elf_low_le"
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"!WORDS_BIG_ENDIAN
- && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
- && TARGET_ELF && !TARGET_64BIT)"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode
+ && TARGET_ELF && !TARGET_64BIT"
"addi %0,%1,%K2")
;; ??? Could use evstwwe for memory stores in some cases, depending on
@@ -2480,8 +2363,7 @@ (define_insn "*mov_si<mode>_e500_subreg0_2_be"
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
(subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))]
"WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
"@
evmergelohi %0,%1,%1
evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
@@ -2491,8 +2373,7 @@ (define_insn "*mov_si<mode>_e500_subreg0_2_le"
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
(subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 0))]
"!WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
"@
mr %0,%1
stw%U0%X0 %1,%0")
@@ -2501,8 +2382,7 @@ (define_insn "*mov_si<mode>_e500_subreg4_be"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 4)
(match_operand:SI 1 "input_operand" "r,m"))]
"WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
"@
mr %0,%1
lwz%U1%X1 %0,%1")
@@ -2511,8 +2391,7 @@ (define_insn "mov_si<mode>_e500_subreg4_le"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 4)
(match_operand:SI 1 "input_operand" "r,m"))]
"!WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
"@
evmergelo %0,%1,%0
evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0"
@@ -2523,8 +2402,7 @@ (define_insn "*mov_si<mode>_e500_subreg4_elf_low_be"
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode
&& TARGET_ELF && !TARGET_64BIT"
"addi %0,%1,%K2")
@@ -2533,9 +2411,8 @@ (define_insn_and_split "*mov_si<mode>_e500_subreg4_elf_low_le"
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"!WORDS_BIG_ENDIAN
- && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
- && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ())"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode
+ && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ()"
"#"
"&& 1"
[(pc)]
@@ -2551,8 +2428,7 @@ (define_insn "*mov_si<mode>_e500_subreg4_2_be"
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
(subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
"WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
"@
mr %0,%1
stw%U0%X0 %1,%0")
@@ -2561,287 +2437,12 @@ (define_insn "*mov_si<mode>_e500_subreg4_2_le"
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
(subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 4))]
"!WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
"@
evmergelohi %0,%1,%1
evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
[(set_attr "length" "4,8")])
-(define_insn "*mov_sitf_e500_subreg8_be"
- [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 8)
- (match_operand:SI 1 "input_operand" "r,m"))]
- "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- evmergelo %L0,%1,%L0
- evmergelohi %L0,%L0,%L0\;lwz%U1%X1 %L0,%1\;evmergelohi %L0,%L0,%L0"
- [(set_attr "length" "4,12")])
-
-(define_insn "*mov_sitf_e500_subreg8_le"
- [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,r") 8)
- (match_operand:SI 1 "input_operand" "r,m"))]
- "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- mr %L0,%1
- lwz%U1%X1 %L0,%1")
-
-(define_insn "*mov_sitf_e500_subreg8_2_be"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
- (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 8))]
- "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- evmergelohi %0,%L1,%L1
- evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0"
- [(set_attr "length" "4,8")])
-
-(define_insn "*mov_sitf_e500_subreg8_2_le"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
- (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 8))]
- "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- mr %0,%L1
- stw%U0%X0 %L1,%0")
-
-(define_insn "*mov_sitf_e500_subreg12_be"
- [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,r") 12)
- (match_operand:SI 1 "input_operand" "r,m"))]
- "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- mr %L0,%1
- lwz%U1%X1 %L0,%1")
-
-(define_insn "*mov_sitf_e500_subreg12_le"
- [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 12)
- (match_operand:SI 1 "input_operand" "r,m"))]
- "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- evmergelo %L0,%1,%L0
- evmergelohi %L0,%L0,%L0\;lwz%U1%X1 %L0,%1\;evmergelohi %L0,%L0,%L0"
- [(set_attr "length" "4,12")])
-
-(define_insn "*mov_sitf_e500_subreg12_2_be"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
- (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 12))]
- "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- mr %0,%L1
- stw%U0%X0 %L1,%0")
-
-(define_insn "*mov_sitf_e500_subreg12_2_le"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
- (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 12))]
- "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- evmergelohi %0,%L1,%L1
- evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0"
- [(set_attr "length" "4,8")])
-
-;; FIXME: Allow r=CONST0.
-(define_insn "*movdf_e500_double"
- [(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m")
- (match_operand:DF 1 "input_operand" "r,m,r"))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && (gpc_reg_operand (operands[0], DFmode)
- || gpc_reg_operand (operands[1], DFmode))"
- "*
- {
- switch (which_alternative)
- {
- case 0:
- return \"evor %0,%1,%1\";
- case 1:
- return \"evldd%X1 %0,%y1\";
- case 2:
- return \"evstdd%X0 %1,%y0\";
- default:
- gcc_unreachable ();
- }
- }"
- [(set_attr "type" "*,vecload,vecstore")
- (set_attr "length" "*,*,*")])
-
-(define_insn "spe_truncdfsf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efscfd %0,%1")
-
-(define_insn "spe_absdf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdabs %0,%1")
-
-(define_insn "spe_nabsdf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdnabs %0,%1")
-
-(define_insn "spe_negdf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdneg %0,%1")
-
-(define_insn "spe_adddf3"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdadd %0,%1,%2")
-
-(define_insn "spe_subdf3"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdsub %0,%1,%2")
-
-(define_insn "spe_muldf3"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdmul %0,%1,%2")
-
-(define_insn "spe_divdf3"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (div:DF (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efddiv %0,%1,%2")
-
-;; Double-precision floating point instructions for IBM long double.
-
-(define_insn_and_split "spe_trunctfdf2_internal1"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r,?r")
- (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,r")))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "@
- #
- evor %0,%1,%1"
- "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
- [(const_int 0)]
-{
- emit_note (NOTE_INSN_DELETED);
- DONE;
-})
-
-(define_insn_and_split "spe_trunctfsf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "r")))
- (clobber (match_scratch:DF 2 "=r"))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "#"
- "&& reload_completed"
- [(set (match_dup 2)
- (float_truncate:DF (match_dup 1)))
- (set (match_dup 0)
- (float_truncate:SF (match_dup 2)))]
- "")
-
-(define_insn "spe_extenddftf2"
- [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,?r,r,o")
- (float_extend:TF (match_operand:DF 1 "input_operand" "0,r,m,r")))
- (clobber (match_scratch:DF 2 "=X,X,X,&r"))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "@
- evxor %L0,%L0,%L0
- evor %0,%1,%1\;evxor %L0,%L0,%L0
- evldd%X1 %0,%y1\;evxor %L0,%L0,%L0
- evstdd%X0 %1,%y0\;evxor %2,%2,%2\;evstdd %2,%Y0"
- [(set_attr "length" "4,8,8,12")])
-
-(define_expand "spe_fix_trunctfsi2"
- [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
- (clobber (match_dup 2))
- (clobber (match_dup 3))
- (clobber (match_dup 4))])]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
-{
- operands[2] = gen_reg_rtx (DFmode);
- operands[3] = gen_reg_rtx (SImode);
- operands[4] = gen_reg_rtx (SImode);
-})
-
-; Like fix_trunc_helper, add with rounding towards 0.
-(define_insn "spe_fix_trunctfsi2_internal"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (fix:SI (match_operand:TF 1 "gpc_reg_operand" "r")))
- (clobber (match_operand:DF 2 "gpc_reg_operand" "=r"))
- (clobber (match_operand:SI 3 "gpc_reg_operand" "=&r"))
- (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "mfspefscr %3\;rlwinm %4,%3,0,0,29\;ori %4,%4,1\;efdadd %2,%1,%L1\;mtspefscr %3\;efdctsiz %0, %2"
- [(set_attr "length" "24")])
-
-(define_insn "spe_negtf2_internal"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=r")
- (neg:TF (match_operand:TF 1 "gpc_reg_operand" "r")))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "*
-{
- if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
- return \"efdneg %L0,%L1\;efdneg %0,%1\";
- else
- return \"efdneg %0,%1\;efdneg %L0,%L1\";
-}"
- [(set_attr "length" "8")])
-
-(define_expand "spe_abstf2_cmp"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
- (match_operand:TF 1 "gpc_reg_operand" "f"))
- (set (match_dup 3) (match_dup 5))
- (set (match_dup 5) (abs:DF (match_dup 5)))
- (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
- (match_dup 5))] CMPDFEQ_GPR))
- (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
- (label_ref (match_operand 2 "" ""))
- (pc)))
- (set (match_dup 6) (neg:DF (match_dup 6)))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "
-{
- const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
- const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
- operands[3] = gen_reg_rtx (DFmode);
- operands[4] = gen_reg_rtx (CCFPmode);
- operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
- operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
-}")
-
-(define_expand "spe_abstf2_tst"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
- (match_operand:TF 1 "gpc_reg_operand" "f"))
- (set (match_dup 3) (match_dup 5))
- (set (match_dup 5) (abs:DF (match_dup 5)))
- (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
- (match_dup 5))] TSTDFEQ_GPR))
- (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
- (label_ref (match_operand 2 "" ""))
- (pc)))
- (set (match_dup 6) (neg:DF (match_dup 6)))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "
-{
- const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
- const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
- operands[3] = gen_reg_rtx (DFmode);
- operands[4] = gen_reg_rtx (CCFPmode);
- operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
- operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
-}")
-
;; Vector move instructions.
(define_expand "movv2si"
@@ -3155,154 +2756,6 @@ (define_insn "spe_mfspefscr"
;; We have 2 variants for each. One for IEEE compliant math and one
;; for non IEEE compliant math.
-;; Same thing, but for double-precision.
-
-(define_insn "cmpdfeq_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r"))]
- CMPDFEQ_GPR))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efdcmpeq %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
-(define_insn "tstdfeq_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r"))]
- TSTDFEQ_GPR))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && flag_finite_math_only && !flag_trapping_math"
- "efdtsteq %0,%1,%2"
- [(set_attr "type" "veccmpsimple")])
-
-(define_insn "cmpdfgt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r"))]
- CMPDFGT_GPR))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efdcmpgt %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
-(define_insn "tstdfgt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r"))]
- TSTDFGT_GPR))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && flag_finite_math_only && !flag_trapping_math"
- "efdtstgt %0,%1,%2"
- [(set_attr "type" "veccmpsimple")])
-
-(define_insn "cmpdflt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r"))]
- CMPDFLT_GPR))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efdcmplt %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
-(define_insn "tstdflt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r"))]
- TSTDFLT_GPR))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && flag_finite_math_only && !flag_trapping_math"
- "efdtstlt %0,%1,%2"
- [(set_attr "type" "veccmpsimple")])
-
-;; Same thing, but for IBM long double.
-
-(define_insn "cmptfeq_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
- (match_operand:TF 2 "gpc_reg_operand" "r"))]
- CMPTFEQ_GPR))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpeq %0,%L1,%L2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "12")])
-
-(define_insn "tsttfeq_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
- (match_operand:TF 2 "gpc_reg_operand" "r"))]
- TSTTFEQ_GPR))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
- && flag_finite_math_only && !flag_trapping_math"
- "efdtsteq %0,%1,%2\;bng %0,$+8\;efdtsteq %0,%L1,%L2"
- [(set_attr "type" "veccmpsimple")
- (set_attr "length" "12")])
-
-(define_insn "cmptfgt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
- (match_operand:TF 2 "gpc_reg_operand" "r"))]
- CMPTFGT_GPR))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efdcmpgt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpgt %0,%L1,%L2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "20")])
-
-(define_insn "tsttfgt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
- (match_operand:TF 2 "gpc_reg_operand" "r"))]
- TSTTFGT_GPR))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
- && flag_finite_math_only && !flag_trapping_math"
- "efdtstgt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstgt %0,%L1,%L2"
- [(set_attr "type" "veccmpsimple")
- (set_attr "length" "20")])
-
-(define_insn "cmptflt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
- (match_operand:TF 2 "gpc_reg_operand" "r"))]
- CMPTFLT_GPR))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efdcmplt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmplt %0,%L1,%L2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "20")])
-
-(define_insn "tsttflt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
- (match_operand:TF 2 "gpc_reg_operand" "r"))]
- TSTTFLT_GPR))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
- && flag_finite_math_only && !flag_trapping_math"
- "efdtstlt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstlt %0,%L1,%L2"
- [(set_attr "type" "veccmpsimple")
- (set_attr "length" "20")])
-
;; Out-of-line prologues and epilogues.
(define_insn "*save_gpregs_spe"
[(match_parallel 0 "any_parallel_operand"
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 03/14] rs6000: Remove -mfloat-gprs
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
@ 2017-06-06 15:57 ` Segher Boessenkool
2017-06-06 17:01 ` David Edelsohn
2017-06-06 15:57 ` [PATCH 02/14] rs6000: Remove TARGET_E500_{SINGLE,DOUBLE} Segher Boessenkool
` (12 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:57 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This deletes -mfloat-gprs and the variables that go with it.
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.c: Remove everything related to -mfloat-gprs.
* config/rs6000/rs6000.opt: Ditto.
* config/rs6000/t-rtems: Ditto.
---
gcc/config/rs6000/rs6000.c | 12 +-----------
gcc/config/rs6000/rs6000.opt | 20 --------------------
gcc/config/rs6000/t-rtems | 9 ++-------
3 files changed, 3 insertions(+), 38 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 8d578f4..1ad08d0 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2797,9 +2797,6 @@ rs6000_debug_reg_global (void)
if (rs6000_darwin64_abi)
fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
- if (rs6000_float_gprs)
- fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
-
fprintf (stderr, DEBUG_FMT_S, "single_float",
(TARGET_SINGLE_FLOAT ? "true" : "false"));
@@ -4198,12 +4195,6 @@ rs6000_option_override_internal (bool global_init_p)
if (!global_options_set.x_rs6000_spe)
rs6000_spe = spe_capable_cpu;
-
- if (!global_options_set.x_rs6000_float_gprs)
- rs6000_float_gprs =
- (rs6000_cpu == PROCESSOR_PPC8540 ? 1
- : rs6000_cpu == PROCESSOR_PPC8548 ? 2
- : 0);
}
if (global_options_set.x_rs6000_spe_abi
@@ -4218,8 +4209,7 @@ rs6000_option_override_internal (bool global_init_p)
if (main_target_opt != NULL
&& ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
- || (main_target_opt->x_rs6000_spe != rs6000_spe)
- || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
+ || (main_target_opt->x_rs6000_spe != rs6000_spe)))
error ("target attribute or pragma changes SPE ABI");
if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index fdac5c7..c5c11c5 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -449,26 +449,6 @@ mwarn-altivec-long
Target Var(rs6000_warn_altivec_long) Init(1) Save
Warn about deprecated 'vector long ...' AltiVec type usage.
-mfloat-gprs=
-Target RejectNegative Joined Enum(rs6000_float_gprs) Var(rs6000_float_gprs) Save
--mfloat-gprs= Select GPR floating point method.
-
-Enum
-Name(rs6000_float_gprs) Type(unsigned char)
-Valid arguments to -mfloat-gprs=:
-
-EnumValue
-Enum(rs6000_float_gprs) String(yes) Value(1)
-
-EnumValue
-Enum(rs6000_float_gprs) String(single) Value(1)
-
-EnumValue
-Enum(rs6000_float_gprs) String(double) Value(2)
-
-EnumValue
-Enum(rs6000_float_gprs) String(no) Value(0)
-
mlong-double-
Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
-mlong-double-<n> Specify size of long double (64 or 128 bits).
diff --git a/gcc/config/rs6000/t-rtems b/gcc/config/rs6000/t-rtems
index 7c7637d..723c6a3 100644
--- a/gcc/config/rs6000/t-rtems
+++ b/gcc/config/rs6000/t-rtems
@@ -30,8 +30,8 @@ MULTILIB_DIRNAMES += m403 m505 m603e m604 m860 m7400 m8540 me6500
MULTILIB_OPTIONS += m32
MULTILIB_DIRNAMES += m32
-MULTILIB_OPTIONS += msoft-float/mfloat-gprs=double
-MULTILIB_DIRNAMES += nof gprsdouble
+MULTILIB_OPTIONS += msoft-float
+MULTILIB_DIRNAMES += nof
MULTILIB_OPTIONS += mno-spe/mno-altivec
MULTILIB_DIRNAMES += nospe noaltivec
@@ -56,10 +56,6 @@ MULTILIB_MATCHES += mcpu?750=
# Map 8548 to 8540
MULTILIB_MATCHES += mcpu?8540=mcpu?8548
-# Map -mcpu=8540 -mfloat-gprs=single to -mcpu=8540
-# (mfloat-gprs=single is implicit default)
-MULTILIB_MATCHES += mcpu?8540=mcpu?8540/mfloat-gprs?single
-
# Enumeration of multilibs
MULTILIB_REQUIRED += msoft-float
@@ -73,7 +69,6 @@ MULTILIB_REQUIRED += mcpu=7400
MULTILIB_REQUIRED += mcpu=7400/msoft-float
MULTILIB_REQUIRED += mcpu=8540
MULTILIB_REQUIRED += mcpu=8540/msoft-float/mno-spe
-MULTILIB_REQUIRED += mcpu=8540/mfloat-gprs=double
MULTILIB_REQUIRED += mcpu=860
MULTILIB_REQUIRED += mcpu=e6500/m32
MULTILIB_REQUIRED += mcpu=e6500/m32/msoft-float/mno-altivec
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 01/14] rs6000: Remove TARGET_FPRS
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
` (3 preceding siblings ...)
2017-06-06 15:57 ` [PATCH 05/14] rs6000: Remove output_e500_flip_gt_bit Segher Boessenkool
@ 2017-06-06 15:57 ` Segher Boessenkool
2017-06-06 16:59 ` David Edelsohn
2017-06-12 10:02 ` [BUILDROBOT] No rule to make target '/home/jbglaw/repos/gcc/gcc/config/rs6000/e500.h', needed by 's-gtype' (was: [PATCH 01/14] rs6000: Remove TARGET_FPRS) Jan-Benedict Glaw
2017-06-06 15:58 ` [PATCH 06/14] rs6000: Remove UNSPEC_MV_CR_GT Segher Boessenkool
` (8 subsequent siblings)
13 siblings, 2 replies; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:57 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
Since rs6000 no longer supports SPE, TARGET_FPRS now always is true.
This makes TARGET_{SF,DF}_SPE always false. Many patterns in spe.md
can now be deleted; which makes it possible to merge e.g. negdd2 with
*negdd2_fpr.
Finally, e500.h is deleted (it isn't used).
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/darwin.md: Replace TARGET_FPRS by 1 and simplify.
* config/rs6000/dfp.md: Ditto.
(negdd2, *negdd2_fpr): Merge.
(absdd2, *absdd2_fpr): Merge.
(negtd2, *negtd2_fpr): Merge.
(abstd2, *abstd2_fpr): Merge.
* config/rs6000/e500.h: Delete file.
* config/rs6000/predicates.md (rs6000_cbranch_operator): Replace
TARGET_FPRS by 1 and simplify.
* config/rs6000/rs6000-c.c: Ditto.
* config/rs6000/rs6000.c: Ditto. Also replace TARGET_SF_SPE and
TARGET_DF_SPE by 0.
* config/rs6000/rs6000.h: Ditto. Delete TARGET_SF_SPE and
TARGET_DF_SPE.
* config/rs6000/rs6000.md: Ditto.
(floatdidf2, *floatdidf2_fpr): Merge.
(move_from_CR_gt_bit): Delete.
* config/rs6000/spe.md: Replace TARGET_FPRS by 1 and simplify.
(E500_CR_IOR_COMPARE): Delete.
(All patterns that require !TARGET_FPRS): Delete.
* config/rs6000/vsx.md: Replace TARGET_FPRS by 1 and simplify.
---
gcc/config/rs6000/darwin.md | 16 +--
gcc/config/rs6000/dfp.md | 48 ++-----
gcc/config/rs6000/e500.h | 45 ------
gcc/config/rs6000/predicates.md | 10 +-
gcc/config/rs6000/rs6000-c.c | 14 +-
gcc/config/rs6000/rs6000.c | 297 +++++-----------------------------------
gcc/config/rs6000/rs6000.h | 38 ++---
gcc/config/rs6000/rs6000.md | 262 +++++++++++++----------------------
gcc/config/rs6000/spe.md | 170 -----------------------
gcc/config/rs6000/vsx.md | 2 +-
10 files changed, 171 insertions(+), 731 deletions(-)
delete mode 100644 gcc/config/rs6000/e500.h
diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md
index fde67fd..a60185a 100644
--- a/gcc/config/rs6000/darwin.md
+++ b/gcc/config/rs6000/darwin.md
@@ -30,7 +30,7 @@ (define_insn "movdf_low_si"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
(mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
- "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT"
+ "TARGET_MACHO && TARGET_HARD_FLOAT && !TARGET_64BIT"
"*
{
switch (which_alternative)
@@ -61,7 +61,7 @@ (define_insn "movdf_low_di"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
- "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
+ "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"*
{
switch (which_alternative)
@@ -81,7 +81,7 @@ (define_insn "movdf_low_st_si"
[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))
(match_operand:DF 0 "gpc_reg_operand" "f"))]
- "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
+ "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
@@ -90,7 +90,7 @@ (define_insn "movdf_low_st_di"
[(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))
(match_operand:DF 0 "gpc_reg_operand" "f"))]
- "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
+ "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
@@ -99,7 +99,7 @@ (define_insn "movsf_low_si"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
(mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
- "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
+ "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"@
lfs %0,lo16(%2)(%1)
lwz %0,lo16(%2)(%1)"
@@ -110,7 +110,7 @@ (define_insn "movsf_low_di"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
(mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
- "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
+ "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"@
lfs %0,lo16(%2)(%1)
lwz %0,lo16(%2)(%1)"
@@ -121,7 +121,7 @@ (define_insn "movsf_low_st_si"
[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" "")))
(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
- "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
+ "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"@
stfs %0,lo16(%2)(%1)
stw %0,lo16(%2)(%1)"
@@ -132,7 +132,7 @@ (define_insn "movsf_low_st_di"
[(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" "")))
(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
- "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
+ "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"@
stfs %0,lo16(%2)(%1)
stw %0,lo16(%2)(%1)"
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 790f2e4..d42434f 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -35,7 +35,7 @@ (define_insn "movsd_store"
UNSPEC_MOVSD_STORE))]
"(gpc_reg_operand (operands[0], DDmode)
|| gpc_reg_operand (operands[1], SDmode))
- && TARGET_HARD_FLOAT && TARGET_FPRS"
+ && TARGET_HARD_FLOAT"
"stfd%U0%X0 %1,%0"
[(set_attr "type" "fpstore")
(set_attr "length" "4")])
@@ -46,7 +46,7 @@ (define_insn "movsd_load"
UNSPEC_MOVSD_LOAD))]
"(gpc_reg_operand (operands[0], SDmode)
|| gpc_reg_operand (operands[1], DDmode))
- && TARGET_HARD_FLOAT && TARGET_FPRS"
+ && TARGET_HARD_FLOAT"
"lfd%U1%X1 %0,%1"
[(set_attr "type" "fpload")
(set_attr "length" "4")])
@@ -78,65 +78,41 @@ (define_insn "truncddsd2"
"drsp %0,%1"
[(set_attr "type" "dfp")])
-(define_expand "negdd2"
- [(set (match_operand:DD 0 "gpc_reg_operand" "")
- (neg:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
- "")
-
-(define_insn "*negdd2_fpr"
+(define_insn "negdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_HARD_FLOAT"
"fneg %0,%1"
[(set_attr "type" "fpsimple")])
-(define_expand "absdd2"
- [(set (match_operand:DD 0 "gpc_reg_operand" "")
- (abs:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
- "")
-
-(define_insn "*absdd2_fpr"
+(define_insn "absdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_HARD_FLOAT"
"fabs %0,%1"
[(set_attr "type" "fpsimple")])
(define_insn "*nabsdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_HARD_FLOAT"
"fnabs %0,%1"
[(set_attr "type" "fpsimple")])
-(define_expand "negtd2"
- [(set (match_operand:TD 0 "gpc_reg_operand" "")
- (neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
- "")
-
-(define_insn "*negtd2_fpr"
+(define_insn "negtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
(neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_HARD_FLOAT"
"@
fneg %0,%1
fneg %0,%1\;fmr %L0,%L1"
[(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
-(define_expand "abstd2"
- [(set (match_operand:TD 0 "gpc_reg_operand" "")
- (abs:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
- "")
-
-(define_insn "*abstd2_fpr"
+(define_insn "abstd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
(abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_HARD_FLOAT"
"@
fabs %0,%1
fabs %0,%1\;fmr %L0,%L1"
@@ -146,7 +122,7 @@ (define_insn "*abstd2_fpr"
(define_insn "*nabstd2_fpr"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
(neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_HARD_FLOAT"
"@
fnabs %0,%1
fnabs %0,%1\;fmr %L0,%L1"
diff --git a/gcc/config/rs6000/e500.h b/gcc/config/rs6000/e500.h
deleted file mode 100644
index 3da9a6e..0000000
--- a/gcc/config/rs6000/e500.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Enable E500 support.
- Copyright (C) 2003-2017 Free Software Foundation, Inc.
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>. */
-
-#undef TARGET_SPE_ABI
-#undef TARGET_SPE
-#undef TARGET_FPRS
-#undef TARGET_E500_SINGLE
-#undef TARGET_E500_DOUBLE
-#undef CHECK_E500_OPTIONS
-
-#define TARGET_SPE_ABI rs6000_spe_abi
-#define TARGET_SPE rs6000_spe
-#define TARGET_FPRS (rs6000_float_gprs == 0)
-#define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1)
-#define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2)
-#define CHECK_E500_OPTIONS \
- do { \
- if (TARGET_SPE || TARGET_SPE_ABI \
- || TARGET_E500_SINGLE || TARGET_E500_DOUBLE) \
- { \
- if (TARGET_ALTIVEC) \
- error ("AltiVec and SPE instructions cannot coexist"); \
- if (TARGET_VSX) \
- error ("VSX and SPE instructions cannot coexist"); \
- if (TARGET_64BIT) \
- error ("64-bit SPE not supported"); \
- if (TARGET_HARD_FLOAT && TARGET_FPRS) \
- error ("E500 and FPRs not supported"); \
- } \
- } while (0)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 7a74d59..a9bf854 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1240,16 +1240,8 @@ (define_predicate "branch_comparison_operator"
1"))))
;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
-;; If we're assuming that FP operations cannot generate user-visible traps,
-;; then on e500 we can use the ordered-signaling instructions to implement
-;; the unordered-quiet FP comparison predicates modulo a reversal.
(define_predicate "rs6000_cbranch_operator"
- (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
- (if_then_else (match_test "flag_trapping_math")
- (match_operand 0 "ordered_comparison_operator")
- (ior (match_operand 0 "ordered_comparison_operator")
- (match_code ("unlt,unle,ungt,unge"))))
- (match_operand 0 "comparison_operator")))
+ (match_operand 0 "comparison_operator"))
;; Return 1 if OP is an unsigned comparison operator.
(define_predicate "unsigned_comparison_operator"
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 8039814..fccbbb7 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -488,10 +488,10 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
the following conditions:
1. The operating system does not support saving of AltiVec
registers (OS_MISSING_ALTIVEC).
- 2. If any of the options TARGET_HARD_FLOAT, TARGET_FPRS,
- TARGET_SINGLE_FLOAT, or TARGET_DOUBLE_FLOAT are turned off.
- Hereafter, the OPTION_MASK_VSX flag is considered to have been
- turned off explicitly.
+ 2. If any of the options TARGET_HARD_FLOAT, TARGET_SINGLE_FLOAT,
+ or TARGET_DOUBLE_FLOAT are turned off. Hereafter, the
+ OPTION_MASK_VSX flag is considered to have been turned off
+ explicitly.
3. If TARGET_PAIRED_FLOAT was enabled. Hereafter, the
OPTION_MASK_VSX flag is considered to have been turned off
explicitly.
@@ -674,8 +674,8 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
}
}
- if ((!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
- ||(TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_DOUBLE_FLOAT))
+ if (!TARGET_HARD_FLOAT
+ || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
builtin_define ("_SOFT_DOUBLE");
/* Used by lwarx/stwcx. errata work-around. */
if (rs6000_cpu == PROCESSOR_PPC405)
@@ -775,7 +775,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__");
/* Let the compiled code know if 'f' class registers will not be available. */
- if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
+ if (TARGET_SOFT_FLOAT)
builtin_define ("__NO_FPRS__");
/* Whether aggregates passed by value are aligned to a 16 byte boundary
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index fcdb8ac..4a37a58 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2809,9 +2809,6 @@ rs6000_debug_reg_global (void)
if (rs6000_float_gprs)
fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
- fprintf (stderr, DEBUG_FMT_S, "fprs",
- (TARGET_FPRS ? "true" : "false"));
-
fprintf (stderr, DEBUG_FMT_S, "single_float",
(TARGET_SINGLE_FLOAT ? "true" : "false"));
@@ -3251,10 +3248,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wJ - VSX register if QImode/HImode are allowed in VSX registers.
wK - Altivec register if QImode/HImode are allowed in VSX registers. */
- if (TARGET_HARD_FLOAT && TARGET_FPRS)
+ if (TARGET_HARD_FLOAT)
rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
- if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
+ if (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
if (TARGET_VSX)
@@ -3619,8 +3616,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (addis_insns[i].pmode != cur_pmode)
continue;
- if (rtype == RELOAD_REG_FPR
- && (!TARGET_HARD_FLOAT || !TARGET_FPRS))
+ if (rtype == RELOAD_REG_FPR && !TARGET_HARD_FLOAT)
continue;
reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load;
@@ -3645,7 +3641,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[HImode].fused_toc = true;
reg_addr[SImode].fused_toc = true;
reg_addr[DImode].fused_toc = true;
- if (TARGET_HARD_FLOAT && TARGET_FPRS)
+ if (TARGET_HARD_FLOAT)
{
if (TARGET_SINGLE_FLOAT)
reg_addr[SFmode].fused_toc = true;
@@ -4311,8 +4307,7 @@ rs6000_option_override_internal (bool global_init_p)
if (TARGET_VSX)
{
const char *msg = NULL;
- if (!TARGET_HARD_FLOAT || !TARGET_FPRS
- || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
+ if (!TARGET_HARD_FLOAT || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
{
if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
msg = N_("-mvsx requires hardware floating point");
@@ -5506,8 +5501,7 @@ rs6000_option_override_internal (bool global_init_p)
/* Set up single/double float flags.
If TARGET_HARD_FLOAT is set, but neither single or double is set,
then set both flags. */
- if (TARGET_HARD_FLOAT && TARGET_FPRS
- && rs6000_single_float == 0 && rs6000_double_float == 0)
+ if (TARGET_HARD_FLOAT && rs6000_single_float == 0 && rs6000_double_float == 0)
rs6000_single_float = rs6000_double_float = 1;
/* If not explicitly specified via option, decide whether to generate indexed
@@ -9060,7 +9054,7 @@ legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
return false;
if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
&& !(/* ??? Assume floating point reg based on mode? */
- TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+ TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (mode == DFmode || mode == DDmode)))
return false;
@@ -9171,7 +9165,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& GET_MODE_NUNITS (mode) == 1
&& (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
|| (/* ??? Assume floating point reg based on mode? */
- (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
+ (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
&& (mode == DFmode || mode == DDmode)))
&& !avoiding_indexed_address_p (mode))
{
@@ -9227,7 +9221,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& GET_MODE_NUNITS (mode) == 1
&& (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
|| (/* ??? Assume floating point reg based on mode? */
- (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
+ (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
&& (mode == DFmode || mode == DDmode))))
{
rtx reg = gen_reg_rtx (Pmode);
@@ -10019,7 +10013,7 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode,
&& mode != PTImode
&& (mode != DImode || TARGET_POWERPC64)
&& ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
- || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
+ || (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)))
{
#if TARGET_MACHO
if (flag_pic)
@@ -10200,7 +10194,7 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
return 1;
if (!FLOAT128_2REG_P (mode)
- && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
+ && ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
|| TARGET_POWERPC64
|| (mode != DFmode && mode != DDmode)
|| (TARGET_E500_DOUBLE && mode != DDmode))
@@ -10432,7 +10426,7 @@ rs6000_conditional_register_usage (void)
= call_really_used_regs[13] = 1;
/* Conditionally disable FPRs. */
- if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
+ if (TARGET_SOFT_FLOAT)
for (i = 32; i < 64; i++)
fixed_regs[i] = call_used_regs[i]
= call_really_used_regs[i] = 1;
@@ -11401,7 +11395,7 @@ rs6000_member_type_forces_blk (const_tree field, machine_mode mode)
#define USE_FP_FOR_ARG_P(CUM,MODE) \
(SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
&& (CUM)->fregno <= FP_ARG_MAX_REG \
- && TARGET_HARD_FLOAT && TARGET_FPRS)
+ && TARGET_HARD_FLOAT)
/* Nonzero if we can use an AltiVec register to pass this arg. */
#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
@@ -11927,7 +11921,7 @@ is_complex_IBM_long_double (machine_mode mode)
static bool
abi_v4_pass_in_fpr (machine_mode mode)
{
- if (!TARGET_FPRS || !TARGET_HARD_FLOAT)
+ if (!TARGET_HARD_FLOAT)
return false;
if (TARGET_SINGLE_FLOAT && mode == SFmode)
return true;
@@ -12027,7 +12021,6 @@ rs6000_function_arg_boundary (machine_mode mode, const_tree type)
if (DEFAULT_ABI == ABI_V4
&& (GET_MODE_SIZE (mode) == 8
|| (TARGET_HARD_FLOAT
- && TARGET_FPRS
&& !is_complex_IBM_long_double (mode)
&& FLOAT128_2REG_P (mode))))
return 64;
@@ -12480,7 +12473,7 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
cum->words = align_words + n_words;
- if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
+ if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
{
/* _Decimal128 must be passed in an even/odd float register pair.
This assumes that the register number is odd when fregno is
@@ -12972,7 +12965,7 @@ rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
/* For the SPE, we need to crxor CR6 always. */
if (TARGET_SPE_ABI)
return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
- else if (TARGET_HARD_FLOAT && TARGET_FPRS)
+ else if (TARGET_HARD_FLOAT)
return GEN_INT (cum->call_cookie
| ((cum->fregno == FP_ARG_MIN_REG)
? CALL_V4_SET_FP_ARGS
@@ -13608,7 +13601,7 @@ setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
anything. */
if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
- if (TARGET_HARD_FLOAT && TARGET_FPRS
+ if (TARGET_HARD_FLOAT
&& next_cum.fregno <= FP_ARG_V4_MAX_REG
&& cfun->va_list_fpr_size)
{
@@ -13697,7 +13690,7 @@ setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
/* Save FP registers if needed. */
if (DEFAULT_ABI == ABI_V4
- && TARGET_HARD_FLOAT && TARGET_FPRS
+ && TARGET_HARD_FLOAT
&& ! no_rtl
&& next_cum.fregno <= FP_ARG_V4_MAX_REG
&& cfun->va_list_fpr_size)
@@ -14068,9 +14061,7 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
/* _Decimal32 varargs are located in the second word of the 64-bit
FP register for 32-bit binaries. */
- if (TARGET_32BIT
- && TARGET_HARD_FLOAT && TARGET_FPRS
- && mode == SDmode)
+ if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
t = fold_build_pointer_plus_hwi (t, size);
/* Args are passed right-aligned. */
@@ -19388,7 +19379,7 @@ init_float128_ibm (machine_mode mode)
set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
- if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
+ if (!TARGET_HARD_FLOAT)
{
set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
@@ -19397,6 +19388,7 @@ init_float128_ibm (machine_mode mode)
set_optab_libfunc (ge_optab, mode, "__gcc_qge");
set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
set_optab_libfunc (le_optab, mode, "__gcc_qle");
+ set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
@@ -19407,9 +19399,6 @@ init_float128_ibm (machine_mode mode)
set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
}
-
- if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
- set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
}
else
{
@@ -24475,187 +24464,9 @@ rs6000_generate_compare (rtx cmp, machine_mode mode)
/* First, the compare. */
compare_result = gen_reg_rtx (comp_mode);
- /* E500 FP compare instructions on the GPRs. Yuck! */
- if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
- && FLOAT_MODE_P (mode))
- {
- rtx cmp, or_result, compare_result2;
- machine_mode op_mode = GET_MODE (op0);
- bool reverse_p;
-
- if (op_mode == VOIDmode)
- op_mode = GET_MODE (op1);
-
- /* First reverse the condition codes that aren't directly supported. */
- switch (code)
- {
- case NE:
- case UNLT:
- case UNLE:
- case UNGT:
- case UNGE:
- code = reverse_condition_maybe_unordered (code);
- reverse_p = true;
- break;
-
- case EQ:
- case LT:
- case LE:
- case GT:
- case GE:
- reverse_p = false;
- break;
-
- default:
- gcc_unreachable ();
- }
-
- /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
- This explains the following mess. */
-
- switch (code)
- {
- case EQ:
- switch (op_mode)
- {
- case SFmode:
- cmp = (flag_finite_math_only && !flag_trapping_math)
- ? gen_tstsfeq_gpr (compare_result, op0, op1)
- : gen_cmpsfeq_gpr (compare_result, op0, op1);
- break;
-
- case DFmode:
- cmp = (flag_finite_math_only && !flag_trapping_math)
- ? gen_tstdfeq_gpr (compare_result, op0, op1)
- : gen_cmpdfeq_gpr (compare_result, op0, op1);
- break;
-
- case TFmode:
- case IFmode:
- case KFmode:
- cmp = (flag_finite_math_only && !flag_trapping_math)
- ? gen_tsttfeq_gpr (compare_result, op0, op1)
- : gen_cmptfeq_gpr (compare_result, op0, op1);
- break;
-
- default:
- gcc_unreachable ();
- }
- break;
-
- case GT:
- case GE:
- switch (op_mode)
- {
- case SFmode:
- cmp = (flag_finite_math_only && !flag_trapping_math)
- ? gen_tstsfgt_gpr (compare_result, op0, op1)
- : gen_cmpsfgt_gpr (compare_result, op0, op1);
- break;
-
- case DFmode:
- cmp = (flag_finite_math_only && !flag_trapping_math)
- ? gen_tstdfgt_gpr (compare_result, op0, op1)
- : gen_cmpdfgt_gpr (compare_result, op0, op1);
- break;
-
- case TFmode:
- case IFmode:
- case KFmode:
- cmp = (flag_finite_math_only && !flag_trapping_math)
- ? gen_tsttfgt_gpr (compare_result, op0, op1)
- : gen_cmptfgt_gpr (compare_result, op0, op1);
- break;
-
- default:
- gcc_unreachable ();
- }
- break;
-
- case LT:
- case LE:
- switch (op_mode)
- {
- case SFmode:
- cmp = (flag_finite_math_only && !flag_trapping_math)
- ? gen_tstsflt_gpr (compare_result, op0, op1)
- : gen_cmpsflt_gpr (compare_result, op0, op1);
- break;
-
- case DFmode:
- cmp = (flag_finite_math_only && !flag_trapping_math)
- ? gen_tstdflt_gpr (compare_result, op0, op1)
- : gen_cmpdflt_gpr (compare_result, op0, op1);
- break;
-
- case TFmode:
- case IFmode:
- case KFmode:
- cmp = (flag_finite_math_only && !flag_trapping_math)
- ? gen_tsttflt_gpr (compare_result, op0, op1)
- : gen_cmptflt_gpr (compare_result, op0, op1);
- break;
-
- default:
- gcc_unreachable ();
- }
- break;
-
- default:
- gcc_unreachable ();
- }
-
- /* Synthesize LE and GE from LT/GT || EQ. */
- if (code == LE || code == GE)
- {
- emit_insn (cmp);
-
- compare_result2 = gen_reg_rtx (CCFPmode);
-
- /* Do the EQ. */
- switch (op_mode)
- {
- case SFmode:
- cmp = (flag_finite_math_only && !flag_trapping_math)
- ? gen_tstsfeq_gpr (compare_result2, op0, op1)
- : gen_cmpsfeq_gpr (compare_result2, op0, op1);
- break;
-
- case DFmode:
- cmp = (flag_finite_math_only && !flag_trapping_math)
- ? gen_tstdfeq_gpr (compare_result2, op0, op1)
- : gen_cmpdfeq_gpr (compare_result2, op0, op1);
- break;
-
- case TFmode:
- case IFmode:
- case KFmode:
- cmp = (flag_finite_math_only && !flag_trapping_math)
- ? gen_tsttfeq_gpr (compare_result2, op0, op1)
- : gen_cmptfeq_gpr (compare_result2, op0, op1);
- break;
-
- default:
- gcc_unreachable ();
- }
-
- emit_insn (cmp);
-
- /* OR them together. */
- or_result = gen_reg_rtx (CCFPmode);
- cmp = gen_e500_cr_ior_compare (or_result, compare_result,
- compare_result2);
- compare_result = or_result;
- }
-
- code = reverse_p ? NE : EQ;
-
- emit_insn (cmp);
- }
-
/* IEEE 128-bit support in VSX registers when we do not have hardware
support. */
- else if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
+ if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
{
rtx libfunc = NULL_RTX;
bool check_nan = false;
@@ -24772,7 +24583,7 @@ rs6000_generate_compare (rtx cmp, machine_mode mode)
CLOBBERs to match cmptf_internal2 pattern. */
if (comp_mode == CCFPmode && TARGET_XL_COMPAT
&& FLOAT128_IBM_P (GET_MODE (op0))
- && TARGET_HARD_FLOAT && TARGET_FPRS)
+ && TARGET_HARD_FLOAT)
emit_insn (gen_rtx_PARALLEL (VOIDmode,
gen_rtvec (10,
gen_rtx_SET (compare_result,
@@ -24807,7 +24618,6 @@ rs6000_generate_compare (rtx cmp, machine_mode mode)
if (FLOAT_MODE_P (mode)
&& (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
&& !flag_finite_math_only
- && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
&& (code == LE || code == GE
|| code == UNEQ || code == LTGT
|| code == UNGT || code == UNLT))
@@ -25169,23 +24979,6 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
condition_rtx = rs6000_generate_compare (operands[1], mode);
cond_code = GET_CODE (condition_rtx);
- if (FLOAT_MODE_P (mode)
- && !TARGET_FPRS && TARGET_HARD_FLOAT)
- {
- rtx t;
-
- PUT_MODE (condition_rtx, SImode);
- t = XEXP (condition_rtx, 0);
-
- gcc_assert (cond_code == NE || cond_code == EQ);
-
- if (cond_code == NE)
- emit_insn (gen_e500_flip_gt_bit (t, t));
-
- emit_insn (gen_move_from_CR_gt_bit (result, t));
- return;
- }
-
if (cond_code == NE
|| cond_code == GE || cond_code == LE
|| cond_code == GEU || cond_code == LEU
@@ -25276,26 +25069,6 @@ output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
code = reverse_condition (code);
}
- if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
- {
- /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
- to the GT bit. */
- switch (code)
- {
- case EQ:
- /* Opposite of GT. */
- code = GT;
- break;
-
- case NE:
- code = UNLE;
- break;
-
- default:
- gcc_unreachable ();
- }
- }
-
switch (code)
{
/* Not all of these are actually distinct opcodes, but
@@ -25819,9 +25592,6 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
return 0;
}
- else if (TARGET_HARD_FLOAT && !TARGET_FPRS
- && SCALAR_FLOAT_MODE_P (compare_mode))
- return 0;
is_against_zero = op1 == CONST0_RTX (compare_mode);
@@ -36525,9 +36295,9 @@ rs6000_elf_file_end (void)
{
int fp;
- if (TARGET_DF_FPR | TARGET_DF_SPE)
+ if (TARGET_DF_FPR)
fp = 1;
- else if (TARGET_SF_FPR | TARGET_SF_SPE)
+ else if (TARGET_SF_FPR)
fp = 3;
else
fp = 2;
@@ -37598,8 +37368,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
*total = COSTS_N_INSNS (1);
return true;
}
- else if (FLOAT_MODE_P (mode)
- && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
+ else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
{
*total = rs6000_cost->fp;
return false;
@@ -38737,7 +38506,7 @@ rs6000_complex_function_value (machine_mode mode)
|| (mode == TCmode && TARGET_IEEEQUAD)))
regno = ALTIVEC_ARG_RETURN;
- else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
+ else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
regno = FP_ARG_RETURN;
else
@@ -38858,10 +38627,10 @@ rs6000_function_value (const_tree valtype,
|| POINTER_TYPE_P (valtype))
mode = TARGET_32BIT ? SImode : DImode;
- if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
+ if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
/* _Decimal128 must use an even/odd register pair. */
regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
- else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS
+ else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
&& !FLOAT128_VECTOR_P (mode)
&& ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
regno = FP_ARG_RETURN;
@@ -38896,11 +38665,11 @@ rs6000_libcall_value (machine_mode mode)
if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
- if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
+ if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
/* _Decimal128 must use an even/odd register pair. */
regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode)
- && TARGET_HARD_FLOAT && TARGET_FPRS
+ && TARGET_HARD_FLOAT
&& ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
regno = FP_ARG_RETURN;
/* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
@@ -38946,7 +38715,7 @@ rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
{
if (TARGET_ALTIVEC)
pressure_classes[n++] = ALTIVEC_REGS;
- if (TARGET_HARD_FLOAT && TARGET_FPRS)
+ if (TARGET_HARD_FLOAT)
pressure_classes[n++] = FLOAT_REGS;
}
pressure_classes[n++] = CR_REGS;
@@ -43446,7 +43215,7 @@ static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
static void
rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
{
- if (!TARGET_HARD_FLOAT || !TARGET_FPRS)
+ if (!TARGET_HARD_FLOAT)
{
#ifdef RS6000_GLIBC_ATOMIC_FENV
if (atomic_hold_decl == NULL_TREE)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 479f9fb..dec1ab7 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -449,8 +449,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
#define FLOAT128_IBM_P(MODE) \
((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
- || (TARGET_HARD_FLOAT && TARGET_FPRS \
- && ((MODE) == IFmode || (MODE) == ICmode)))
+ || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
/* Helper macros to say whether a 128-bit floating point type can go in a
single vector register, or whether it needs paired scalar values. */
@@ -573,7 +572,6 @@ extern int rs6000_vector_align[];
#define TARGET_SPE_ABI 0
#define TARGET_SPE 0
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
-#define TARGET_FPRS 1
#define TARGET_E500_SINGLE 0
#define TARGET_E500_DOUBLE 0
#define CHECK_E500_OPTIONS do { } while (0)
@@ -724,39 +722,26 @@ extern int rs6000_vector_align[];
|| rs6000_cpu == PROCESSOR_PPC8548)
-/* Whether SF/DF operations are supported on the E500. */
-#define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \
- && !TARGET_FPRS)
-
-#define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
- && !TARGET_FPRS && TARGET_E500_DOUBLE)
-
/* Whether SF/DF operations are supported by the normal floating point unit
(or the vector/scalar unit). */
-#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
- && TARGET_SINGLE_FLOAT)
-
-#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
- && TARGET_DOUBLE_FLOAT)
+#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT)
+#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
/* Whether SF/DF operations are supported by any hardware. */
-#define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE)
-#define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE)
+#define TARGET_SF_INSN TARGET_SF_FPR
+#define TARGET_DF_INSN TARGET_DF_FPR
/* Which machine supports the various reciprocal estimate instructions. */
#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
- && TARGET_FPRS && TARGET_SINGLE_FLOAT)
+ && TARGET_SINGLE_FLOAT)
-#define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
- && TARGET_DOUBLE_FLOAT \
+#define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
- && TARGET_PPC_GFXOPT && TARGET_FPRS \
- && TARGET_SINGLE_FLOAT)
+ && TARGET_PPC_GFXOPT && TARGET_SINGLE_FLOAT)
-#define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
- && TARGET_DOUBLE_FLOAT \
+#define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
&& (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
/* Conditions to allow TOC fusion for loading/storing integers. */
@@ -771,7 +756,6 @@ extern int rs6000_vector_align[];
&& (TARGET_CMODEL != CMODEL_SMALL) \
&& TARGET_POWERPC64 \
&& TARGET_HARD_FLOAT \
- && TARGET_FPRS \
&& TARGET_SINGLE_FLOAT \
&& TARGET_DOUBLE_FLOAT)
@@ -1875,7 +1859,7 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
#define FUNCTION_VALUE_REGNO_P(N) \
((N) == GP_ARG_RETURN \
|| (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
- && TARGET_HARD_FLOAT && TARGET_FPRS) \
+ && TARGET_HARD_FLOAT) \
|| (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
&& TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
@@ -1887,7 +1871,7 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
|| (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
&& TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
|| (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
- && TARGET_HARD_FLOAT && TARGET_FPRS))
+ && TARGET_HARD_FLOAT))
\f
/* Define a data type for recording info about an argument list
during the scan of that argument list. This data type should
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d8c890c..210077d 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -372,22 +372,18 @@ (define_mode_iterator TI2 [TI PTI])
; Any hardware-supported floating-point mode
(define_mode_iterator FP [
- (SF "TARGET_HARD_FLOAT
- && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
- (DF "TARGET_HARD_FLOAT
- && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
- (TF "TARGET_HARD_FLOAT
- && (TARGET_FPRS || TARGET_E500_DOUBLE)
- && TARGET_LONG_DOUBLE_128")
- (IF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")
+ (SF "TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT || TARGET_E500_SINGLE)")
+ (DF "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)")
+ (TF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
+ (IF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
(KF "TARGET_FLOAT128_TYPE")
(DD "TARGET_DFP")
(TD "TARGET_DFP")])
; Any fma capable floating-point mode.
(define_mode_iterator FMA_F [
- (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
- (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
+ (SF "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT")
+ (DF "(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
|| VECTOR_UNIT_VSX_P (DFmode)")
(V2SF "TARGET_PAIRED_FLOAT")
(V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
@@ -402,11 +398,11 @@ (define_mode_iterator FMOVE64 [DF DD])
(define_mode_iterator FMOVE64X [DI DF DD])
(define_mode_iterator FMOVE128 [(TF "TARGET_LONG_DOUBLE_128")
(IF "FLOAT128_IBM_P (IFmode)")
- (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
+ (TD "TARGET_HARD_FLOAT")])
(define_mode_iterator FMOVE128_FPR [(TF "FLOAT128_2REG_P (TFmode)")
(IF "FLOAT128_2REG_P (IFmode)")
- (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
+ (TD "TARGET_HARD_FLOAT")])
; Iterators for 128 bit types for direct move
(define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
@@ -426,7 +422,7 @@ (define_mode_iterator FMOVE128_VSX [V1TI KF])
; Whether a floating point move is ok, don't allow SD without hardware FP
(define_mode_attr fmove_ok [(SF "")
(DF "")
- (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
+ (SD "TARGET_HARD_FLOAT")
(DD "")])
; Convert REAL_VALUE to the appropriate bits
@@ -618,7 +614,7 @@ (define_mode_attr rreg2 [(SF "f")
(define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
(DF "TARGET_FCFID")])
-(define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
+(define_mode_attr E500_CONVERT [(SF "0")
(DF "TARGET_E500_DOUBLE")])
(define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
@@ -4650,7 +4646,7 @@ (define_insn "*cmp<mode>_fpr"
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand")
(float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand")))]
- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
+ "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
{
if (HONOR_SNANS (SFmode))
operands[1] = force_reg (SFmode, operands[1]);
@@ -4659,8 +4655,7 @@ (define_expand "extendsfdf2"
(define_insn_and_split "*extendsfdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wu,wb")
(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z,wY")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
- && !HONOR_SNANS (SFmode)"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !HONOR_SNANS (SFmode)"
"@
#
fmr %0,%1
@@ -4680,8 +4675,7 @@ (define_insn_and_split "*extendsfdf2_fpr"
(define_insn "*extendsfdf2_snan"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f,wy")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
- && HONOR_SNANS (SFmode)"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && HONOR_SNANS (SFmode)"
"@
frsp %0,%1
xsrsp %x0,%x1"
@@ -4690,13 +4684,13 @@ (define_insn "*extendsfdf2_snan"
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
+ "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
"")
(define_insn "*truncdfsf2_fpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,ws")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
frsp %0,%1
xsrsp %x0,%x1"
@@ -4715,7 +4709,6 @@ (define_expand "signbit<mode>2"
(set (match_operand:SI 0 "gpc_reg_operand" "")
(match_dup 6))]
"TARGET_HARD_FLOAT
- && (TARGET_FPRS || TARGET_E500_DOUBLE)
&& (!FLOAT128_IEEE_P (<MODE>mode)
|| (TARGET_POWERPC64 && TARGET_DIRECT_MOVE))"
{
@@ -4757,7 +4750,7 @@ (define_expand "copysign<mode>3"
(match_dup 5))
(match_dup 3)
(match_dup 4)))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
+ "TARGET_HARD_FLOAT && <TARGET_FLOAT>
&& ((TARGET_PPC_GFXOPT
&& !HONOR_NANS (<MODE>mode)
&& !HONOR_SIGNED_ZEROS (<MODE>mode))
@@ -5096,7 +5089,7 @@ (define_insn "lfiwax"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wK")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wK")]
UNSPEC_LFIWAX))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
"@
lfiwax %0,%y1
lxsiwax %x0,%y1
@@ -5113,7 +5106,7 @@ (define_insn_and_split "floatsi<mode>2_lfiwax"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
(float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
(clobber (match_scratch:DI 2 "=wi"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
&& <SI_CONVERT_FP> && can_create_pseudo_p ()"
"#"
""
@@ -5156,8 +5149,7 @@ (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
(sign_extend:DI
(match_operand:SI 1 "indexed_or_indirect_operand" "Z"))))
(clobber (match_scratch:DI 2 "=wi"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
- && <SI_CONVERT_FP>"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX && <SI_CONVERT_FP>"
"#"
""
[(pc)]
@@ -5180,7 +5172,7 @@ (define_insn "lfiwzx"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wJwK")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wJwK")]
UNSPEC_LFIWZX))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
"@
lfiwzx %0,%y1
lxsiwzx %x0,%y1
@@ -5192,8 +5184,7 @@ (define_insn_and_split "floatunssi<mode>2_lfiwzx"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
(unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
(clobber (match_scratch:DI 2 "=wi"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
- && <SI_CONVERT_FP>"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
"#"
""
[(pc)]
@@ -5235,8 +5226,7 @@ (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
(zero_extend:DI
(match_operand:SI 1 "indexed_or_indirect_operand" "Z"))))
(clobber (match_scratch:DI 2 "=wi"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
- && <SI_CONVERT_FP>"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
"#"
""
[(pc)]
@@ -5268,8 +5258,7 @@ (define_expand "floatsidf2"
(clobber (match_dup 4))
(clobber (match_dup 5))
(clobber (match_dup 6))])]
- "TARGET_HARD_FLOAT
- && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
+ "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
"
{
if (TARGET_E500_DOUBLE)
@@ -5311,7 +5300,7 @@ (define_insn_and_split "*floatsidf2_internal"
(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
(clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
- "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
+ "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"#"
""
[(pc)]
@@ -5342,19 +5331,12 @@ (define_expand "floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
- && (!TARGET_FPRS
- || (TARGET_FPRS
- && ((TARGET_FCFIDUS && TARGET_LFIWZX)
- || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
- && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
+ && ((TARGET_FCFIDUS && TARGET_LFIWZX)
+ || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
+ && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
"
{
- if (!TARGET_FPRS)
- {
- if (!REG_P (operands[1]))
- operands[1] = force_reg (SImode, operands[1]);
- }
- else if (TARGET_LFIWZX && TARGET_FCFIDUS)
+ if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
DONE;
@@ -5377,8 +5359,7 @@ (define_expand "floatunssidf2"
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
- "TARGET_HARD_FLOAT
- && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
+ "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
"
{
if (TARGET_E500_DOUBLE)
@@ -5418,7 +5399,7 @@ (define_insn_and_split "*floatunssidf2_internal"
(use (match_operand:DF 3 "gpc_reg_operand" "d"))
(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
- "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+ "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& !(TARGET_FCFID && TARGET_POWERPC64)"
"#"
""
@@ -5551,7 +5532,7 @@ (define_insn_and_split "*floatuns<QHI:mode><FP_ISA3:mode>2_internal"
(define_expand "fix_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
+ "TARGET_HARD_FLOAT && (<TARGET_FLOAT> || <E500_CONVERT>)"
"
{
if (!<E500_CONVERT> && !TARGET_VSX_SMALL_INTEGER)
@@ -5578,7 +5559,7 @@ (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DI 2 "=d"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
&& TARGET_STFIWX && can_create_pseudo_p ()
&& !TARGET_VSX_SMALL_INTEGER"
@@ -5622,8 +5603,7 @@ (define_insn_and_split "fix_trunc<mode>si2_internal"
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
- && !TARGET_VSX_SMALL_INTEGER"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_VSX_SMALL_INTEGER"
"#"
""
[(pc)]
@@ -5644,15 +5624,13 @@ (define_insn_and_split "fix_trunc<mode>si2_internal"
(define_expand "fix_trunc<mode>di2"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
- && TARGET_FCFID"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID"
"")
(define_insn "*fix_trunc<mode>di2_fctidz"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
(fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
- && TARGET_FCFID"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID"
"@
fctidz %0,%1
xscvdpsxds %x0,%x1"
@@ -5703,8 +5681,7 @@ (define_expand "fixuns_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT
- && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
- || <E500_CONVERT>)"
+ && ((<TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX) || <E500_CONVERT>)"
"
{
if (!<E500_CONVERT> && !TARGET_VSX_SMALL_INTEGER)
@@ -5718,7 +5695,7 @@ (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DI 2 "=d"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
+ "TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ
&& TARGET_STFIWX && can_create_pseudo_p ()
&& !TARGET_VSX_SMALL_INTEGER"
"#"
@@ -5759,7 +5736,7 @@ (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
(define_insn "fixuns_trunc<mode>di2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
(unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCTIDUZ"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCTIDUZ"
"@
fctiduz %0,%1
xscvdpuxds %x0,%x1"
@@ -5812,8 +5789,7 @@ (define_insn_and_split "*fixuns_trunc<SFDF:mode><QHI:mode>2_internal"
(define_insn "*fctiw<u>z_<mode>_smallint"
[(set (match_operand:SI 0 "vsx_register_operand" "=d,wi")
(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_VSX_SMALL_INTEGER"
"@
fctiw<u>z %0,%1
xscvdp<su>xws %x0,%x1"
@@ -5825,8 +5801,7 @@ (define_insn_and_split "*fctiw<u>z_<mode>_mem"
[(set (match_operand:SI 0 "memory_operand" "=Z")
(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "wa")))
(clobber (match_scratch:SI 2 "=wa"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_VSX_SMALL_INTEGER"
"#"
"&& reload_completed"
[(set (match_dup 2)
@@ -5843,7 +5818,7 @@ (define_insn "fctiwz_<mode>"
(unspec:DI [(fix:SI
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
UNSPEC_FCTIWZ))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
fctiwz %0,%1
xscvdpsxws %x0,%x1"
@@ -5854,7 +5829,7 @@ (define_insn "fctiwuz_<mode>"
(unspec:DI [(unsigned_fix:SI
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
UNSPEC_FCTIWUZ))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
+ "TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ"
"@
fctiwuz %0,%1
xscvdpuxws %x0,%x1"
@@ -5866,7 +5841,7 @@ (define_insn "fctiwuz_<mode>"
(define_insn "*friz"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRND
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
"@
friz %0,%1
@@ -5885,7 +5860,7 @@ (define_insn_and_split "*round32<mode>2_fprs"
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
(clobber (match_scratch:DI 2 "=d"))
(clobber (match_scratch:DI 3 "=d"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
&& !TARGET_DIRECT_MOVE && can_create_pseudo_p ()"
"#"
@@ -5918,7 +5893,7 @@ (define_insn_and_split "*roundu32<mode>2_fprs"
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
(clobber (match_scratch:DI 2 "=d"))
(clobber (match_scratch:DI 3 "=d"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU && !TARGET_DIRECT_MOVE
&& can_create_pseudo_p ()"
"#"
@@ -6038,19 +6013,12 @@ (define_expand "floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
- && (!TARGET_FPRS
- || (TARGET_FPRS
- && ((TARGET_FCFIDS && TARGET_LFIWAX)
- || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
- && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
+ && ((TARGET_FCFIDS && TARGET_LFIWAX)
+ || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
+ && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
"
{
- if (!TARGET_FPRS)
- {
- if (!REG_P (operands[1]))
- operands[1] = force_reg (SImode, operands[1]);
- }
- else if (TARGET_FCFIDS && TARGET_LFIWAX)
+ if (TARGET_FCFIDS && TARGET_LFIWAX)
{
emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
DONE;
@@ -6073,16 +6041,10 @@ (define_expand "floatsisf2"
}
}")
-(define_expand "floatdidf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
- "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
- "")
-
-(define_insn "*floatdidf2_fpr"
+(define_insn "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
- "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
+ "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
fcfid %0,%1
xscvsxddp %x0,%x1"
@@ -6097,7 +6059,7 @@ (define_insn_and_split "*floatdidf2_mem"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
(clobber (match_scratch:DI 2 "=d,wi"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID"
"#"
"&& reload_completed"
[(set (match_dup 2) (match_dup 1))
@@ -6139,7 +6101,7 @@ (define_insn_and_split "*floatunsdidf2_mem"
(define_expand "floatdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
- "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
+ "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
"
{
@@ -6161,7 +6123,7 @@ (define_expand "floatdisf2"
(define_insn "floatdisf2_fcfids"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
+ "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
"@
fcfids %0,%1
@@ -6172,7 +6134,7 @@ (define_insn_and_split "*floatdisf2_mem"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
(float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
(clobber (match_scratch:DI 2 "=d,d,wi"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
+ "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
"#"
"&& reload_completed"
@@ -6193,8 +6155,7 @@ (define_insn_and_split "floatdisf2_internal1"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DF 2 "=d"))]
- "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
- && !TARGET_FCFIDS"
+ "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_FCFIDS"
"#"
"&& reload_completed"
[(set (match_dup 2)
@@ -6229,7 +6190,7 @@ (define_expand "floatdisf2_internal2"
(label_ref (match_operand:DI 2 "" ""))
(pc)))
(set (match_dup 0) (match_dup 1))]
- "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& !TARGET_FCFIDS"
"
{
@@ -6240,14 +6201,14 @@ (define_expand "floatdisf2_internal2"
(define_expand "floatunsdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
+ "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
"")
(define_insn "floatunsdisf2_fcfidus"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wu")
(unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
+ "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
"@
fcfidus %0,%1
@@ -6258,7 +6219,7 @@ (define_insn_and_split "*floatunsdisf2_mem"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
(unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
(clobber (match_scratch:DI 2 "=d,d,wi"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
+ "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
"#"
"&& reload_completed"
@@ -7209,7 +7170,7 @@ (define_insn "movsf_hardfloat"
r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
+ && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& (TARGET_ALLOW_SF_SUBREG
|| valid_sf_si_move (operands[0], operands[1], SFmode))"
"@
@@ -7245,7 +7206,7 @@ (define_insn "movsd_hardfloat"
f, r, r, *h, 0"))]
"(register_operand (operands[0], SDmode)
|| register_operand (operands[1], SDmode))
- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
+ && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
"@
lwz%U1%X1 %0,%1
lfiwzx %0,%y1
@@ -7267,7 +7228,7 @@ (define_insn "*mov<mode>_softfloat"
(match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
"(gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))
- && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
+ && TARGET_SOFT_FLOAT"
"@
mr %0,%1
mt%0 %1
@@ -7446,7 +7407,7 @@ (define_split
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_p9>,wY,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,wY,<f64_p9>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
- "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+ "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"@
@@ -7471,8 +7432,7 @@ (define_insn "*mov<mode>_softfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
(match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
"! TARGET_POWERPC64
- && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
- || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
+ && (TARGET_SINGLE_FLOAT || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
|| (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7485,7 +7445,7 @@ (define_insn "*mov<mode>_softfloat32"
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>")
(match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))]
- "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"@
@@ -7516,7 +7476,7 @@ (define_insn "*mov<mode>_hardfloat64"
(define_insn "*mov<mode>_softfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
(match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
- "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
+ "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"@
@@ -7549,8 +7509,7 @@ (define_expand "mov<mode>"
(define_insn_and_split "*mov<mode>_64bit_dm"
[(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r,r,wh")
(match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r,wh,r"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
- && FLOAT128_2REG_P (<MODE>mode)
+ "TARGET_HARD_FLOAT && TARGET_POWERPC64 && FLOAT128_2REG_P (<MODE>mode)
&& (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7563,7 +7522,7 @@ (define_insn_and_split "*mov<mode>_64bit_dm"
(define_insn_and_split "*movtd_64bit_nodm"
[(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
(match_operand:TD 1 "input_operand" "d,m,d,r,Y,r"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
+ "TARGET_HARD_FLOAT && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
&& (gpc_reg_operand (operands[0], TDmode)
|| gpc_reg_operand (operands[1], TDmode))"
"#"
@@ -7575,7 +7534,7 @@ (define_insn_and_split "*movtd_64bit_nodm"
(define_insn_and_split "*mov<mode>_32bit"
[(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r")
(match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
+ "TARGET_HARD_FLOAT && !TARGET_POWERPC64
&& (FLOAT128_2REG_P (<MODE>mode)
|| int_reg_operand_not_pseudo (operands[0], <MODE>mode)
|| int_reg_operand_not_pseudo (operands[1], <MODE>mode))
@@ -7590,7 +7549,7 @@ (define_insn_and_split "*mov<mode>_32bit"
(define_insn_and_split "*mov<mode>_softfloat"
[(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
(match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
- "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
+ "TARGET_SOFT_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"#"
@@ -7602,8 +7561,7 @@ (define_insn_and_split "*mov<mode>_softfloat"
(define_expand "extenddf<mode>2"
[(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
(float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)
- && TARGET_LONG_DOUBLE_128"
+ "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
rs6000_expand_float128_convert (operands[0], operands[1], false);
@@ -7642,7 +7600,7 @@ (define_insn_and_split "extenddf<mode>2_fprs"
(float_extend:IBM128
(match_operand:DF 1 "nonimmediate_operand" "d,m,d")))
(use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))]
- "!TARGET_VSX && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+ "!TARGET_VSX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
"#"
"&& reload_completed"
@@ -7677,9 +7635,7 @@ (define_insn_and_split "extenddf<mode>2_vsx"
(define_expand "extendsf<mode>2"
[(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
(float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT
- && (TARGET_FPRS || TARGET_E500_DOUBLE)
- && TARGET_LONG_DOUBLE_128"
+ "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
rs6000_expand_float128_convert (operands[0], operands[1], false);
@@ -7695,9 +7651,7 @@ (define_expand "extendsf<mode>2"
(define_expand "trunc<mode>df2"
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT
- && (TARGET_FPRS || TARGET_E500_DOUBLE)
- && TARGET_LONG_DOUBLE_128"
+ "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
{
@@ -7711,7 +7665,7 @@ (define_insn_and_split "trunc<mode>df2_internal1"
(float_truncate:DF
(match_operand:IBM128 1 "gpc_reg_operand" "0,d")))]
"FLOAT128_IBM_P (<MODE>mode) && !TARGET_XL_COMPAT
- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
+ && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"@
#
fmr %0,%1"
@@ -7727,7 +7681,7 @@ (define_insn "trunc<mode>df2_internal2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(float_truncate:DF (match_operand:IBM128 1 "gpc_reg_operand" "d")))]
"FLOAT128_IBM_P (<MODE>mode) && TARGET_XL_COMPAT && TARGET_HARD_FLOAT
- && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
+ && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
"fadd %0,%1,%L1"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_addsub_d")])
@@ -7735,9 +7689,7 @@ (define_insn "trunc<mode>df2_internal2"
(define_expand "trunc<mode>sf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT
- && (TARGET_FPRS || TARGET_E500_DOUBLE)
- && TARGET_LONG_DOUBLE_128"
+ "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
rs6000_expand_float128_convert (operands[0], operands[1], false);
@@ -7759,7 +7711,7 @@ (define_insn_and_split "trunc<mode>sf2_fprs"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:IBM128 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DF 2 "=d"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
+ "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
"#"
"&& reload_completed"
@@ -7773,9 +7725,7 @@ (define_expand "floatsi<mode>2"
[(parallel [(set (match_operand:FLOAT128 0 "gpc_reg_operand")
(float:FLOAT128 (match_operand:SI 1 "gpc_reg_operand")))
(clobber (match_scratch:DI 2))])]
- "TARGET_HARD_FLOAT
- && (TARGET_FPRS || TARGET_E500_DOUBLE)
- && TARGET_LONG_DOUBLE_128"
+ "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
rtx op0 = operands[0];
rtx op1 = operands[1];
@@ -7808,8 +7758,7 @@ (define_insn "fix_trunc_helper<mode>"
(unspec:DF [(match_operand:IBM128 1 "gpc_reg_operand" "d")]
UNSPEC_FIX_TRUNC_TF))
(clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
- && FLOAT128_IBM_P (<MODE>mode)"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && FLOAT128_IBM_P (<MODE>mode)"
"mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
[(set_attr "type" "fp")
(set_attr "length" "20")])
@@ -7817,8 +7766,7 @@ (define_insn "fix_trunc_helper<mode>"
(define_expand "fix_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT
- && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
+ "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
rtx op0 = operands[0];
rtx op1 = operands[1];
@@ -7848,7 +7796,7 @@ (define_expand "fix_trunc<mode>si2_fprs"
(clobber (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
+ "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
operands[2] = gen_reg_rtx (DFmode);
operands[3] = gen_reg_rtx (DFmode);
@@ -7863,7 +7811,7 @@ (define_insn_and_split "*fix_trunc<mode>si2_internal"
(clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
(clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
(clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
+ "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
""
[(pc)]
@@ -7945,9 +7893,7 @@ (define_expand "neg<mode>2"
[(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
(neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"FLOAT128_IEEE_P (<MODE>mode)
- || (FLOAT128_IBM_P (<MODE>mode)
- && TARGET_HARD_FLOAT
- && (TARGET_FPRS || TARGET_E500_DOUBLE))"
+ || (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
"
{
if (FLOAT128_IEEE_P (<MODE>mode))
@@ -7987,7 +7933,7 @@ (define_expand "neg<mode>2"
(define_insn "neg<mode>2_internal"
[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d")
(neg:IBM128 (match_operand:IBM128 1 "gpc_reg_operand" "d")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && FLOAT128_IBM_P (TFmode)"
+ "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
"*
{
if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
@@ -8002,9 +7948,7 @@ (define_expand "abs<mode>2"
[(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
(abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"FLOAT128_IEEE_P (<MODE>mode)
- || (FLOAT128_IBM_P (<MODE>mode)
- && TARGET_HARD_FLOAT
- && (TARGET_FPRS || TARGET_E500_DOUBLE))"
+ || (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
"
{
rtx label;
@@ -8063,8 +8007,7 @@ (define_expand "abs<mode>2_internal"
(label_ref (match_operand 2 "" ""))
(pc)))
(set (match_dup 6) (neg:DF (match_dup 6)))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
- && TARGET_LONG_DOUBLE_128"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
"
{
const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
@@ -9750,7 +9693,7 @@ (define_insn "*movsf_update1"
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
+ "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
@@ -9766,7 +9709,7 @@ (define_insn "*movsf_update2"
(match_operand:SF 3 "gpc_reg_operand" "f,f"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
+ "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
@@ -9782,7 +9725,7 @@ (define_insn "*movsf_update3"
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
+ "TARGET_SOFT_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
@@ -9798,7 +9741,7 @@ (define_insn "*movsf_update4"
(match_operand:SF 3 "gpc_reg_operand" "r,r"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
+ "TARGET_SOFT_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
@@ -9814,7 +9757,7 @@ (define_insn "*movdf_update1"
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
@@ -9831,7 +9774,7 @@ (define_insn "*movdf_update2"
(match_operand:DF 3 "gpc_reg_operand" "d,d"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
@@ -12057,7 +12000,7 @@ (define_insn "*cmp<mode>_internal1"
(compare:CCFP (match_operand:IBM128 1 "gpc_reg_operand" "d")
(match_operand:IBM128 2 "gpc_reg_operand" "d")))]
"!TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode)
- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
+ && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
"fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
[(set_attr "type" "fpcompare")
(set_attr "length" "12")])
@@ -12076,7 +12019,7 @@ (define_insn_and_split "*cmp<mode>_internal2"
(clobber (match_scratch:DF 10 "=d"))
(clobber (match_scratch:GPR 11 "=b"))]
"TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode)
- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
+ && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
"&& reload_completed"
[(set (match_dup 3) (match_dup 14))
@@ -12144,15 +12087,6 @@ (define_insn ""
(const_string "mfcr")))
(set_attr "length" "8")])
-;; Same as above, but get the GT bit.
-(define_insn "move_from_CR_gt_bit"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "mfcr %0\;rlwinm %0,%0,%D1,31,31"
- [(set_attr "type" "mfcr")
- (set_attr "length" "8")])
-
;; Same as above, but get the OV/ORDERED bit.
(define_insn "move_from_CR_ov_bit"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -13822,14 +13756,14 @@ (define_insn "rs6000_mftb_<mode>"
(define_insn "rs6000_mffs"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_HARD_FLOAT"
"mffs %0")
(define_insn "rs6000_mtfsf"
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
(match_operand:DF 1 "gpc_reg_operand" "d")]
UNSPECV_MTFSF)]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_HARD_FLOAT"
"mtfsf %0,%1")
\f
diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md
index 2351152..b6f4e0a 100644
--- a/gcc/config/rs6000/spe.md
+++ b/gcc/config/rs6000/spe.md
@@ -31,7 +31,6 @@ (define_constants
(TSTTFGT_GPR 1015)
(CMPTFLT_GPR 1016)
(TSTTFLT_GPR 1017)
- (E500_CR_IOR_COMPARE 1018)
])
;; Modes using a 64-bit register.
@@ -43,59 +42,6 @@ (define_mode_iterator SPE64TF [DF V4HI V2SF V1DI V2SI TF])
;; DImode and TImode.
(define_mode_iterator DITI [DI TI])
-(define_insn "*negsf2_gpr"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "efsneg %0,%1"
- [(set_attr "type" "fpsimple")])
-
-(define_insn "*abssf2_gpr"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "efsabs %0,%1"
- [(set_attr "type" "fpsimple")])
-
-(define_insn "*nabssf2_gpr"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "efsnabs %0,%1"
- [(set_attr "type" "fpsimple")])
-
-(define_insn "*addsf3_gpr"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
- (match_operand:SF 2 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "efsadd %0,%1,%2"
- [(set_attr "type" "fp")])
-
-(define_insn "*subsf3_gpr"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
- (match_operand:SF 2 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "efssub %0,%1,%2"
- [(set_attr "type" "fp")])
-
-(define_insn "*mulsf3_gpr"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
- (match_operand:SF 2 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "efsmul %0,%1,%2"
- [(set_attr "type" "fp")])
-
-(define_insn "*divsf3_gpr"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (div:SF (match_operand:SF 1 "gpc_reg_operand" "r")
- (match_operand:SF 2 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "efsdiv %0,%1,%2"
- [(set_attr "type" "vecfdiv")])
-
;; Floating point conversion instructions.
(define_insn "spe_fixuns_truncdfsi2"
@@ -112,20 +58,6 @@ (define_insn "spe_extendsfdf2"
"efdcfs %0,%1"
[(set_attr "type" "fp")])
-(define_insn "spe_fixuns_truncsfsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "efsctuiz %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "spe_fix_truncsfsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "efsctsiz %0,%1"
- [(set_attr "type" "fp")])
-
(define_insn "spe_fix_truncdfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
@@ -133,13 +65,6 @@ (define_insn "spe_fix_truncdfsi2"
"efdctsiz %0,%1"
[(set_attr "type" "fp")])
-(define_insn "spe_floatunssisf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "efscfui %0,%1"
- [(set_attr "type" "fp")])
-
(define_insn "spe_floatunssidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
@@ -147,13 +72,6 @@ (define_insn "spe_floatunssidf2"
"efdcfui %0,%1"
[(set_attr "type" "fp")])
-(define_insn "spe_floatsisf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "efscfsi %0,%1"
- [(set_attr "type" "fp")])
-
(define_insn "spe_floatsidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
@@ -3233,88 +3151,10 @@ (define_insn "spe_mfspefscr"
"mfspefscr %0"
[(set_attr "type" "vecsimple")])
-;; Flip the GT bit.
-(define_insn "e500_flip_gt_bit"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
- "!TARGET_FPRS && TARGET_HARD_FLOAT"
- "*
-{
- return output_e500_flip_gt_bit (operands[0], operands[1]);
-}"
- [(set_attr "type" "cr_logical")])
-
;; MPC8540 single-precision FP instructions on GPRs.
;; We have 2 variants for each. One for IEEE compliant math and one
;; for non IEEE compliant math.
-(define_insn "cmpsfeq_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
- (match_operand:SF 2 "gpc_reg_operand" "r"))]
- 1000))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efscmpeq %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
-(define_insn "tstsfeq_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
- (match_operand:SF 2 "gpc_reg_operand" "r"))]
- 1001))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS
- && flag_finite_math_only && !flag_trapping_math"
- "efststeq %0,%1,%2"
- [(set_attr "type" "veccmpsimple")])
-
-(define_insn "cmpsfgt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
- (match_operand:SF 2 "gpc_reg_operand" "r"))]
- 1002))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efscmpgt %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
-(define_insn "tstsfgt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
- (match_operand:SF 2 "gpc_reg_operand" "r"))]
- 1003))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS
- && flag_finite_math_only && !flag_trapping_math"
- "efststgt %0,%1,%2"
- [(set_attr "type" "veccmpsimple")])
-
-(define_insn "cmpsflt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
- (match_operand:SF 2 "gpc_reg_operand" "r"))]
- 1004))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efscmplt %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
-(define_insn "tstsflt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
- (match_operand:SF 2 "gpc_reg_operand" "r"))]
- 1005))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS
- && flag_finite_math_only && !flag_trapping_math"
- "efststlt %0,%1,%2"
- [(set_attr "type" "veccmpsimple")])
-
;; Same thing, but for double-precision.
(define_insn "cmpdfeq_gpr"
@@ -3463,16 +3303,6 @@ (define_insn "tsttflt_gpr"
[(set_attr "type" "veccmpsimple")
(set_attr "length" "20")])
-;; Like cceq_ior_compare, but compare the GT bits.
-(define_insn "e500_cr_ior_compare"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
- (match_operand 2 "cc_reg_operand" "y")]
- E500_CR_IOR_COMPARE))]
- "TARGET_HARD_FLOAT && !TARGET_FPRS"
- "cror 4*%0+gt,4*%1+gt,4*%2+gt"
- [(set_attr "type" "cr_logical")])
-
;; Out-of-line prologues and epilogues.
(define_insn "*save_gpregs_spe"
[(match_parallel 0 "any_parallel_operand"
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b669764..141aa42 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1984,7 +1984,7 @@ (define_insn "*vsx_float_fix_v2df2"
(float:V2DF
(fix:V2DI
(match_operand:V2DF 1 "vsx_register_operand" "wd,?wa"))))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& VECTOR_UNIT_VSX_P (V2DFmode) && flag_unsafe_math_optimizations
&& !flag_trapping_math && TARGET_FRIZ"
"xvrdpiz %x0,%x1"
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 10/14] rs6000: Remove spe.md, spe.h, linuxspe.h
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
` (11 preceding siblings ...)
2017-06-06 15:58 ` [PATCH 13/14] rs6000: Remove spe_acc and spefscr Segher Boessenkool
@ 2017-06-06 15:58 ` Segher Boessenkool
2017-06-06 17:06 ` David Edelsohn
2017-06-06 15:59 ` [PATCH 14/14] rs6000: Remove rs6000_nonimmediate_operand Segher Boessenkool
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:58 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config.gcc (powerpc*-*-*): Don't add spe.h to extra_headers.
(powerpc*-linux*spe*): Use ${cpu_type} instead of rs6000.
* config/rs6000/linuxspe.h: Delete file.
* config/rs6000/rs6000.md: Don't include spe.md.
* config/rs6000/spe.h: Delete file.
* config/rs6000/spe.md: Delete file.
* config/rs6000/t-rs6000: Remove spe.md.
---
gcc/config.gcc | 4 +-
gcc/config/rs6000/linuxspe.h | 32 --
gcc/config/rs6000/rs6000.md | 1 -
gcc/config/rs6000/spe.h | 1107 ------------------------------------------
gcc/config/rs6000/spe.md | 28 --
gcc/config/rs6000/t-rs6000 | 1 -
6 files changed, 2 insertions(+), 1171 deletions(-)
delete mode 100644 gcc/config/rs6000/linuxspe.h
delete mode 100644 gcc/config/rs6000/spe.h
delete mode 100644 gcc/config/rs6000/spe.md
diff --git a/gcc/config.gcc b/gcc/config.gcc
index f55dcaa..a311cd95 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -457,7 +457,7 @@ powerpc*-*-*)
extra_headers="ppc-asm.h altivec.h htmintrin.h htmxlintrin.h"
extra_headers="${extra_headers} bmi2intrin.h bmiintrin.h x86intrin.h"
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h"
- extra_headers="${extra_headers} spe.h paired.h"
+ extra_headers="${extra_headers} paired.h"
case x$with_cpu in
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
cpu_is_64bit=yes
@@ -2510,7 +2510,7 @@ powerpc*-*-linux*)
powerpc*-*-linux*altivec*)
tm_file="${tm_file} rs6000/linuxaltivec.h" ;;
powerpc*-*-linux*spe*)
- tm_file="${tm_file} rs6000/linuxspe.h rs6000/e500.h" ;;
+ tm_file="${tm_file} ${cpu_type}/linuxspe.h ${cpu_type}/e500.h" ;;
powerpc*-*-linux*paired*)
tm_file="${tm_file} rs6000/750cl.h" ;;
esac
diff --git a/gcc/config/rs6000/linuxspe.h b/gcc/config/rs6000/linuxspe.h
deleted file mode 100644
index 92efabf..0000000
--- a/gcc/config/rs6000/linuxspe.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Definitions of target machine for GNU compiler,
- for PowerPC e500 machines running GNU/Linux.
- Copyright (C) 2003-2017 Free Software Foundation, Inc.
- Contributed by Aldy Hernandez (aldy@quesejoda.com).
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>. */
-
-/* Override rs6000.h and sysv4.h definition. */
-#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_STRICT_ALIGN | MASK_LITTLE_ENDIAN)
-#else
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT MASK_STRICT_ALIGN
-#endif
-
-#undef ASM_DEFAULT_SPEC
-#define ASM_DEFAULT_SPEC "-mppc -mspe -me500"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index edb5208..ec25f45 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -14629,7 +14629,6 @@ (define_insn "*cmp<mode>_hw"
(include "vector.md")
(include "vsx.md")
(include "altivec.md")
-(include "spe.md")
(include "dfp.md")
(include "paired.md")
(include "crypto.md")
diff --git a/gcc/config/rs6000/spe.h b/gcc/config/rs6000/spe.h
deleted file mode 100644
index 3d556c0..0000000
--- a/gcc/config/rs6000/spe.h
+++ /dev/null
@@ -1,1107 +0,0 @@
-/* PowerPC E500 user include file.
- Copyright (C) 2002-2017 Free Software Foundation, Inc.
- Contributed by Aldy Hernandez (aldyh@redhat.com).
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- Under Section 7 of GPL version 3, you are granted additional
- permissions described in the GCC Runtime Library Exception, version
- 3.1, as published by the Free Software Foundation.
-
- You should have received a copy of the GNU General Public License and
- a copy of the GCC Runtime Library Exception along with this program;
- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#ifndef _SPE_H
-#define _SPE_H
-
-#define __vector __attribute__((vector_size(8)))
-
-typedef int int32_t;
-typedef unsigned uint32_t;
-typedef short int16_t;
-typedef unsigned short uint16_t;
-typedef long long int64_t;
-typedef unsigned long long uint64_t;
-
-typedef short __vector __ev64_s16__;
-typedef unsigned short __vector __ev64_u16__;
-typedef int __vector __ev64_s32__;
-typedef unsigned __vector __ev64_u32__;
-typedef long long __vector __ev64_s64__;
-typedef unsigned long long __vector __ev64_u64__;
-typedef float __vector __ev64_fs__;
-
-#define __v2si __ev64_opaque__
-#define __v2sf __ev64_fs__
-
-#define __ev_addw __builtin_spe_evaddw
-#define __ev_addiw __builtin_spe_evaddiw
-#define __ev_subfw(a,b) __builtin_spe_evsubfw ((b), (a))
-#define __ev_subw __builtin_spe_evsubfw
-#define __ev_subifw(a,b) __builtin_spe_evsubifw ((b), (a))
-#define __ev_subiw __builtin_spe_evsubifw
-#define __ev_abs __builtin_spe_evabs
-#define __ev_neg __builtin_spe_evneg
-#define __ev_extsb __builtin_spe_evextsb
-#define __ev_extsh __builtin_spe_evextsh
-#define __ev_and __builtin_spe_evand
-#define __ev_or __builtin_spe_evor
-#define __ev_xor __builtin_spe_evxor
-#define __ev_nand __builtin_spe_evnand
-#define __ev_nor __builtin_spe_evnor
-#define __ev_eqv __builtin_spe_eveqv
-#define __ev_andc __builtin_spe_evandc
-#define __ev_orc __builtin_spe_evorc
-#define __ev_rlw __builtin_spe_evrlw
-#define __ev_rlwi __builtin_spe_evrlwi
-#define __ev_slw __builtin_spe_evslw
-#define __ev_slwi __builtin_spe_evslwi
-#define __ev_srws __builtin_spe_evsrws
-#define __ev_srwu __builtin_spe_evsrwu
-#define __ev_srwis __builtin_spe_evsrwis
-#define __ev_srwiu __builtin_spe_evsrwiu
-#define __ev_cntlzw __builtin_spe_evcntlzw
-#define __ev_cntlsw __builtin_spe_evcntlsw
-#define __ev_rndw __builtin_spe_evrndw
-#define __ev_mergehi __builtin_spe_evmergehi
-#define __ev_mergelo __builtin_spe_evmergelo
-#define __ev_mergelohi __builtin_spe_evmergelohi
-#define __ev_mergehilo __builtin_spe_evmergehilo
-#define __ev_splati __builtin_spe_evsplati
-#define __ev_splatfi __builtin_spe_evsplatfi
-#define __ev_divws __builtin_spe_evdivws
-#define __ev_divwu __builtin_spe_evdivwu
-#define __ev_mra __builtin_spe_evmra
-
-#define __brinc __builtin_spe_brinc
-
-/* Loads. */
-
-#define __ev_lddx __builtin_spe_evlddx
-#define __ev_ldwx __builtin_spe_evldwx
-#define __ev_ldhx __builtin_spe_evldhx
-#define __ev_lwhex __builtin_spe_evlwhex
-#define __ev_lwhoux __builtin_spe_evlwhoux
-#define __ev_lwhosx __builtin_spe_evlwhosx
-#define __ev_lwwsplatx __builtin_spe_evlwwsplatx
-#define __ev_lwhsplatx __builtin_spe_evlwhsplatx
-#define __ev_lhhesplatx __builtin_spe_evlhhesplatx
-#define __ev_lhhousplatx __builtin_spe_evlhhousplatx
-#define __ev_lhhossplatx __builtin_spe_evlhhossplatx
-#define __ev_ldd __builtin_spe_evldd
-#define __ev_ldw __builtin_spe_evldw
-#define __ev_ldh __builtin_spe_evldh
-#define __ev_lwhe __builtin_spe_evlwhe
-#define __ev_lwhou __builtin_spe_evlwhou
-#define __ev_lwhos __builtin_spe_evlwhos
-#define __ev_lwwsplat __builtin_spe_evlwwsplat
-#define __ev_lwhsplat __builtin_spe_evlwhsplat
-#define __ev_lhhesplat __builtin_spe_evlhhesplat
-#define __ev_lhhousplat __builtin_spe_evlhhousplat
-#define __ev_lhhossplat __builtin_spe_evlhhossplat
-
-/* Stores. */
-
-#define __ev_stddx __builtin_spe_evstddx
-#define __ev_stdwx __builtin_spe_evstdwx
-#define __ev_stdhx __builtin_spe_evstdhx
-#define __ev_stwwex __builtin_spe_evstwwex
-#define __ev_stwwox __builtin_spe_evstwwox
-#define __ev_stwhex __builtin_spe_evstwhex
-#define __ev_stwhox __builtin_spe_evstwhox
-#define __ev_stdd __builtin_spe_evstdd
-#define __ev_stdw __builtin_spe_evstdw
-#define __ev_stdh __builtin_spe_evstdh
-#define __ev_stwwe __builtin_spe_evstwwe
-#define __ev_stwwo __builtin_spe_evstwwo
-#define __ev_stwhe __builtin_spe_evstwhe
-#define __ev_stwho __builtin_spe_evstwho
-
-/* Fixed point complex. */
-
-#define __ev_mhossf __builtin_spe_evmhossf
-#define __ev_mhosmf __builtin_spe_evmhosmf
-#define __ev_mhosmi __builtin_spe_evmhosmi
-#define __ev_mhoumi __builtin_spe_evmhoumi
-#define __ev_mhessf __builtin_spe_evmhessf
-#define __ev_mhesmf __builtin_spe_evmhesmf
-#define __ev_mhesmi __builtin_spe_evmhesmi
-#define __ev_mheumi __builtin_spe_evmheumi
-#define __ev_mhossfa __builtin_spe_evmhossfa
-#define __ev_mhosmfa __builtin_spe_evmhosmfa
-#define __ev_mhosmia __builtin_spe_evmhosmia
-#define __ev_mhoumia __builtin_spe_evmhoumia
-#define __ev_mhessfa __builtin_spe_evmhessfa
-#define __ev_mhesmfa __builtin_spe_evmhesmfa
-#define __ev_mhesmia __builtin_spe_evmhesmia
-#define __ev_mheumia __builtin_spe_evmheumia
-
-#define __ev_mhoumf __ev_mhoumi
-#define __ev_mheumf __ev_mheumi
-#define __ev_mhoumfa __ev_mhoumia
-#define __ev_mheumfa __ev_mheumia
-
-#define __ev_mhossfaaw __builtin_spe_evmhossfaaw
-#define __ev_mhossiaaw __builtin_spe_evmhossiaaw
-#define __ev_mhosmfaaw __builtin_spe_evmhosmfaaw
-#define __ev_mhosmiaaw __builtin_spe_evmhosmiaaw
-#define __ev_mhousiaaw __builtin_spe_evmhousiaaw
-#define __ev_mhoumiaaw __builtin_spe_evmhoumiaaw
-#define __ev_mhessfaaw __builtin_spe_evmhessfaaw
-#define __ev_mhessiaaw __builtin_spe_evmhessiaaw
-#define __ev_mhesmfaaw __builtin_spe_evmhesmfaaw
-#define __ev_mhesmiaaw __builtin_spe_evmhesmiaaw
-#define __ev_mheusiaaw __builtin_spe_evmheusiaaw
-#define __ev_mheumiaaw __builtin_spe_evmheumiaaw
-
-#define __ev_mhousfaaw __ev_mhousiaaw
-#define __ev_mhoumfaaw __ev_mhoumiaaw
-#define __ev_mheusfaaw __ev_mheusiaaw
-#define __ev_mheumfaaw __ev_mheumiaaw
-
-#define __ev_mhossfanw __builtin_spe_evmhossfanw
-#define __ev_mhossianw __builtin_spe_evmhossianw
-#define __ev_mhosmfanw __builtin_spe_evmhosmfanw
-#define __ev_mhosmianw __builtin_spe_evmhosmianw
-#define __ev_mhousianw __builtin_spe_evmhousianw
-#define __ev_mhoumianw __builtin_spe_evmhoumianw
-#define __ev_mhessfanw __builtin_spe_evmhessfanw
-#define __ev_mhessianw __builtin_spe_evmhessianw
-#define __ev_mhesmfanw __builtin_spe_evmhesmfanw
-#define __ev_mhesmianw __builtin_spe_evmhesmianw
-#define __ev_mheusianw __builtin_spe_evmheusianw
-#define __ev_mheumianw __builtin_spe_evmheumianw
-
-#define __ev_mhousfanw __ev_mhousianw
-#define __ev_mhoumfanw __ev_mhoumianw
-#define __ev_mheusfanw __ev_mheusianw
-#define __ev_mheumfanw __ev_mheumianw
-
-#define __ev_mhogsmfaa __builtin_spe_evmhogsmfaa
-#define __ev_mhogsmiaa __builtin_spe_evmhogsmiaa
-#define __ev_mhogumiaa __builtin_spe_evmhogumiaa
-#define __ev_mhegsmfaa __builtin_spe_evmhegsmfaa
-#define __ev_mhegsmiaa __builtin_spe_evmhegsmiaa
-#define __ev_mhegumiaa __builtin_spe_evmhegumiaa
-
-#define __ev_mhogumfaa __ev_mhogumiaa
-#define __ev_mhegumfaa __ev_mhegumiaa
-
-#define __ev_mhogsmfan __builtin_spe_evmhogsmfan
-#define __ev_mhogsmian __builtin_spe_evmhogsmian
-#define __ev_mhogumian __builtin_spe_evmhogumian
-#define __ev_mhegsmfan __builtin_spe_evmhegsmfan
-#define __ev_mhegsmian __builtin_spe_evmhegsmian
-#define __ev_mhegumian __builtin_spe_evmhegumian
-
-#define __ev_mhogumfan __ev_mhogumian
-#define __ev_mhegumfan __ev_mhegumian
-
-#define __ev_mwhssf __builtin_spe_evmwhssf
-#define __ev_mwhsmf __builtin_spe_evmwhsmf
-#define __ev_mwhsmi __builtin_spe_evmwhsmi
-#define __ev_mwhumi __builtin_spe_evmwhumi
-#define __ev_mwhssfa __builtin_spe_evmwhssfa
-#define __ev_mwhsmfa __builtin_spe_evmwhsmfa
-#define __ev_mwhsmia __builtin_spe_evmwhsmia
-#define __ev_mwhumia __builtin_spe_evmwhumia
-
-#define __ev_mwhumf __ev_mwhumi
-#define __ev_mwhumfa __ev_mwhumia
-
-#define __ev_mwlumi __builtin_spe_evmwlumi
-#define __ev_mwlumia __builtin_spe_evmwlumia
-#define __ev_mwlumiaaw __builtin_spe_evmwlumiaaw
-
-#define __ev_mwlssiaaw __builtin_spe_evmwlssiaaw
-#define __ev_mwlsmiaaw __builtin_spe_evmwlsmiaaw
-#define __ev_mwlusiaaw __builtin_spe_evmwlusiaaw
-#define __ev_mwlusiaaw __builtin_spe_evmwlusiaaw
-
-#define __ev_mwlssianw __builtin_spe_evmwlssianw
-#define __ev_mwlsmianw __builtin_spe_evmwlsmianw
-#define __ev_mwlusianw __builtin_spe_evmwlusianw
-#define __ev_mwlumianw __builtin_spe_evmwlumianw
-
-#define __ev_mwssf __builtin_spe_evmwssf
-#define __ev_mwsmf __builtin_spe_evmwsmf
-#define __ev_mwsmi __builtin_spe_evmwsmi
-#define __ev_mwumi __builtin_spe_evmwumi
-#define __ev_mwssfa __builtin_spe_evmwssfa
-#define __ev_mwsmfa __builtin_spe_evmwsmfa
-#define __ev_mwsmia __builtin_spe_evmwsmia
-#define __ev_mwumia __builtin_spe_evmwumia
-
-#define __ev_mwumf __ev_mwumi
-#define __ev_mwumfa __ev_mwumia
-
-#define __ev_mwssfaa __builtin_spe_evmwssfaa
-#define __ev_mwsmfaa __builtin_spe_evmwsmfaa
-#define __ev_mwsmiaa __builtin_spe_evmwsmiaa
-#define __ev_mwumiaa __builtin_spe_evmwumiaa
-
-#define __ev_mwumfaa __ev_mwumiaa
-
-#define __ev_mwssfan __builtin_spe_evmwssfan
-#define __ev_mwsmfan __builtin_spe_evmwsmfan
-#define __ev_mwsmian __builtin_spe_evmwsmian
-#define __ev_mwumian __builtin_spe_evmwumian
-
-#define __ev_mwumfan __ev_mwumian
-
-#define __ev_addssiaaw __builtin_spe_evaddssiaaw
-#define __ev_addsmiaaw __builtin_spe_evaddsmiaaw
-#define __ev_addusiaaw __builtin_spe_evaddusiaaw
-#define __ev_addumiaaw __builtin_spe_evaddumiaaw
-
-#define __ev_addusfaaw __ev_addusiaaw
-#define __ev_addumfaaw __ev_addumiaaw
-#define __ev_addsmfaaw __ev_addsmiaaw
-#define __ev_addssfaaw __ev_addssiaaw
-
-#define __ev_subfssiaaw __builtin_spe_evsubfssiaaw
-#define __ev_subfsmiaaw __builtin_spe_evsubfsmiaaw
-#define __ev_subfusiaaw __builtin_spe_evsubfusiaaw
-#define __ev_subfumiaaw __builtin_spe_evsubfumiaaw
-
-#define __ev_subfusfaaw __ev_subfusiaaw
-#define __ev_subfumfaaw __ev_subfumiaaw
-#define __ev_subfsmfaaw __ev_subfsmiaaw
-#define __ev_subfssfaaw __ev_subfssiaaw
-
-/* Floating Point SIMD Instructions */
-
-#define __ev_fsabs __builtin_spe_evfsabs
-#define __ev_fsnabs __builtin_spe_evfsnabs
-#define __ev_fsneg __builtin_spe_evfsneg
-#define __ev_fsadd __builtin_spe_evfsadd
-#define __ev_fssub __builtin_spe_evfssub
-#define __ev_fsmul __builtin_spe_evfsmul
-#define __ev_fsdiv __builtin_spe_evfsdiv
-#define __ev_fscfui __builtin_spe_evfscfui
-#define __ev_fscfsi __builtin_spe_evfscfsi
-#define __ev_fscfuf __builtin_spe_evfscfuf
-#define __ev_fscfsf __builtin_spe_evfscfsf
-#define __ev_fsctui __builtin_spe_evfsctui
-#define __ev_fsctsi __builtin_spe_evfsctsi
-#define __ev_fsctuf __builtin_spe_evfsctuf
-#define __ev_fsctsf __builtin_spe_evfsctsf
-#define __ev_fsctuiz __builtin_spe_evfsctuiz
-#define __ev_fsctsiz __builtin_spe_evfsctsiz
-
-/* NOT SUPPORTED IN FIRST e500, support via two instructions: */
-
-#define __ev_mwhusfaaw __ev_mwhusiaaw
-#define __ev_mwhumfaaw __ev_mwhumiaaw
-#define __ev_mwhusfanw __ev_mwhusianw
-#define __ev_mwhumfanw __ev_mwhumianw
-#define __ev_mwhgumfaa __ev_mwhgumiaa
-#define __ev_mwhgumfan __ev_mwhgumian
-
-#define __ev_mwhgssfaa __internal_ev_mwhgssfaa
-#define __ev_mwhgsmfaa __internal_ev_mwhgsmfaa
-#define __ev_mwhgsmiaa __internal_ev_mwhgsmiaa
-#define __ev_mwhgumiaa __internal_ev_mwhgumiaa
-#define __ev_mwhgssfan __internal_ev_mwhgssfan
-#define __ev_mwhgsmfan __internal_ev_mwhgsmfan
-#define __ev_mwhgsmian __internal_ev_mwhgsmian
-#define __ev_mwhgumian __internal_ev_mwhgumian
-#define __ev_mwhssiaaw __internal_ev_mwhssiaaw
-#define __ev_mwhssfaaw __internal_ev_mwhssfaaw
-#define __ev_mwhsmfaaw __internal_ev_mwhsmfaaw
-#define __ev_mwhsmiaaw __internal_ev_mwhsmiaaw
-#define __ev_mwhusiaaw __internal_ev_mwhusiaaw
-#define __ev_mwhumiaaw __internal_ev_mwhumiaaw
-#define __ev_mwhssfanw __internal_ev_mwhssfanw
-#define __ev_mwhssianw __internal_ev_mwhssianw
-#define __ev_mwhsmfanw __internal_ev_mwhsmfanw
-#define __ev_mwhsmianw __internal_ev_mwhsmianw
-#define __ev_mwhusianw __internal_ev_mwhusianw
-#define __ev_mwhumianw __internal_ev_mwhumianw
-
-static inline __ev64_opaque__
-__internal_ev_mwhssfaaw (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhssf (a, b);
- return __ev_addssiaaw (t);
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhssiaaw (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhsmi (a, b);
- return __ev_addssiaaw (t);
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhsmfaaw (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhsmf (a, b);
- return __ev_addsmiaaw (t);
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhsmiaaw (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhsmi (a, b);
- return __ev_addsmiaaw (t);
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhusiaaw (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhumi (a, b);
- return __ev_addusiaaw (t);
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhumiaaw (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhumi (a, b);
- return __ev_addumiaaw (t);
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhssfanw (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhssf (a, b);
- return __ev_subfssiaaw (t);
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhssianw (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhsmi (a, b);
- return __ev_subfssiaaw (t);
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhsmfanw (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhsmf (a, b);
- return __ev_subfsmiaaw (t);
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhsmianw (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhsmi (a, b);
- return __ev_subfsmiaaw (t);
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhusianw (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhumi (a, b);
- return __ev_subfusiaaw (t);
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhumianw (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhumi (a, b);
- return __ev_subfumiaaw (t);
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhgssfaa (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhssf (a, b);
- return __ev_mwsmiaa (t, ((__ev64_s32__){1, 1}));
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhgsmfaa (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhsmf (a, b);
- return __ev_mwsmiaa (t, ((__ev64_s32__){1, 1}));
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhgsmiaa (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhsmi (a, b);
- return __ev_mwsmiaa (t, ((__ev64_s32__){1, 1}));
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhgumiaa (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhumi (a, b);
- return __ev_mwumiaa (t, ((__ev64_s32__){1, 1}));
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhgssfan (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhssf (a, b);
- return __ev_mwsmian (t, ((__ev64_s32__){1, 1}));
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhgsmfan (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhsmf (a, b);
- return __ev_mwsmian (t, ((__ev64_s32__){1, 1}));
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhgsmian (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhsmi (a, b);
- return __ev_mwsmian (t, ((__ev64_s32__){1, 1}));
-}
-
-static inline __ev64_opaque__
-__internal_ev_mwhgumian (__ev64_opaque__ a, __ev64_opaque__ b)
-{
- __ev64_opaque__ t;
-
- t = __ev_mwhumi (a, b);
- return __ev_mwumian (t, ((__ev64_s32__){1, 1}));
-}
-
-/* END OF NOT SUPPORTED */
-
-/* __ev_create* functions. */
-
-#define __ev_create_ufix32_u32 __ev_create_u32
-#define __ev_create_sfix32_s32 __ev_create_s32
-
-static inline __ev64_opaque__
-__ev_create_s16 (int16_t a, int16_t b, int16_t c, int16_t d)
-{
- union
- {
- __ev64_opaque__ v;
- int16_t i[4];
- } u;
-
- u.i[0] = a;
- u.i[1] = b;
- u.i[2] = c;
- u.i[3] = d;
-
- return u.v;
-}
-
-static inline __ev64_opaque__
-__ev_create_u16 (uint16_t a, uint16_t b, uint16_t c, uint16_t d)
-
-{
- union
- {
- __ev64_opaque__ v;
- uint16_t i[4];
- } u;
-
- u.i[0] = a;
- u.i[1] = b;
- u.i[2] = c;
- u.i[3] = d;
-
- return u.v;
-}
-
-static inline __ev64_opaque__
-__ev_create_s32 (int32_t a, int32_t b)
-{
- union
- {
- __ev64_opaque__ v;
- int32_t i[2];
- } u;
-
- u.i[0] = a;
- u.i[1] = b;
-
- return u.v;
-}
-
-static inline __ev64_opaque__
-__ev_create_u32 (uint32_t a, uint32_t b)
-{
- union
- {
- __ev64_opaque__ v;
- uint32_t i[2];
- } u;
-
- u.i[0] = a;
- u.i[1] = b;
-
- return u.v;
-}
-
-static inline __ev64_opaque__
-__ev_create_fs (float a, float b)
-{
- union
- {
- __ev64_opaque__ v;
- float f[2];
- } u;
-
- u.f[0] = a;
- u.f[1] = b;
-
- return u.v;
-}
-
-static inline __ev64_opaque__
-__ev_create_sfix32_fs (float a, float b)
-{
- __ev64_opaque__ ev;
-
- ev = (__ev64_opaque__) __ev_create_fs (a, b);
- return (__ev64_opaque__) __builtin_spe_evfsctsf ((__v2sf) ev);
-}
-
-static inline __ev64_opaque__
-__ev_create_ufix32_fs (float a, float b)
-{
- __ev64_opaque__ ev;
-
- ev = (__ev64_opaque__) __ev_create_fs (a, b);
- return (__ev64_opaque__) __builtin_spe_evfsctuf ((__v2sf) ev);
-}
-
-static inline __ev64_opaque__
-__ev_create_s64 (int64_t a)
-{
- union
- {
- __ev64_opaque__ v;
- int64_t i;
- } u;
-
- u.i = a;
- return u.v;
-}
-
-static inline __ev64_opaque__
-__ev_create_u64 (uint64_t a)
-{
- union
- {
- __ev64_opaque__ v;
- uint64_t i;
- } u;
-
- u.i = a;
- return u.v;
-}
-
-static inline uint64_t
-__ev_convert_u64 (__ev64_opaque__ a)
-{
- return (uint64_t) a;
-}
-
-static inline int64_t
-__ev_convert_s64 (__ev64_opaque__ a)
-{
- return (int64_t) a;
-}
-
-/* __ev_get_* functions. */
-
-#define __ev_get_upper_u32(a) __ev_get_u32_internal ((a), 0)
-#define __ev_get_lower_u32(a) __ev_get_u32_internal ((a), 1)
-#define __ev_get_upper_s32(a) __ev_get_s32_internal ((a), 0)
-#define __ev_get_lower_s32(a) __ev_get_s32_internal ((a), 1)
-#define __ev_get_upper_fs(a) __ev_get_fs_internal ((a), 0)
-#define __ev_get_lower_fs(a) __ev_get_fs_internal ((a), 1)
-#define __ev_get_upper_ufix32_u32 __ev_get_upper_u32
-#define __ev_get_lower_ufix32_u32 __ev_get_lower_u32
-#define __ev_get_upper_sfix32_s32 __ev_get_upper_s32
-#define __ev_get_lower_sfix32_s32 __ev_get_lower_s32
-#define __ev_get_upper_sfix32_fs(a) __ev_get_sfix32_fs ((a), 0)
-#define __ev_get_lower_sfix32_fs(a) __ev_get_sfix32_fs ((a), 1)
-#define __ev_get_upper_ufix32_fs(a) __ev_get_ufix32_fs ((a), 0)
-#define __ev_get_lower_ufix32_fs(a) __ev_get_ufix32_fs ((a), 1)
-
-#define __ev_get_u32 __ev_get_u32_internal
-#define __ev_get_s32 __ev_get_s32_internal
-#define __ev_get_fs __ev_get_fs_internal
-#define __ev_get_u16 __ev_get_u16_internal
-#define __ev_get_s16 __ev_get_s16_internal
-
-#define __ev_get_ufix32_u32 __ev_get_u32
-#define __ev_get_sfix32_s32 __ev_get_s32
-#define __ev_get_ufix32_fs __ev_get_ufix32_fs_internal
-#define __ev_get_sfix32_fs __ev_get_sfix32_fs_internal
-
-static inline uint32_t
-__ev_get_u32_internal (__ev64_opaque__ a, uint32_t pos)
-{
- union
- {
- __ev64_opaque__ v;
- uint32_t i[2];
- } u;
-
- u.v = a;
- return u.i[pos];
-}
-
-static inline int32_t
-__ev_get_s32_internal (__ev64_opaque__ a, uint32_t pos)
-{
- union
- {
- __ev64_opaque__ v;
- int32_t i[2];
- } u;
-
- u.v = a;
- return u.i[pos];
-}
-
-static inline float
-__ev_get_fs_internal (__ev64_opaque__ a, uint32_t pos)
-{
- union
- {
- __ev64_opaque__ v;
- float f[2];
- } u;
-
- u.v = a;
- return u.f[pos];
-}
-
-static inline float
-__ev_get_sfix32_fs_internal (__ev64_opaque__ a, uint32_t pos)
-{
- __ev64_fs__ v;
-
- v = __builtin_spe_evfscfsf ((__v2sf) a);
- return __ev_get_fs_internal ((__ev64_opaque__) v, pos);
-}
-
-static inline float
-__ev_get_ufix32_fs_internal (__ev64_opaque__ a, uint32_t pos)
-{
- __ev64_fs__ v;
-
- v = __builtin_spe_evfscfuf ((__v2sf) a);
- return __ev_get_fs_internal ((__ev64_opaque__) v, pos);
-}
-
-static inline uint16_t
-__ev_get_u16_internal (__ev64_opaque__ a, uint32_t pos)
-{
- union
- {
- __ev64_opaque__ v;
- uint16_t i[4];
- } u;
-
- u.v = a;
- return u.i[pos];
-}
-
-static inline int16_t
-__ev_get_s16_internal (__ev64_opaque__ a, uint32_t pos)
-{
- union
- {
- __ev64_opaque__ v;
- int16_t i[4];
- } u;
-
- u.v = a;
- return u.i[pos];
-}
-
-/* __ev_set_* functions. */
-
-#define __ev_set_u32 __ev_set_u32_internal
-#define __ev_set_s32 __ev_set_s32_internal
-#define __ev_set_fs __ev_set_fs_internal
-#define __ev_set_u16 __ev_set_u16_internal
-#define __ev_set_s16 __ev_set_s16_internal
-
-#define __ev_set_ufix32_u32 __ev_set_u32
-#define __ev_set_sfix32_s32 __ev_set_s32
-
-#define __ev_set_sfix32_fs __ev_set_sfix32_fs_internal
-#define __ev_set_ufix32_fs __ev_set_ufix32_fs_internal
-
-#define __ev_set_upper_u32(a, b) __ev_set_u32 (a, b, 0)
-#define __ev_set_lower_u32(a, b) __ev_set_u32 (a, b, 1)
-#define __ev_set_upper_s32(a, b) __ev_set_s32 (a, b, 0)
-#define __ev_set_lower_s32(a, b) __ev_set_s32 (a, b, 1)
-#define __ev_set_upper_fs(a, b) __ev_set_fs (a, b, 0)
-#define __ev_set_lower_fs(a, b) __ev_set_fs (a, b, 1)
-#define __ev_set_upper_ufix32_u32 __ev_set_upper_u32
-#define __ev_set_lower_ufix32_u32 __ev_set_lower_u32
-#define __ev_set_upper_sfix32_s32 __ev_set_upper_s32
-#define __ev_set_lower_sfix32_s32 __ev_set_lower_s32
-#define __ev_set_upper_sfix32_fs(a, b) __ev_set_sfix32_fs (a, b, 0)
-#define __ev_set_lower_sfix32_fs(a, b) __ev_set_sfix32_fs (a, b, 1)
-#define __ev_set_upper_ufix32_fs(a, b) __ev_set_ufix32_fs (a, b, 0)
-#define __ev_set_lower_ufix32_fs(a, b) __ev_set_ufix32_fs (a, b, 1)
-
-#define __ev_set_acc_vec64 __builtin_spe_evmra
-
-static inline __ev64_opaque__
-__ev_set_acc_u64 (uint64_t a)
-{
- __ev64_opaque__ ev32;
- ev32 = __ev_create_u64 (a);
- __ev_mra (ev32);
- return ev32;
-}
-
-static inline __ev64_opaque__
-__ev_set_acc_s64 (int64_t a)
-{
- __ev64_opaque__ ev32;
- ev32 = __ev_create_s64 (a);
- __ev_mra (ev32);
- return ev32;
-}
-
-static inline __ev64_opaque__
-__ev_set_u32_internal (__ev64_opaque__ a, uint32_t b, uint32_t pos)
-{
- union
- {
- __ev64_opaque__ v;
- uint32_t i[2];
- } u;
-
- u.v = a;
- u.i[pos] = b;
- return u.v;
-}
-
-static inline __ev64_opaque__
-__ev_set_s32_internal (__ev64_opaque__ a, int32_t b, uint32_t pos)
-{
- union
- {
- __ev64_opaque__ v;
- int32_t i[2];
- } u;
-
- u.v = a;
- u.i[pos] = b;
- return u.v;
-}
-
-static inline __ev64_opaque__
-__ev_set_fs_internal (__ev64_opaque__ a, float b, uint32_t pos)
-{
- union
- {
- __ev64_opaque__ v;
- float f[2];
- } u;
-
- u.v = a;
- u.f[pos] = b;
- return u.v;
-}
-
-static inline __ev64_opaque__
-__ev_set_sfix32_fs_internal (__ev64_opaque__ a, float b, uint32_t pos)
-{
- __ev64_opaque__ v;
- float other;
-
- /* Get other half. */
- other = __ev_get_fs_internal (a, pos ^ 1);
-
- /* Make an sfix32 with 'b'. */
- v = __ev_create_sfix32_fs (b, b);
-
- /* Set other half to what it used to be. */
- return __ev_set_fs_internal (v, other, pos ^ 1);
-}
-
-static inline __ev64_opaque__
-__ev_set_ufix32_fs_internal (__ev64_opaque__ a, float b, uint32_t pos)
-{
- __ev64_opaque__ v;
- float other;
-
- /* Get other half. */
- other = __ev_get_fs_internal (a, pos ^ 1);
-
- /* Make an ufix32 with 'b'. */
- v = __ev_create_ufix32_fs (b, b);
-
- /* Set other half to what it used to be. */
- return __ev_set_fs_internal (v, other, pos ^ 1);
-}
-
-static inline __ev64_opaque__
-__ev_set_u16_internal (__ev64_opaque__ a, uint16_t b, uint32_t pos)
-{
- union
- {
- __ev64_opaque__ v;
- uint16_t i[4];
- } u;
-
- u.v = a;
- u.i[pos] = b;
- return u.v;
-}
-
-static inline __ev64_opaque__
-__ev_set_s16_internal (__ev64_opaque__ a, int16_t b, uint32_t pos)
-{
- union
- {
- __ev64_opaque__ v;
- int16_t i[4];
- } u;
-
- u.v = a;
- u.i[pos] = b;
- return u.v;
-}
-
-/* Predicates. */
-
-#define __pred_all 0
-#define __pred_any 1
-#define __pred_upper 2
-#define __pred_lower 3
-
-#define __ev_any_gts(a, b) __builtin_spe_evcmpgts (__pred_any, (a), (b))
-#define __ev_all_gts(a, b) __builtin_spe_evcmpgts (__pred_all, (a), (b))
-#define __ev_upper_gts(a, b) __builtin_spe_evcmpgts (__pred_upper, (a), (b))
-#define __ev_lower_gts(a, b) __builtin_spe_evcmpgts (__pred_lower, (a), (b))
-#define __ev_select_gts __builtin_spe_evsel_gts
-
-#define __ev_any_gtu(a, b) __builtin_spe_evcmpgtu (__pred_any, (a), (b))
-#define __ev_all_gtu(a, b) __builtin_spe_evcmpgtu (__pred_all, (a), (b))
-#define __ev_upper_gtu(a, b) __builtin_spe_evcmpgtu (__pred_upper, (a), (b))
-#define __ev_lower_gtu(a, b) __builtin_spe_evcmpgtu (__pred_lower, (a), (b))
-#define __ev_select_gtu __builtin_spe_evsel_gtu
-
-#define __ev_any_lts(a, b) __builtin_spe_evcmplts (__pred_any, (a), (b))
-#define __ev_all_lts(a, b) __builtin_spe_evcmplts (__pred_all, (a), (b))
-#define __ev_upper_lts(a, b) __builtin_spe_evcmplts (__pred_upper, (a), (b))
-#define __ev_lower_lts(a, b) __builtin_spe_evcmplts (__pred_lower, (a), (b))
-#define __ev_select_lts(a, b, c, d) ((__v2si) __builtin_spe_evsel_lts ((a), (b), (c), (d)))
-
-#define __ev_any_ltu(a, b) __builtin_spe_evcmpltu (__pred_any, (a), (b))
-#define __ev_all_ltu(a, b) __builtin_spe_evcmpltu (__pred_all, (a), (b))
-#define __ev_upper_ltu(a, b) __builtin_spe_evcmpltu (__pred_upper, (a), (b))
-#define __ev_lower_ltu(a, b) __builtin_spe_evcmpltu (__pred_lower, (a), (b))
-#define __ev_select_ltu __builtin_spe_evsel_ltu
-#define __ev_any_eq(a, b) __builtin_spe_evcmpeq (__pred_any, (a), (b))
-#define __ev_all_eq(a, b) __builtin_spe_evcmpeq (__pred_all, (a), (b))
-#define __ev_upper_eq(a, b) __builtin_spe_evcmpeq (__pred_upper, (a), (b))
-#define __ev_lower_eq(a, b) __builtin_spe_evcmpeq (__pred_lower, (a), (b))
-#define __ev_select_eq __builtin_spe_evsel_eq
-
-#define __ev_any_fs_gt(a, b) __builtin_spe_evfscmpgt (__pred_any, (a), (b))
-#define __ev_all_fs_gt(a, b) __builtin_spe_evfscmpgt (__pred_all, (a), (b))
-#define __ev_upper_fs_gt(a, b) __builtin_spe_evfscmpgt (__pred_upper, (a), (b))
-#define __ev_lower_fs_gt(a, b) __builtin_spe_evfscmpgt (__pred_lower, (a), (b))
-#define __ev_select_fs_gt __builtin_spe_evsel_fsgt
-
-#define __ev_any_fs_lt(a, b) __builtin_spe_evfscmplt (__pred_any, (a), (b))
-#define __ev_all_fs_lt(a, b) __builtin_spe_evfscmplt (__pred_all, (a), (b))
-#define __ev_upper_fs_lt(a, b) __builtin_spe_evfscmplt (__pred_upper, (a), (b))
-#define __ev_lower_fs_lt(a, b) __builtin_spe_evfscmplt (__pred_lower, (a), (b))
-#define __ev_select_fs_lt __builtin_spe_evsel_fslt
-
-#define __ev_any_fs_eq(a, b) __builtin_spe_evfscmpeq (__pred_any, (a), (b))
-#define __ev_all_fs_eq(a, b) __builtin_spe_evfscmpeq (__pred_all, (a), (b))
-#define __ev_upper_fs_eq(a, b) __builtin_spe_evfscmpeq (__pred_upper, (a), (b))
-#define __ev_lower_fs_eq(a, b) __builtin_spe_evfscmpeq (__pred_lower, (a), (b))
-#define __ev_select_fs_eq __builtin_spe_evsel_fseq
-
-#define __ev_any_fs_tst_gt(a, b) __builtin_spe_evfststgt (__pred_any, (a), (b))
-#define __ev_all_fs_tst_gt(a, b) __builtin_spe_evfststgt (__pred_all, (a), (b))
-#define __ev_upper_fs_tst_gt(a, b) __builtin_spe_evfststgt (__pred_upper, (a), (b))
-#define __ev_lower_fs_tst_gt(a, b) __builtin_spe_evfststgt (__pred_lower, (a), (b))
-#define __ev_select_fs_tst_gt __builtin_spe_evsel_fststgt
-
-#define __ev_any_fs_tst_lt(a, b) __builtin_spe_evfststlt (__pred_any, (a), (b))
-#define __ev_all_fs_tst_lt(a, b) __builtin_spe_evfststlt (__pred_all, (a), (b))
-#define __ev_upper_fs_tst_lt(a, b) __builtin_spe_evfststlt (__pred_upper, (a), (b))
-#define __ev_lower_fs_tst_lt(a, b) __builtin_spe_evfststlt (__pred_lower, (a), (b))
-#define __ev_select_fs_tst_lt __builtin_spe_evsel_fststlt
-
-#define __ev_any_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_any, (a), (b))
-#define __ev_all_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_all, (a), (b))
-#define __ev_upper_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_upper, (a), (b))
-#define __ev_lower_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_lower, (a), (b))
-#define __ev_select_fs_tst_eq __builtin_spe_evsel_fststeq
-
-/* SPEFSCR accessor functions. */
-
-#define __SPEFSCR_SOVH 0x80000000
-#define __SPEFSCR_OVH 0x40000000
-#define __SPEFSCR_FGH 0x20000000
-#define __SPEFSCR_FXH 0x10000000
-#define __SPEFSCR_FINVH 0x08000000
-#define __SPEFSCR_FDBZH 0x04000000
-#define __SPEFSCR_FUNFH 0x02000000
-#define __SPEFSCR_FOVFH 0x01000000
-/* 2 unused bits. */
-#define __SPEFSCR_FINXS 0x00200000
-#define __SPEFSCR_FINVS 0x00100000
-#define __SPEFSCR_FDBZS 0x00080000
-#define __SPEFSCR_FUNFS 0x00040000
-#define __SPEFSCR_FOVFS 0x00020000
-#define __SPEFSCR_MODE 0x00010000
-#define __SPEFSCR_SOV 0x00008000
-#define __SPEFSCR_OV 0x00004000
-#define __SPEFSCR_FG 0x00002000
-#define __SPEFSCR_FX 0x00001000
-#define __SPEFSCR_FINV 0x00000800
-#define __SPEFSCR_FDBZ 0x00000400
-#define __SPEFSCR_FUNF 0x00000200
-#define __SPEFSCR_FOVF 0x00000100
-/* 1 unused bit. */
-#define __SPEFSCR_FINXE 0x00000040
-#define __SPEFSCR_FINVE 0x00000020
-#define __SPEFSCR_FDBZE 0x00000010
-#define __SPEFSCR_FUNFE 0x00000008
-#define __SPEFSCR_FOVFE 0x00000004
-#define __SPEFSCR_FRMC 0x00000003
-
-#define __ev_get_spefscr_sovh() (__builtin_spe_mfspefscr () & __SPEFSCR_SOVH)
-#define __ev_get_spefscr_ovh() (__builtin_spe_mfspefscr () & __SPEFSCR_OVH)
-#define __ev_get_spefscr_fgh() (__builtin_spe_mfspefscr () & __SPEFSCR_FGH)
-#define __ev_get_spefscr_fxh() (__builtin_spe_mfspefscr () & __SPEFSCR_FXH)
-#define __ev_get_spefscr_finvh() (__builtin_spe_mfspefscr () & __SPEFSCR_FINVH)
-#define __ev_get_spefscr_fdbzh() (__builtin_spe_mfspefscr () & __SPEFSCR_FDBZH)
-#define __ev_get_spefscr_funfh() (__builtin_spe_mfspefscr () & __SPEFSCR_FUNFH)
-#define __ev_get_spefscr_fovfh() (__builtin_spe_mfspefscr () & __SPEFSCR_FOVFH)
-#define __ev_get_spefscr_finxs() (__builtin_spe_mfspefscr () & __SPEFSCR_FINXS)
-#define __ev_get_spefscr_finvs() (__builtin_spe_mfspefscr () & __SPEFSCR_FINVS)
-#define __ev_get_spefscr_fdbzs() (__builtin_spe_mfspefscr () & __SPEFSCR_FDBZS)
-#define __ev_get_spefscr_funfs() (__builtin_spe_mfspefscr () & __SPEFSCR_FUNFS)
-#define __ev_get_spefscr_fovfs() (__builtin_spe_mfspefscr () & __SPEFSCR_FOVFS)
-#define __ev_get_spefscr_mode() (__builtin_spe_mfspefscr () & __SPEFSCR_MODE)
-#define __ev_get_spefscr_sov() (__builtin_spe_mfspefscr () & __SPEFSCR_SOV)
-#define __ev_get_spefscr_ov() (__builtin_spe_mfspefscr () & __SPEFSCR_OV)
-#define __ev_get_spefscr_fg() (__builtin_spe_mfspefscr () & __SPEFSCR_FG)
-#define __ev_get_spefscr_fx() (__builtin_spe_mfspefscr () & __SPEFSCR_FX)
-#define __ev_get_spefscr_finv() (__builtin_spe_mfspefscr () & __SPEFSCR_FINV)
-#define __ev_get_spefscr_fdbz() (__builtin_spe_mfspefscr () & __SPEFSCR_FDBZ)
-#define __ev_get_spefscr_funf() (__builtin_spe_mfspefscr () & __SPEFSCR_FUNF)
-#define __ev_get_spefscr_fovf() (__builtin_spe_mfspefscr () & __SPEFSCR_FOVF)
-#define __ev_get_spefscr_finxe() (__builtin_spe_mfspefscr () & __SPEFSCR_FINXE)
-#define __ev_get_spefscr_finve() (__builtin_spe_mfspefscr () & __SPEFSCR_FINVE)
-#define __ev_get_spefscr_fdbze() (__builtin_spe_mfspefscr () & __SPEFSCR_FDBZE)
-#define __ev_get_spefscr_funfe() (__builtin_spe_mfspefscr () & __SPEFSCR_FUNFE)
-#define __ev_get_spefscr_fovfe() (__builtin_spe_mfspefscr () & __SPEFSCR_FOVFE)
-#define __ev_get_spefscr_frmc() (__builtin_spe_mfspefscr () & __SPEFSCR_FRMC)
-
-static inline void
-__ev_clr_spefscr_field (int mask)
-{
- int i;
-
- i = __builtin_spe_mfspefscr ();
- i &= ~mask;
- __builtin_spe_mtspefscr (i);
-}
-
-#define __ev_clr_spefscr_sovh() __ev_clr_spefscr_field (__SPEFSCR_SOVH)
-#define __ev_clr_spefscr_sov() __ev_clr_spefscr_field (__SPEFSCR_SOV)
-#define __ev_clr_spefscr_finxs() __ev_clr_spefscr_field (__SPEFSCR_FINXS)
-#define __ev_clr_spefscr_finvs() __ev_clr_spefscr_field (__SPEFSCR_FINVS)
-#define __ev_clr_spefscr_fdbzs() __ev_clr_spefscr_field (__SPEFSCR_FDBZS)
-#define __ev_clr_spefscr_funfs() __ev_clr_spefscr_field (__SPEFSCR_FUNFS)
-#define __ev_clr_spefscr_fovfs() __ev_clr_spefscr_field (__SPEFSCR_FOVFS)
-
-/* Set rounding mode:
- rnd = 0 (nearest)
- rnd = 1 (zero)
- rnd = 2 (+inf)
- rnd = 3 (-inf). */
-
-static inline void
-__ev_set_spefscr_frmc (int rnd)
-{
- int i;
-
- i = __builtin_spe_mfspefscr ();
- i &= ~__SPEFSCR_FRMC;
- i |= rnd;
- __builtin_spe_mtspefscr (i);
-}
-
-/* The SPE PIM says these are declared in <spe.h>, although they are
- not provided by GCC: they must be taken from a separate
- library. */
-extern short int atosfix16 (const char *);
-extern int atosfix32 (const char *);
-extern long long atosfix64 (const char *);
-
-extern unsigned short atoufix16 (const char *);
-extern unsigned int atoufix32 (const char *);
-extern unsigned long long atoufix64 (const char *);
-
-extern short int strtosfix16 (const char *, char **);
-extern int strtosfix32 (const char *, char **);
-extern long long strtosfix64 (const char *, char **);
-
-extern unsigned short int strtoufix16 (const char *, char **);
-extern unsigned int strtoufix32 (const char *, char **);
-extern unsigned long long strtoufix64 (const char *, char **);
-
-#endif /* _SPE_H */
diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md
deleted file mode 100644
index 372e190..0000000
--- a/gcc/config/rs6000/spe.md
+++ /dev/null
@@ -1,28 +0,0 @@
-;; e500 SPE description
-;; Copyright (C) 2002-2017 Free Software Foundation, Inc.
-;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
-
-;; This file is part of GCC.
-
-;; GCC is free software; you can redistribute it and/or modify it
-;; under the terms of the GNU General Public License as published
-;; by the Free Software Foundation; either version 3, or (at your
-;; option) any later version.
-
-;; GCC is distributed in the hope that it will be useful, but WITHOUT
-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
-;; License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3. If not see
-;; <http://www.gnu.org/licenses/>.
-
-;; Modes using a 64-bit register.
-(define_mode_iterator SPE64 [DF V4HI V2SF V1DI V2SI])
-
-;; Likewise, but allow TFmode (two registers) as well.
-(define_mode_iterator SPE64TF [DF V4HI V2SF V1DI V2SI TF])
-
-;; DImode and TImode.
-(define_mode_iterator DITI [DI TI])
diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000
index 7270723..a1dca3c 100644
--- a/gcc/config/rs6000/t-rs6000
+++ b/gcc/config/rs6000/t-rs6000
@@ -64,6 +64,5 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \
$(srcdir)/config/rs6000/altivec.md \
$(srcdir)/config/rs6000/crypto.md \
$(srcdir)/config/rs6000/htm.md \
- $(srcdir)/config/rs6000/spe.md \
$(srcdir)/config/rs6000/dfp.md \
$(srcdir)/config/rs6000/paired.md
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 09/14] rs6000: Remove reg_or_none500mem_operand
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
` (9 preceding siblings ...)
2017-06-06 15:58 ` [PATCH 12/14] rs6000: Remove SPE high registers Segher Boessenkool
@ 2017-06-06 15:58 ` Segher Boessenkool
2017-06-06 17:06 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 13/14] rs6000: Remove spe_acc and spefscr Segher Boessenkool
` (2 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:58 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/predicates.md (reg_or_mem_operand): Reformat.
(reg_or_none500mem_operand): Delete.
* config/rs6000/rs6000.md (extendsfdf2): Use reg_or_mem_operand
instead of reg_or_none500mem_operand.
---
gcc/config/rs6000/predicates.md | 18 +++++-------------
gcc/config/rs6000/rs6000.md | 2 +-
2 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 4edfdbb..1bf9194 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -970,19 +970,11 @@ (define_predicate "scc_eq_operand"
;; Return 1 if the operand is a general non-special register or memory operand.
(define_predicate "reg_or_mem_operand"
- (ior (match_operand 0 "memory_operand")
- (ior (and (match_code "mem")
- (match_test "macho_lo_sum_memory_operand (op, mode)"))
- (ior (match_operand 0 "volatile_mem_operand")
- (match_operand 0 "gpc_reg_operand")))))
-
-;; Return 1 if the operand is either an easy FP constant or memory or reg.
-(define_predicate "reg_or_none500mem_operand"
- (if_then_else (match_code "mem")
- (ior (match_operand 0 "memory_operand")
- (match_test "macho_lo_sum_memory_operand (op, mode)")
- (match_operand 0 "volatile_mem_operand"))
- (match_operand 0 "gpc_reg_operand")))
+ (ior (match_operand 0 "memory_operand")
+ (and (match_code "mem")
+ (match_test "macho_lo_sum_memory_operand (op, mode)"))
+ (match_operand 0 "volatile_mem_operand")
+ (match_operand 0 "gpc_reg_operand")))
;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
(define_predicate "zero_reg_mem_operand"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3fea231..edb5208 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4638,7 +4638,7 @@ (define_insn "*cmp<mode>_fpr"
;; Floating point conversions
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand")
- (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand")))]
+ (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
if (HONOR_SNANS (SFmode))
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 07/14] rs6000: Remove TARGET_SPE and TARGET_SPE_ABI and friends
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
` (5 preceding siblings ...)
2017-06-06 15:58 ` [PATCH 06/14] rs6000: Remove UNSPEC_MV_CR_GT Segher Boessenkool
@ 2017-06-06 15:58 ` Segher Boessenkool
2017-06-06 17:04 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 08/14] rs6000: Remove -mspe options Segher Boessenkool
` (6 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:58 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000-common.c (rs6000_handle_option): Remove
SPE ABI handling.
* config/rs6000/paired.md (paired_negv2sf2): Rename to negv2sf2.
(paired_absv2sf2, paired_addv2sf3, paired_subv2sf3, paired_mulv2sf3,
paired_divv2sf3): Similar.
* config/rs6000/predicates.md: Replace TARGET_SPE, TARGET_SPE_ABI,
SPE_VECTOR_MODE and SPE_HIGH_REGNO_P by 0; simplify.
* config/rs6000/rs6000-builtin.def: Delete RS6000_BUILTIN_E and
RS6000_BUILTIN_S.
Delete BU_SPE_1, BU_SPE_2, BU_SPE_3, BU_SPE_E, BU_SPE_P, and BU_SPE_X.
Rename the paired_* instruction patterns.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Do not
define __SPE__.
* config/rs6000/rs6000-protos.h (invalid_e500_subreg): Delete.
* config/rs6000/rs6000.c: Delete RS6000_BUILTIN_E and RS6000_BUILTIN_S.
(struct rs6000_stack): Delete fields spe_gp_save_offset, spe_gp_size,
spe_padding_size, and spe_64bit_regs_used. Replace TARGET_SPE and
TARGET_SPE_ABI with 0, simplify. Replace SPE_VECTOR_MODE with
PAIRED_VECTOR_MODE.
(struct machine_function): Delete field spe_insn_chain_scanned_p.
(spe_func_has_64bit_regs_p): Delete.
(spe_expand_predicate_builtin): Delete.
(spe_expand_evsel_builtin): Delete.
(TARGET_DWARF_REGISTER_SPAN): Do not define.
(TARGET_MEMBER_TYPE_FORCES_BLK): Do not define.
(invalid_e500_subreg): Delete.
(rs6000_legitimize_address): Always force_reg op2 as well, for
paired single memory accesses.
(rs6000_member_type_forces_blk): Delete.
(rs6000_spe_function_arg): Delete.
(rs6000_expand_unop_builtin): Delete SPE handling.
(rs6000_expand_binop_builtin): Ditto.
(spe_expand_stv_builtin): Delete.
(bdesc_2arg_spe): Delete.
(spe_expand_builtin): Delete.
(spe_expand_predicate_builtin): Delete.
(spe_expand_evsel_builtin): Delete.
(rs6000_invalid_builtin): Remove RS6000_BTM_SPE handling.
(spe_init_builtins): Delete.
(spe_func_has_64bit_regs_p): Delete.
(savres_routine_name): Delete "info" parameter. Adjust callers.
(rs6000_emit_stack_reset): Ditto.
(rs6000_dwarf_register_span): Delete.
* config/rs6000/rs6000.h (TARGET_SPE_ABI, TARGET_SPE,
UNITS_PER_SPE_WORD, SPE_HIGH_REGNO_P, SPE_SIMD_REGNO_P,
SPE_VECTOR_MODE, RS6000_BTM_SPE, RS6000_BUILTIN_E, RS6000_BUILTIN_S):
Delete.
* config/rs6000/rs6000.md (FIRST_SPE_HIGH_REGNO, LAST_SPE_HIGH_REGNO):
Delete.
* config/rs6000/rs6000.opt (-mabi=spe, -mabi=no-spe): Delete.
* config/rs6000/spe.md: Delete every pattern that uses TARGET_SPE.
* config/rs6000/vector.md (absv2sf2, negv2sf2, addv2sf3, subv2sf3,
mulv2sf3, divv2sf3): Delete expanders.
---
gcc/common/config/rs6000/rs6000-common.c | 9 -
gcc/config/rs6000/paired.md | 12 +-
gcc/config/rs6000/predicates.md | 49 +-
gcc/config/rs6000/rs6000-builtin.def | 313 +---
gcc/config/rs6000/rs6000-c.c | 4 -
gcc/config/rs6000/rs6000-protos.h | 1 -
gcc/config/rs6000/rs6000.c | 1417 +--------------
gcc/config/rs6000/rs6000.h | 44 +-
gcc/config/rs6000/rs6000.md | 2 -
gcc/config/rs6000/rs6000.opt | 8 -
gcc/config/rs6000/spe.md | 2767 ------------------------------
gcc/config/rs6000/vector.md | 95 -
12 files changed, 67 insertions(+), 4654 deletions(-)
diff --git a/gcc/common/config/rs6000/rs6000-common.c b/gcc/common/config/rs6000/rs6000-common.c
index 3c0106a..0753754 100644
--- a/gcc/common/config/rs6000/rs6000-common.c
+++ b/gcc/common/config/rs6000/rs6000-common.c
@@ -207,15 +207,6 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
break;
#endif
- case OPT_mabi_altivec:
- /* Enabling the AltiVec ABI turns off the SPE ABI. */
- opts->x_rs6000_spe_abi = 0;
- break;
-
- case OPT_mabi_spe:
- opts->x_rs6000_altivec_abi = 0;
- break;
-
case OPT_mlong_double_:
if (value != 64 && value != 128)
{
diff --git a/gcc/config/rs6000/paired.md b/gcc/config/rs6000/paired.md
index 09123ee..c9f9586 100644
--- a/gcc/config/rs6000/paired.md
+++ b/gcc/config/rs6000/paired.md
@@ -26,7 +26,7 @@ (define_c_enum "unspec"
UNSPEC_EXTODD_V2SF
])
-(define_insn "paired_negv2sf2"
+(define_insn "negv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
@@ -40,7 +40,7 @@ (define_insn "sqrtv2sf2"
"ps_rsqrte %0,%1"
[(set_attr "type" "fp")])
-(define_insn "paired_absv2sf2"
+(define_insn "absv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
@@ -54,7 +54,7 @@ (define_insn "nabsv2sf2"
"ps_nabs %0,%1"
[(set_attr "type" "fp")])
-(define_insn "paired_addv2sf3"
+(define_insn "addv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
@@ -62,7 +62,7 @@ (define_insn "paired_addv2sf3"
"ps_add %0,%1,%2"
[(set_attr "type" "fp")])
-(define_insn "paired_subv2sf3"
+(define_insn "subv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
@@ -70,7 +70,7 @@ (define_insn "paired_subv2sf3"
"ps_sub %0,%1,%2"
[(set_attr "type" "fp")])
-(define_insn "paired_mulv2sf3"
+(define_insn "mulv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
@@ -85,7 +85,7 @@ (define_insn "resv2sf2"
"ps_res %0,%1"
[(set_attr "type" "fp")])
-(define_insn "paired_divv2sf3"
+(define_insn "divv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 11aecbd..4edfdbb 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -299,9 +299,6 @@ (define_predicate "const_0_to_15_operand"
(define_predicate "gpc_reg_operand"
(match_operand 0 "register_operand")
{
- if (TARGET_SPE && invalid_e500_subreg (op, mode))
- return 0;
-
if (GET_CODE (op) == SUBREG)
{
if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
@@ -331,9 +328,6 @@ (define_predicate "gpc_reg_operand"
(define_predicate "int_reg_operand"
(match_operand 0 "register_operand")
{
- if (TARGET_SPE && invalid_e500_subreg (op, mode))
- return 0;
-
if (GET_CODE (op) == SUBREG)
{
if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
@@ -357,9 +351,6 @@ (define_predicate "int_reg_operand"
(define_predicate "int_reg_operand_not_pseudo"
(match_operand 0 "register_operand")
{
- if (TARGET_SPE && invalid_e500_subreg (op, mode))
- return 0;
-
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
@@ -711,32 +702,6 @@ (define_predicate "easy_vector_constant"
return easy_altivec_constant (op, mode);
}
- if (SPE_VECTOR_MODE (mode))
- {
- int cst, cst2;
- if (zero_constant (op, mode))
- return true;
- if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
- return false;
-
- /* Limit SPE vectors to 15 bits signed. These we can generate with:
- li r0, CONSTANT1
- evmergelo r0, r0, r0
- li r0, CONSTANT2
-
- I don't know how efficient it would be to allow bigger constants,
- considering we'll have an extra 'ori' for every 'li'. I doubt 5
- instructions is better than a 64-bit memory load, but I don't
- have the e500 timing specs. */
- if (mode == V2SImode)
- {
- cst = INTVAL (CONST_VECTOR_ELT (op, 0));
- cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
- return cst >= -0x7fff && cst <= 0x7fff
- && cst2 >= -0x7fff && cst2 <= 0x7fff;
- }
- }
-
return false;
})
@@ -1135,12 +1100,6 @@ (define_predicate "input_operand"
&& easy_vector_constant (op, mode))
return 1;
- /* Do not allow invalid E500 subregs. */
- if (TARGET_SPE
- && GET_CODE (op) == SUBREG
- && invalid_e500_subreg (op, mode))
- return 0;
-
/* For floating-point or multi-word mode, the only remaining valid type
is a register. */
if (SCALAR_FLOAT_MODE_P (mode)
@@ -1199,16 +1158,10 @@ (define_predicate "splat_input_operand"
return gpc_reg_operand (op, mode);
})
-;; Return true if OP is a non-immediate operand and not an invalid
-;; SUBREG operation on the e500.
+;; Return true if OP is a non-immediate operand.
(define_predicate "rs6000_nonimmediate_operand"
(match_code "reg,subreg,mem")
{
- if (TARGET_SPE
- && GET_CODE (op) == SUBREG
- && invalid_e500_subreg (op, mode))
- return 0;
-
return nonimmediate_operand (op, mode);
})
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index ebe005a..01c62b3 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -30,11 +30,9 @@
RS6000_BUILTIN_3 -- 3 arg builtins
RS6000_BUILTIN_A -- ABS builtins
RS6000_BUILTIN_D -- DST builtins
- RS6000_BUILTIN_E -- SPE EVSEL builtins.
RS6000_BUILTIN_H -- HTM builtins
RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins
RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins
- RS6000_BUILTIN_S -- SPE predicate builtins
RS6000_BUILTIN_X -- special builtins
Each of the above macros takes 4 arguments:
@@ -68,10 +66,6 @@
#error "RS6000_BUILTIN_D is not defined."
#endif
-#ifndef RS6000_BUILTIN_E
- #error "RS6000_BUILTIN_E is not defined."
-#endif
-
#ifndef RS6000_BUILTIN_H
#error "RS6000_BUILTIN_H is not defined."
#endif
@@ -84,10 +78,6 @@
#error "RS6000_BUILTIN_Q is not defined."
#endif
-#ifndef RS6000_BUILTIN_S
- #error "RS6000_BUILTIN_S is not defined."
-#endif
-
#ifndef RS6000_BUILTIN_X
#error "RS6000_BUILTIN_X is not defined."
#endif
@@ -551,55 +541,6 @@
| RS6000_BTC_VOID), \
CODE_FOR_ ## ICODE) /* ICODE */
-/* SPE convenience macros. */
-#define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_spe_" NAME, /* NAME */ \
- RS6000_BTM_SPE, /* MASK */ \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_UNARY), \
- CODE_FOR_ ## ICODE) /* ICODE */
-
-#define BU_SPE_2(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_2 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_spe_" NAME, /* NAME */ \
- RS6000_BTM_SPE, /* MASK */ \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_BINARY), \
- CODE_FOR_ ## ICODE) /* ICODE */
-
-#define BU_SPE_3(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_3 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_spe_" NAME, /* NAME */ \
- RS6000_BTM_SPE, /* MASK */ \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_TERNARY), \
- CODE_FOR_ ## ICODE) /* ICODE */
-
-#define BU_SPE_E(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_E (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_spe_" NAME, /* NAME */ \
- RS6000_BTM_SPE, /* MASK */ \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_EVSEL), \
- CODE_FOR_ ## ICODE) /* ICODE */
-
-#define BU_SPE_P(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_S (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_spe_" NAME, /* NAME */ \
- RS6000_BTM_SPE, /* MASK */ \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_PREDICATE), \
- CODE_FOR_ ## ICODE) /* ICODE */
-
-#define BU_SPE_X(ENUM, NAME, ATTR) \
- RS6000_BUILTIN_X (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_spe_" NAME, /* NAME */ \
- RS6000_BTM_SPE, /* MASK */ \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_SPECIAL), \
- CODE_FOR_nothing) /* ICODE */
-
/* Paired floating point convenience macros. */
#define BU_PAIRED_1(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_1 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \
@@ -2349,10 +2290,10 @@ BU_PAIRED_3 (SUM1, "sum1", FP, paired_sum1)
BU_PAIRED_3 (SELV2SF4, "selv2sf4", CONST, selv2sf4)
/* 2 argument paired floating point builtins. */
-BU_PAIRED_2 (DIVV2SF3, "divv2sf3", FP, paired_divv2sf3)
-BU_PAIRED_2 (ADDV2SF3, "addv2sf3", FP, paired_addv2sf3)
-BU_PAIRED_2 (SUBV2SF3, "subv2sf3", FP, paired_subv2sf3)
-BU_PAIRED_2 (MULV2SF3, "mulv2sf3", FP, paired_mulv2sf3)
+BU_PAIRED_2 (DIVV2SF3, "divv2sf3", FP, divv2sf3)
+BU_PAIRED_2 (ADDV2SF3, "addv2sf3", FP, addv2sf3)
+BU_PAIRED_2 (SUBV2SF3, "subv2sf3", FP, subv2sf3)
+BU_PAIRED_2 (MULV2SF3, "mulv2sf3", FP, mulv2sf3)
BU_PAIRED_2 (MULS0, "muls0", FP, paired_muls0)
BU_PAIRED_2 (MULS1, "muls1", FP, paired_muls1)
BU_PAIRED_2 (MERGE00, "merge00", CONST, paired_merge00)
@@ -2361,9 +2302,9 @@ BU_PAIRED_2 (MERGE10, "merge10", CONST, paired_merge10)
BU_PAIRED_2 (MERGE11, "merge11", CONST, paired_merge11)
/* 1 argument paired floating point builtin functions. */
-BU_PAIRED_1 (ABSV2SF2, "absv2sf2", CONST, paired_absv2sf2)
+BU_PAIRED_1 (ABSV2SF2, "absv2sf2", CONST, absv2sf2)
BU_PAIRED_1 (NABSV2SF2, "nabsv2sf2", CONST, nabsv2sf2)
-BU_PAIRED_1 (NEGV2SF2, "negv2sf2", CONST, paired_negv2sf2)
+BU_PAIRED_1 (NEGV2SF2, "negv2sf2", CONST, negv2sf2)
BU_PAIRED_1 (SQRTV2SF2, "sqrtv2sf2", FP, sqrtv2sf2)
BU_PAIRED_1 (RESV2SF, "resv2sf2", FP, resv2sf2)
@@ -2375,248 +2316,6 @@ BU_PAIRED_X (LX, "lx", MISC)
BU_PAIRED_P (CMPU0, "cmpu0", CONST, paired_cmpu0)
BU_PAIRED_P (CMPU1, "cmpu1", CONST, paired_cmpu1)
\f
-/* PowerPC E500 builtins (SPE). */
-
-BU_SPE_2 (EVADDW, "evaddw", MISC, addv2si3)
-BU_SPE_2 (EVAND, "evand", MISC, andv2si3)
-BU_SPE_2 (EVANDC, "evandc", MISC, spe_evandc)
-BU_SPE_2 (EVDIVWS, "evdivws", MISC, divv2si3)
-BU_SPE_2 (EVDIVWU, "evdivwu", MISC, spe_evdivwu)
-BU_SPE_2 (EVEQV, "eveqv", MISC, spe_eveqv)
-BU_SPE_2 (EVFSADD, "evfsadd", MISC, spe_evfsadd)
-BU_SPE_2 (EVFSDIV, "evfsdiv", MISC, spe_evfsdiv)
-BU_SPE_2 (EVFSMUL, "evfsmul", MISC, spe_evfsmul)
-BU_SPE_2 (EVFSSUB, "evfssub", MISC, spe_evfssub)
-BU_SPE_2 (EVMERGEHI, "evmergehi", MISC, spe_evmergehi)
-BU_SPE_2 (EVMERGEHILO, "evmergehilo", MISC, spe_evmergehilo)
-BU_SPE_2 (EVMERGELO, "evmergelo", MISC, spe_evmergelo)
-BU_SPE_2 (EVMERGELOHI, "evmergelohi", MISC, spe_evmergelohi)
-BU_SPE_2 (EVMHEGSMFAA, "evmhegsmfaa", MISC, spe_evmhegsmfaa)
-BU_SPE_2 (EVMHEGSMFAN, "evmhegsmfan", MISC, spe_evmhegsmfan)
-BU_SPE_2 (EVMHEGSMIAA, "evmhegsmiaa", MISC, spe_evmhegsmiaa)
-BU_SPE_2 (EVMHEGSMIAN, "evmhegsmian", MISC, spe_evmhegsmian)
-BU_SPE_2 (EVMHEGUMIAA, "evmhegumiaa", MISC, spe_evmhegumiaa)
-BU_SPE_2 (EVMHEGUMIAN, "evmhegumian", MISC, spe_evmhegumian)
-BU_SPE_2 (EVMHESMF, "evmhesmf", MISC, spe_evmhesmf)
-BU_SPE_2 (EVMHESMFA, "evmhesmfa", MISC, spe_evmhesmfa)
-BU_SPE_2 (EVMHESMFAAW, "evmhesmfaaw", MISC, spe_evmhesmfaaw)
-BU_SPE_2 (EVMHESMFANW, "evmhesmfanw", MISC, spe_evmhesmfanw)
-BU_SPE_2 (EVMHESMI, "evmhesmi", MISC, spe_evmhesmi)
-BU_SPE_2 (EVMHESMIA, "evmhesmia", MISC, spe_evmhesmia)
-BU_SPE_2 (EVMHESMIAAW, "evmhesmiaaw", MISC, spe_evmhesmiaaw)
-BU_SPE_2 (EVMHESMIANW, "evmhesmianw", MISC, spe_evmhesmianw)
-BU_SPE_2 (EVMHESSF, "evmhessf", MISC, spe_evmhessf)
-BU_SPE_2 (EVMHESSFA, "evmhessfa", MISC, spe_evmhessfa)
-BU_SPE_2 (EVMHESSFAAW, "evmhessfaaw", MISC, spe_evmhessfaaw)
-BU_SPE_2 (EVMHESSFANW, "evmhessfanw", MISC, spe_evmhessfanw)
-BU_SPE_2 (EVMHESSIAAW, "evmhessiaaw", MISC, spe_evmhessiaaw)
-BU_SPE_2 (EVMHESSIANW, "evmhessianw", MISC, spe_evmhessianw)
-BU_SPE_2 (EVMHEUMI, "evmheumi", MISC, spe_evmheumi)
-BU_SPE_2 (EVMHEUMIA, "evmheumia", MISC, spe_evmheumia)
-BU_SPE_2 (EVMHEUMIAAW, "evmheumiaaw", MISC, spe_evmheumiaaw)
-BU_SPE_2 (EVMHEUMIANW, "evmheumianw", MISC, spe_evmheumianw)
-BU_SPE_2 (EVMHEUSIAAW, "evmheusiaaw", MISC, spe_evmheusiaaw)
-BU_SPE_2 (EVMHEUSIANW, "evmheusianw", MISC, spe_evmheusianw)
-BU_SPE_2 (EVMHOGSMFAA, "evmhogsmfaa", MISC, spe_evmhogsmfaa)
-BU_SPE_2 (EVMHOGSMFAN, "evmhogsmfan", MISC, spe_evmhogsmfan)
-BU_SPE_2 (EVMHOGSMIAA, "evmhogsmiaa", MISC, spe_evmhogsmiaa)
-BU_SPE_2 (EVMHOGSMIAN, "evmhogsmian", MISC, spe_evmhogsmian)
-BU_SPE_2 (EVMHOGUMIAA, "evmhogumiaa", MISC, spe_evmhogumiaa)
-BU_SPE_2 (EVMHOGUMIAN, "evmhogumian", MISC, spe_evmhogumian)
-BU_SPE_2 (EVMHOSMF, "evmhosmf", MISC, spe_evmhosmf)
-BU_SPE_2 (EVMHOSMFA, "evmhosmfa", MISC, spe_evmhosmfa)
-BU_SPE_2 (EVMHOSMFAAW, "evmhosmfaaw", MISC, spe_evmhosmfaaw)
-BU_SPE_2 (EVMHOSMFANW, "evmhosmfanw", MISC, spe_evmhosmfanw)
-BU_SPE_2 (EVMHOSMI, "evmhosmi", MISC, spe_evmhosmi)
-BU_SPE_2 (EVMHOSMIA, "evmhosmia", MISC, spe_evmhosmia)
-BU_SPE_2 (EVMHOSMIAAW, "evmhosmiaaw", MISC, spe_evmhosmiaaw)
-BU_SPE_2 (EVMHOSMIANW, "evmhosmianw", MISC, spe_evmhosmianw)
-BU_SPE_2 (EVMHOSSF, "evmhossf", MISC, spe_evmhossf)
-BU_SPE_2 (EVMHOSSFA, "evmhossfa", MISC, spe_evmhossfa)
-BU_SPE_2 (EVMHOSSFAAW, "evmhossfaaw", MISC, spe_evmhossfaaw)
-BU_SPE_2 (EVMHOSSFANW, "evmhossfanw", MISC, spe_evmhossfanw)
-BU_SPE_2 (EVMHOSSIAAW, "evmhossiaaw", MISC, spe_evmhossiaaw)
-BU_SPE_2 (EVMHOSSIANW, "evmhossianw", MISC, spe_evmhossianw)
-BU_SPE_2 (EVMHOUMI, "evmhoumi", MISC, spe_evmhoumi)
-BU_SPE_2 (EVMHOUMIA, "evmhoumia", MISC, spe_evmhoumia)
-BU_SPE_2 (EVMHOUMIAAW, "evmhoumiaaw", MISC, spe_evmhoumiaaw)
-BU_SPE_2 (EVMHOUMIANW, "evmhoumianw", MISC, spe_evmhoumianw)
-BU_SPE_2 (EVMHOUSIAAW, "evmhousiaaw", MISC, spe_evmhousiaaw)
-BU_SPE_2 (EVMHOUSIANW, "evmhousianw", MISC, spe_evmhousianw)
-BU_SPE_2 (EVMWHSMF, "evmwhsmf", MISC, spe_evmwhsmf)
-BU_SPE_2 (EVMWHSMFA, "evmwhsmfa", MISC, spe_evmwhsmfa)
-BU_SPE_2 (EVMWHSMI, "evmwhsmi", MISC, spe_evmwhsmi)
-BU_SPE_2 (EVMWHSMIA, "evmwhsmia", MISC, spe_evmwhsmia)
-BU_SPE_2 (EVMWHSSF, "evmwhssf", MISC, spe_evmwhssf)
-BU_SPE_2 (EVMWHSSFA, "evmwhssfa", MISC, spe_evmwhssfa)
-BU_SPE_2 (EVMWHUMI, "evmwhumi", MISC, spe_evmwhumi)
-BU_SPE_2 (EVMWHUMIA, "evmwhumia", MISC, spe_evmwhumia)
-BU_SPE_2 (EVMWLSMIAAW, "evmwlsmiaaw", MISC, spe_evmwlsmiaaw)
-BU_SPE_2 (EVMWLSMIANW, "evmwlsmianw", MISC, spe_evmwlsmianw)
-BU_SPE_2 (EVMWLSSIAAW, "evmwlssiaaw", MISC, spe_evmwlssiaaw)
-BU_SPE_2 (EVMWLSSIANW, "evmwlssianw", MISC, spe_evmwlssianw)
-BU_SPE_2 (EVMWLUMI, "evmwlumi", MISC, spe_evmwlumi)
-BU_SPE_2 (EVMWLUMIA, "evmwlumia", MISC, spe_evmwlumia)
-BU_SPE_2 (EVMWLUMIAAW, "evmwlumiaaw", MISC, spe_evmwlumiaaw)
-BU_SPE_2 (EVMWLUMIANW, "evmwlumianw", MISC, spe_evmwlumianw)
-BU_SPE_2 (EVMWLUSIAAW, "evmwlusiaaw", MISC, spe_evmwlusiaaw)
-BU_SPE_2 (EVMWLUSIANW, "evmwlusianw", MISC, spe_evmwlusianw)
-BU_SPE_2 (EVMWSMF, "evmwsmf", MISC, spe_evmwsmf)
-BU_SPE_2 (EVMWSMFA, "evmwsmfa", MISC, spe_evmwsmfa)
-BU_SPE_2 (EVMWSMFAA, "evmwsmfaa", MISC, spe_evmwsmfaa)
-BU_SPE_2 (EVMWSMFAN, "evmwsmfan", MISC, spe_evmwsmfan)
-BU_SPE_2 (EVMWSMI, "evmwsmi", MISC, spe_evmwsmi)
-BU_SPE_2 (EVMWSMIA, "evmwsmia", MISC, spe_evmwsmia)
-BU_SPE_2 (EVMWSMIAA, "evmwsmiaa", MISC, spe_evmwsmiaa)
-BU_SPE_2 (EVMWSMIAN, "evmwsmian", MISC, spe_evmwsmian)
-BU_SPE_2 (EVMWSSF, "evmwssf", MISC, spe_evmwssf)
-BU_SPE_2 (EVMWSSFA, "evmwssfa", MISC, spe_evmwssfa)
-BU_SPE_2 (EVMWSSFAA, "evmwssfaa", MISC, spe_evmwssfaa)
-BU_SPE_2 (EVMWSSFAN, "evmwssfan", MISC, spe_evmwssfan)
-BU_SPE_2 (EVMWUMI, "evmwumi", MISC, spe_evmwumi)
-BU_SPE_2 (EVMWUMIA, "evmwumia", MISC, spe_evmwumia)
-BU_SPE_2 (EVMWUMIAA, "evmwumiaa", MISC, spe_evmwumiaa)
-BU_SPE_2 (EVMWUMIAN, "evmwumian", MISC, spe_evmwumian)
-BU_SPE_2 (EVNAND, "evnand", MISC, spe_evnand)
-BU_SPE_2 (EVNOR, "evnor", MISC, spe_evnor)
-BU_SPE_2 (EVOR, "evor", MISC, spe_evor)
-BU_SPE_2 (EVORC, "evorc", MISC, spe_evorc)
-BU_SPE_2 (EVRLW, "evrlw", MISC, spe_evrlw)
-BU_SPE_2 (EVSLW, "evslw", MISC, spe_evslw)
-BU_SPE_2 (EVSRWS, "evsrws", MISC, spe_evsrws)
-BU_SPE_2 (EVSRWU, "evsrwu", MISC, spe_evsrwu)
-BU_SPE_2 (EVSUBFW, "evsubfw", MISC, subv2si3)
-
-/* SPE binary operations expecting a 5-bit unsigned literal. */
-BU_SPE_2 (EVADDIW, "evaddiw", MISC, spe_evaddiw)
-
-BU_SPE_2 (EVRLWI, "evrlwi", MISC, spe_evrlwi)
-BU_SPE_2 (EVSLWI, "evslwi", MISC, spe_evslwi)
-BU_SPE_2 (EVSRWIS, "evsrwis", MISC, spe_evsrwis)
-BU_SPE_2 (EVSRWIU, "evsrwiu", MISC, spe_evsrwiu)
-BU_SPE_2 (EVSUBIFW, "evsubifw", MISC, spe_evsubifw)
-BU_SPE_2 (EVMWHSSFAA, "evmwhssfaa", MISC, spe_evmwhssfaa)
-BU_SPE_2 (EVMWHSSMAA, "evmwhssmaa", MISC, spe_evmwhssmaa)
-BU_SPE_2 (EVMWHSMFAA, "evmwhsmfaa", MISC, spe_evmwhsmfaa)
-BU_SPE_2 (EVMWHSMIAA, "evmwhsmiaa", MISC, spe_evmwhsmiaa)
-BU_SPE_2 (EVMWHUSIAA, "evmwhusiaa", MISC, spe_evmwhusiaa)
-BU_SPE_2 (EVMWHUMIAA, "evmwhumiaa", MISC, spe_evmwhumiaa)
-BU_SPE_2 (EVMWHSSFAN, "evmwhssfan", MISC, spe_evmwhssfan)
-BU_SPE_2 (EVMWHSSIAN, "evmwhssian", MISC, spe_evmwhssian)
-BU_SPE_2 (EVMWHSMFAN, "evmwhsmfan", MISC, spe_evmwhsmfan)
-BU_SPE_2 (EVMWHSMIAN, "evmwhsmian", MISC, spe_evmwhsmian)
-BU_SPE_2 (EVMWHUSIAN, "evmwhusian", MISC, spe_evmwhusian)
-BU_SPE_2 (EVMWHUMIAN, "evmwhumian", MISC, spe_evmwhumian)
-BU_SPE_2 (EVMWHGSSFAA, "evmwhgssfaa", MISC, spe_evmwhgssfaa)
-BU_SPE_2 (EVMWHGSMFAA, "evmwhgsmfaa", MISC, spe_evmwhgsmfaa)
-BU_SPE_2 (EVMWHGSMIAA, "evmwhgsmiaa", MISC, spe_evmwhgsmiaa)
-BU_SPE_2 (EVMWHGUMIAA, "evmwhgumiaa", MISC, spe_evmwhgumiaa)
-BU_SPE_2 (EVMWHGSSFAN, "evmwhgssfan", MISC, spe_evmwhgssfan)
-BU_SPE_2 (EVMWHGSMFAN, "evmwhgsmfan", MISC, spe_evmwhgsmfan)
-BU_SPE_2 (EVMWHGSMIAN, "evmwhgsmian", MISC, spe_evmwhgsmian)
-BU_SPE_2 (EVMWHGUMIAN, "evmwhgumian", MISC, spe_evmwhgumian)
-BU_SPE_2 (BRINC, "brinc", MISC, spe_brinc)
-BU_SPE_2 (EVXOR, "evxor", MISC, xorv2si3)
-
-/* SPE predicate builtins. */
-BU_SPE_P (EVCMPEQ, "evcmpeq", MISC, spe_evcmpeq)
-BU_SPE_P (EVCMPGTS, "evcmpgts", MISC, spe_evcmpgts)
-BU_SPE_P (EVCMPGTU, "evcmpgtu", MISC, spe_evcmpgtu)
-BU_SPE_P (EVCMPLTS, "evcmplts", MISC, spe_evcmplts)
-BU_SPE_P (EVCMPLTU, "evcmpltu", MISC, spe_evcmpltu)
-BU_SPE_P (EVFSCMPEQ, "evfscmpeq", MISC, spe_evfscmpeq)
-BU_SPE_P (EVFSCMPGT, "evfscmpgt", MISC, spe_evfscmpgt)
-BU_SPE_P (EVFSCMPLT, "evfscmplt", MISC, spe_evfscmplt)
-BU_SPE_P (EVFSTSTEQ, "evfststeq", MISC, spe_evfststeq)
-BU_SPE_P (EVFSTSTGT, "evfststgt", MISC, spe_evfststgt)
-BU_SPE_P (EVFSTSTLT, "evfststlt", MISC, spe_evfststlt)
-
-/* SPE evsel builtins. */
-BU_SPE_E (EVSEL_CMPGTS, "evsel_gts", MISC, spe_evcmpgts)
-BU_SPE_E (EVSEL_CMPGTU, "evsel_gtu", MISC, spe_evcmpgtu)
-BU_SPE_E (EVSEL_CMPLTS, "evsel_lts", MISC, spe_evcmplts)
-BU_SPE_E (EVSEL_CMPLTU, "evsel_ltu", MISC, spe_evcmpltu)
-BU_SPE_E (EVSEL_CMPEQ, "evsel_eq", MISC, spe_evcmpeq)
-BU_SPE_E (EVSEL_FSCMPGT, "evsel_fsgt", MISC, spe_evfscmpgt)
-BU_SPE_E (EVSEL_FSCMPLT, "evsel_fslt", MISC, spe_evfscmplt)
-BU_SPE_E (EVSEL_FSCMPEQ, "evsel_fseq", MISC, spe_evfscmpeq)
-BU_SPE_E (EVSEL_FSTSTGT, "evsel_fststgt", MISC, spe_evfststgt)
-BU_SPE_E (EVSEL_FSTSTLT, "evsel_fststlt", MISC, spe_evfststlt)
-BU_SPE_E (EVSEL_FSTSTEQ, "evsel_fststeq", MISC, spe_evfststeq)
-
-BU_SPE_1 (EVABS, "evabs", CONST, absv2si2)
-BU_SPE_1 (EVADDSMIAAW, "evaddsmiaaw", CONST, spe_evaddsmiaaw)
-BU_SPE_1 (EVADDSSIAAW, "evaddssiaaw", CONST, spe_evaddssiaaw)
-BU_SPE_1 (EVADDUMIAAW, "evaddumiaaw", CONST, spe_evaddumiaaw)
-BU_SPE_1 (EVADDUSIAAW, "evaddusiaaw", CONST, spe_evaddusiaaw)
-BU_SPE_1 (EVCNTLSW, "evcntlsw", CONST, spe_evcntlsw)
-BU_SPE_1 (EVCNTLZW, "evcntlzw", CONST, spe_evcntlzw)
-BU_SPE_1 (EVEXTSB, "evextsb", CONST, spe_evextsb)
-BU_SPE_1 (EVEXTSH, "evextsh", CONST, spe_evextsh)
-BU_SPE_1 (EVFSABS, "evfsabs", CONST, spe_evfsabs)
-BU_SPE_1 (EVFSCFSF, "evfscfsf", CONST, spe_evfscfsf)
-BU_SPE_1 (EVFSCFSI, "evfscfsi", CONST, spe_evfscfsi)
-BU_SPE_1 (EVFSCFUF, "evfscfuf", CONST, spe_evfscfuf)
-BU_SPE_1 (EVFSCFUI, "evfscfui", CONST, spe_evfscfui)
-BU_SPE_1 (EVFSCTSF, "evfsctsf", CONST, spe_evfsctsf)
-BU_SPE_1 (EVFSCTSI, "evfsctsi", CONST, spe_evfsctsi)
-BU_SPE_1 (EVFSCTSIZ, "evfsctsiz", CONST, spe_evfsctsiz)
-BU_SPE_1 (EVFSCTUF, "evfsctuf", CONST, spe_evfsctuf)
-BU_SPE_1 (EVFSCTUI, "evfsctui", CONST, spe_evfsctui)
-BU_SPE_1 (EVFSCTUIZ, "evfsctuiz", CONST, spe_evfsctuiz)
-BU_SPE_1 (EVFSNABS, "evfsnabs", CONST, spe_evfsnabs)
-BU_SPE_1 (EVFSNEG, "evfsneg", CONST, spe_evfsneg)
-BU_SPE_1 (EVMRA, "evmra", CONST, spe_evmra)
-BU_SPE_1 (EVNEG, "evneg", CONST, negv2si2)
-BU_SPE_1 (EVRNDW, "evrndw", CONST, spe_evrndw)
-BU_SPE_1 (EVSUBFSMIAAW, "evsubfsmiaaw", CONST, spe_evsubfsmiaaw)
-BU_SPE_1 (EVSUBFSSIAAW, "evsubfssiaaw", CONST, spe_evsubfssiaaw)
-BU_SPE_1 (EVSUBFUMIAAW, "evsubfumiaaw", CONST, spe_evsubfumiaaw)
-BU_SPE_1 (EVSUBFUSIAAW, "evsubfusiaaw", CONST, spe_evsubfusiaaw)
-
-/* SPE builtins that are handled as special cases. */
-BU_SPE_X (EVLDD, "evldd", MISC)
-BU_SPE_X (EVLDDX, "evlddx", MISC)
-BU_SPE_X (EVLDH, "evldh", MISC)
-BU_SPE_X (EVLDHX, "evldhx", MISC)
-BU_SPE_X (EVLDW, "evldw", MISC)
-BU_SPE_X (EVLDWX, "evldwx", MISC)
-BU_SPE_X (EVLHHESPLAT, "evlhhesplat", MISC)
-BU_SPE_X (EVLHHESPLATX, "evlhhesplatx", MISC)
-BU_SPE_X (EVLHHOSSPLAT, "evlhhossplat", MISC)
-BU_SPE_X (EVLHHOSSPLATX, "evlhhossplatx", MISC)
-BU_SPE_X (EVLHHOUSPLAT, "evlhhousplat", MISC)
-BU_SPE_X (EVLHHOUSPLATX, "evlhhousplatx", MISC)
-BU_SPE_X (EVLWHE, "evlwhe", MISC)
-BU_SPE_X (EVLWHEX, "evlwhex", MISC)
-BU_SPE_X (EVLWHOS, "evlwhos", MISC)
-BU_SPE_X (EVLWHOSX, "evlwhosx", MISC)
-BU_SPE_X (EVLWHOU, "evlwhou", MISC)
-BU_SPE_X (EVLWHOUX, "evlwhoux", MISC)
-BU_SPE_X (EVLWHSPLAT, "evlwhsplat", MISC)
-BU_SPE_X (EVLWHSPLATX, "evlwhsplatx", MISC)
-BU_SPE_X (EVLWWSPLAT, "evlwwsplat", MISC)
-BU_SPE_X (EVLWWSPLATX, "evlwwsplatx", MISC)
-BU_SPE_X (EVSPLATFI, "evsplatfi", MISC)
-BU_SPE_X (EVSPLATI, "evsplati", MISC)
-BU_SPE_X (EVSTDD, "evstdd", MISC)
-BU_SPE_X (EVSTDDX, "evstddx", MISC)
-BU_SPE_X (EVSTDH, "evstdh", MISC)
-BU_SPE_X (EVSTDHX, "evstdhx", MISC)
-BU_SPE_X (EVSTDW, "evstdw", MISC)
-BU_SPE_X (EVSTDWX, "evstdwx", MISC)
-BU_SPE_X (EVSTWHE, "evstwhe", MISC)
-BU_SPE_X (EVSTWHEX, "evstwhex", MISC)
-BU_SPE_X (EVSTWHO, "evstwho", MISC)
-BU_SPE_X (EVSTWHOX, "evstwhox", MISC)
-BU_SPE_X (EVSTWWE, "evstwwe", MISC)
-BU_SPE_X (EVSTWWEX, "evstwwex", MISC)
-BU_SPE_X (EVSTWWO, "evstwwo", MISC)
-BU_SPE_X (EVSTWWOX, "evstwwox", MISC)
-BU_SPE_X (MFSPEFSCR, "mfspefscr", MISC)
-BU_SPE_X (MTSPEFSCR, "mtspefscr", MISC)
-
-\f
/* Power7 builtins, that aren't VSX instructions. */
BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", RS6000_BTM_POPCNTD,
RS6000_BTC_CONST)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index fccbbb7..c3b8224 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -611,10 +611,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_SF__");
/* options from the builtin masks. */
- /* Note that RS6000_BTM_SPE is enabled only if TARGET_SPE
- (e.g. -mspe). */
- if ((bu_mask & RS6000_BTM_SPE) != 0)
- rs6000_define_or_undefine_macro (define_p, "__SPE__");
/* Note that RS6000_BTM_PAIRED is enabled only if
TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired). */
if ((bu_mask & RS6000_BTM_PAIRED) != 0)
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 2955d97..8a231f5 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -41,7 +41,6 @@ extern int small_data_operand (rtx, machine_mode);
extern bool mem_operand_gpr (rtx, machine_mode);
extern bool mem_operand_ds_form (rtx, machine_mode);
extern bool toc_relative_expr_p (const_rtx, bool);
-extern bool invalid_e500_subreg (rtx, machine_mode);
extern void validate_condition_mode (enum rtx_code, machine_mode);
extern bool legitimate_constant_pool_address_p (const_rtx, machine_mode,
bool);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index a31c608..a2bf968 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -107,7 +107,6 @@ typedef struct rs6000_stack {
int lr_save_offset; /* offset to save LR from initial SP */
int cr_save_offset; /* offset to save CR from initial SP */
int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
- int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
int varargs_save_offset; /* offset to save the varargs registers */
int ehrd_offset; /* offset to EH return data */
int ehcr_offset; /* offset to EH CR field data */
@@ -122,10 +121,7 @@ typedef struct rs6000_stack {
int cr_size; /* size to hold CR if not in fixed area */
int vrsave_size; /* size to hold VRSAVE */
int altivec_padding_size; /* size of altivec alignment padding */
- int spe_gp_size; /* size of 64-bit GPR save size for SPE */
- int spe_padding_size;
HOST_WIDE_INT total_size; /* total bytes allocated for stack */
- int spe_64bit_regs_used;
int savres_strategy;
} rs6000_stack_t;
@@ -133,8 +129,6 @@ typedef struct rs6000_stack {
This is added to the cfun structure. */
typedef struct GTY(()) machine_function
{
- /* Whether the instruction chain has been scanned already. */
- int spe_insn_chain_scanned_p;
/* Flags if __builtin_return_address (n) with n >= 1 was used. */
int ra_needs_full_frame;
/* Flags if __builtin_return_address (0) was used. */
@@ -1249,11 +1243,9 @@ struct processor_costs ppca2_cost = {
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
@@ -1274,9 +1266,6 @@ struct processor_costs ppca2_cost = {
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
- { NAME, ICODE, MASK, ATTR },
-
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
@@ -1286,9 +1275,6 @@ struct processor_costs ppca2_cost = {
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
- { NAME, ICODE, MASK, ATTR },
-
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
@@ -1310,11 +1296,9 @@ static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
/* Support for -mveclibabi=<xxx> to control which vector library to use. */
@@ -1322,7 +1306,6 @@ static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
\f
static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
-static bool spe_func_has_64bit_regs_p (void);
static struct machine_function * rs6000_init_machine_status (void);
static int rs6000_ra_ever_killed (void);
static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
@@ -1352,10 +1335,7 @@ static tree builtin_function_type (machine_mode, machine_mode,
static void rs6000_common_init_builtins (void);
static void paired_init_builtins (void);
static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
-static void spe_init_builtins (void);
static void htm_init_builtins (void);
-static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
-static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
static rs6000_stack_t *rs6000_stack_info (void);
static void is_altivec_return_reg (rtx, void *);
@@ -1770,15 +1750,9 @@ static const struct attribute_spec rs6000_attribute_table[] =
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
-#undef TARGET_DWARF_REGISTER_SPAN
-#define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
-
#undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
#define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
-#undef TARGET_MEMBER_TYPE_FORCES_BLK
-#define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
-
#undef TARGET_PROMOTE_FUNCTION_MODE
#define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
@@ -2032,9 +2006,6 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
? UNITS_PER_VSX_WORD
: UNITS_PER_FP_WORD);
- else if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
- reg_size = UNITS_PER_SPE_WORD;
-
else if (ALTIVEC_REGNO_P (regno))
reg_size = UNITS_PER_ALTIVEC_WORD;
@@ -2137,10 +2108,6 @@ rs6000_hard_regno_mode_ok (int regno, machine_mode mode)
return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
|| mode == V1TImode);
- /* ...but GPRs can hold SIMD data on the SPE in one register. */
- if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
- return 1;
-
/* We cannot put non-VSX TImode or PTImode anywhere except general register
and it must be able to fit within the register set. */
@@ -2791,9 +2758,6 @@ rs6000_debug_reg_global (void)
if (rs6000_altivec_abi)
fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
- if (rs6000_spe_abi)
- fprintf (stderr, DEBUG_FMT_S, "spe_abi", "true");
-
if (rs6000_darwin64_abi)
fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
@@ -3853,7 +3817,6 @@ rs6000_builtin_mask_calculate (void)
return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
| ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
| ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
- | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)
| ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
| ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
| ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
@@ -4190,26 +4153,15 @@ rs6000_option_override_internal (bool global_init_p)
(rs6000_cpu == PROCESSOR_PPC8540
|| rs6000_cpu == PROCESSOR_PPC8548);
- if (!global_options_set.x_rs6000_spe_abi)
- rs6000_spe_abi = spe_capable_cpu;
-
if (!global_options_set.x_rs6000_spe)
rs6000_spe = spe_capable_cpu;
}
- if (global_options_set.x_rs6000_spe_abi
- && rs6000_spe_abi
- && !TARGET_SPE_ABI)
- error ("not configured for SPE ABI");
-
- if (global_options_set.x_rs6000_spe
- && rs6000_spe
- && !TARGET_SPE)
+ if (global_options_set.x_rs6000_spe && rs6000_spe)
error ("not configured for SPE instruction set");
if (main_target_opt != NULL
- && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
- || (main_target_opt->x_rs6000_spe != rs6000_spe)))
+ && main_target_opt->x_rs6000_spe != rs6000_spe)
error ("target attribute or pragma changes SPE ABI");
if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
@@ -4218,13 +4170,6 @@ rs6000_option_override_internal (bool global_init_p)
{
if (TARGET_ALTIVEC)
error ("AltiVec not supported in this target");
- if (TARGET_SPE)
- error ("SPE not supported in this target");
- }
- if (rs6000_cpu == PROCESSOR_PPCE6500)
- {
- if (TARGET_SPE)
- error ("SPE not supported in this target");
}
/* If we are optimizing big endian systems for space, use the load/store
@@ -5858,15 +5803,6 @@ rs6000_preferred_simd_mode (machine_mode mode)
return V16QImode;
default:;
}
- if (TARGET_SPE)
- switch (mode)
- {
- case SFmode:
- return V2SFmode;
- case SImode:
- return V2SImode;
- default:;
- }
if (TARGET_PAIRED_FLOAT
&& mode == SFmode)
return V2SFmode;
@@ -6971,7 +6907,7 @@ xxspltib_constant_p (rtx op,
const char *
output_vec_const_move (rtx *operands)
{
- int cst, cst2, shift;
+ int shift;
machine_mode mode;
rtx dest, vec;
@@ -7063,23 +6999,7 @@ output_vec_const_move (rtx *operands)
}
}
- gcc_assert (TARGET_SPE);
-
- /* Vector constant 0 is handled as a splitter of V2SI, and in the
- pattern of V1DI, V4HI, and V2SF.
-
- FIXME: We should probably return # and add post reload
- splitters for these, but this way is so easy ;-). */
- cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
- cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
- operands[1] = CONST_VECTOR_ELT (vec, 0);
- operands[2] = CONST_VECTOR_ELT (vec, 1);
- if (cst == cst2)
- return "li %0,%1\n\tevmergelo %0,%0,%0";
- else if (WORDS_BIG_ENDIAN)
- return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
- else
- return "li %0,%2\n\tevmergelo %0,%0,%0\n\tli %0,%1";
+ gcc_unreachable ();
}
/* Initialize TARGET of vector PAIRED to VALS. */
@@ -8151,21 +8071,6 @@ rs6000_split_v4si_init (rtx operands[])
gcc_unreachable ();
}
-/* Return TRUE if OP is an invalid SUBREG operation on the e500. */
-
-bool
-invalid_e500_subreg (rtx op, machine_mode mode)
-{
- if (TARGET_SPE
- && GET_CODE (op) == SUBREG
- && mode == SImode
- && REG_P (SUBREG_REG (op))
- && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
- return true;
-
- return false;
-}
-
/* Return alignment of TYPE. Existing alignment is ALIGN. HOW
selects whether the alignment is abi mandated, optional, or
both abi and optional alignment. */
@@ -8177,8 +8082,7 @@ rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
{
if (TREE_CODE (type) == VECTOR_TYPE)
{
- if ((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (type)))
- || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type))))
+ if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type)))
{
if (align < 64)
align = 64;
@@ -8303,13 +8207,6 @@ small_data_operand (rtx op ATTRIBUTE_UNUSED,
if (DEFAULT_ABI != ABI_V4)
return 0;
- /* Vector and float memory instructions have a limited offset on the
- SPE, so using a vector or float variable directly as an operand is
- not useful. */
- if (TARGET_SPE
- && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
- return 0;
-
if (GET_CODE (op) == SYMBOL_REF)
sym_ref = op;
@@ -9062,7 +8959,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
>= 0x10000 - extra)
- && !SPE_VECTOR_MODE (mode))
+ && !PAIRED_VECTOR_MODE (mode))
{
HOST_WIDE_INT high_int, low_int;
rtx sum;
@@ -9087,11 +8984,11 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
return gen_rtx_PLUS (Pmode, XEXP (x, 0),
force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
}
- else if (SPE_VECTOR_MODE (mode))
+ else if (PAIRED_VECTOR_MODE (mode))
{
if (mode == DImode)
return x;
- /* We accept [reg + reg] and [reg + OFFSET]. */
+ /* We accept [reg + reg]. */
if (GET_CODE (x) == PLUS)
{
@@ -9100,13 +8997,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
rtx y;
op1 = force_reg (Pmode, op1);
-
- if (GET_CODE (op2) != REG
- && (GET_CODE (op2) != CONST_INT
- || !SPE_CONST_OFFSET_OK (INTVAL (op2))
- || (GET_MODE_SIZE (mode) > 8
- && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
- op2 = force_reg (Pmode, op2);
+ op2 = force_reg (Pmode, op2);
/* We can't always do [reg + reg] for these, because [reg +
reg + offset] is not a legitimate addressing mode. */
@@ -9850,7 +9741,7 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode,
&& INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
&& CONST_INT_P (XEXP (x, 1))
&& reg_offset_p
- && !SPE_VECTOR_MODE (mode)
+ && !PAIRED_VECTOR_MODE (mode)
&& (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
{
HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
@@ -9891,7 +9782,7 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode,
&& reg_offset_p
&& !quad_offset_p
&& (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
- && !SPE_VECTOR_MODE (mode)
+ && !PAIRED_VECTOR_MODE (mode)
#if TARGET_MACHO
&& DEFAULT_ABI == ABI_DARWIN
&& (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
@@ -10365,20 +10256,6 @@ rs6000_conditional_register_usage (void)
fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
= call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
- if (TARGET_SPE)
- {
- global_regs[SPEFSCR_REGNO] = 1;
- /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
- registers in prologues and epilogues. We no longer use r14
- for FIXED_SCRATCH, but we're keeping r14 out of the allocation
- pool for link-compatibility with older versions of GCC. Once
- "old" code has died out, we can return r14 to the allocation
- pool. */
- fixed_regs[14]
- = call_used_regs[14]
- = call_really_used_regs[14] = 1;
- }
-
if (!TARGET_ALTIVEC && !TARGET_VSX)
{
for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
@@ -11282,25 +11159,6 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
emit_set:
emit_insn (gen_rtx_SET (operands[0], operands[1]));
}
-
-/* Return true if a structure, union or array containing FIELD should be
- accessed using `BLKMODE'.
-
- For the SPE, simd types are V2SI, and gcc can be tempted to put the
- entire thing in a DI and use subregs to access the internals.
- store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
- back-end. Because a single GPR can hold a V2SI, but not a DI, the
- best thing to do is set structs to BLKmode and avoid Severe Tire
- Damage.
-
- On e500 v2, DF and DI modes suffer from the same anomaly. DF can
- fit into 1, whereas DI still needs two. */
-
-static bool
-rs6000_member_type_forces_blk (const_tree field, machine_mode)
-{
- return (TARGET_SPE && TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE);
-}
\f
/* Nonzero if we can use a floating-point register to pass this arg. */
#define USE_FP_FOR_ARG_P(CUM,MODE) \
@@ -11759,7 +11617,7 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
rs6000_passes_long_double = true;
}
if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
- || SPE_VECTOR_MODE (return_mode))
+ || PAIRED_VECTOR_MODE (return_mode))
rs6000_passes_vector = true;
}
}
@@ -11937,7 +11795,7 @@ rs6000_function_arg_boundary (machine_mode mode, const_tree type)
return 64;
else if (FLOAT128_VECTOR_P (mode))
return 128;
- else if (SPE_VECTOR_MODE (mode)
+ else if (PAIRED_VECTOR_MODE (mode)
|| (type && TREE_CODE (type) == VECTOR_TYPE
&& int_size_in_bytes (type) >= 8
&& int_size_in_bytes (type) < 16))
@@ -12219,7 +12077,7 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
rs6000_passes_long_double = true;
}
if ((named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
- || (SPE_VECTOR_MODE (mode)
+ || (PAIRED_VECTOR_MODE (mode)
&& !cum->stdarg
&& cum->sysv_gregno <= GP_ARG_MAX_REG))
rs6000_passes_vector = true;
@@ -12278,11 +12136,6 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
}
}
}
- else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
- && !cum->stdarg
- && cum->sysv_gregno <= GP_ARG_MAX_REG)
- cum->sysv_gregno++;
-
else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
{
int size = int_size_in_bytes (type);
@@ -12414,44 +12267,6 @@ rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
0);
}
-/* Determine where to put a SIMD argument on the SPE. */
-static rtx
-rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, machine_mode mode,
- const_tree type)
-{
- int gregno = cum->sysv_gregno;
-
- if (cum->stdarg)
- {
- int n_words = rs6000_arg_size (mode, type);
-
- /* SPE vectors are put in odd registers. */
- if (n_words == 2 && (gregno & 1) == 0)
- gregno += 1;
-
- if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
- {
- rtx r1, r2;
- machine_mode m = SImode;
-
- r1 = gen_rtx_REG (m, gregno);
- r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
- r2 = gen_rtx_REG (m, gregno + 1);
- r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
- return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
- }
- else
- return NULL_RTX;
- }
- else
- {
- if (gregno <= GP_ARG_MAX_REG)
- return gen_rtx_REG (mode, gregno);
- else
- return NULL_RTX;
- }
-}
-
/* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
structure between cum->intoffset and bitpos to integer registers. */
@@ -12818,17 +12633,12 @@ rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
&& (cum->call_cookie & CALL_LIBCALL) == 0
&& (cum->stdarg
|| (cum->nargs_prototype < 0
- && (cum->prototype || TARGET_NO_PROTOTYPE))))
- {
- /* For the SPE, we need to crxor CR6 always. */
- if (TARGET_SPE_ABI)
- return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
- else if (TARGET_HARD_FLOAT)
- return GEN_INT (cum->call_cookie
- | ((cum->fregno == FP_ARG_MIN_REG)
- ? CALL_V4_SET_FP_ARGS
- : CALL_V4_CLEAR_FP_ARGS));
- }
+ && (cum->prototype || TARGET_NO_PROTOTYPE)))
+ && TARGET_HARD_FLOAT)
+ return GEN_INT (cum->call_cookie
+ | ((cum->fregno == FP_ARG_MIN_REG)
+ ? CALL_V4_SET_FP_ARGS
+ : CALL_V4_CLEAR_FP_ARGS));
return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
}
@@ -12913,8 +12723,6 @@ rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
}
}
- else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
- return rs6000_spe_function_arg (cum, mode, type);
else if (abi == ABI_V4)
{
@@ -14056,11 +13864,9 @@ def_builtin (const char *name, tree type, enum rs6000_builtins code)
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -14071,11 +13877,9 @@ def_builtin (const char *name, tree type, enum rs6000_builtins code)
#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_3arg[] =
@@ -14091,11 +13895,9 @@ static const struct builtin_description bdesc_3arg[] =
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -14106,11 +13908,9 @@ static const struct builtin_description bdesc_3arg[] =
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
{ MASK, ICODE, NAME, ENUM },
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_dst[] =
@@ -14126,11 +13926,9 @@ static const struct builtin_description bdesc_dst[] =
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -14141,11 +13939,9 @@ static const struct builtin_description bdesc_dst[] =
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_2arg[] =
@@ -14159,11 +13955,9 @@ static const struct builtin_description bdesc_2arg[] =
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -14172,13 +13966,11 @@ static const struct builtin_description bdesc_2arg[] =
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
{ MASK, ICODE, NAME, ENUM },
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
/* AltiVec predicates. */
@@ -14188,74 +13980,6 @@ static const struct builtin_description bdesc_altivec_preds[] =
#include "rs6000-builtin.def"
};
-/* SPE predicates. */
-#undef RS6000_BUILTIN_0
-#undef RS6000_BUILTIN_1
-#undef RS6000_BUILTIN_2
-#undef RS6000_BUILTIN_3
-#undef RS6000_BUILTIN_A
-#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
-#undef RS6000_BUILTIN_H
-#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
-#undef RS6000_BUILTIN_X
-
-#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
- { MASK, ICODE, NAME, ENUM },
-
-#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
-
-static const struct builtin_description bdesc_spe_predicates[] =
-{
-#include "rs6000-builtin.def"
-};
-
-/* SPE evsel predicates. */
-#undef RS6000_BUILTIN_0
-#undef RS6000_BUILTIN_1
-#undef RS6000_BUILTIN_2
-#undef RS6000_BUILTIN_3
-#undef RS6000_BUILTIN_A
-#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
-#undef RS6000_BUILTIN_H
-#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
-#undef RS6000_BUILTIN_X
-
-#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
- { MASK, ICODE, NAME, ENUM },
-
-#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
-
-static const struct builtin_description bdesc_spe_evsel[] =
-{
-#include "rs6000-builtin.def"
-};
-
/* PAIRED predicates. */
#undef RS6000_BUILTIN_0
#undef RS6000_BUILTIN_1
@@ -14263,11 +13987,9 @@ static const struct builtin_description bdesc_spe_evsel[] =
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -14276,13 +13998,11 @@ static const struct builtin_description bdesc_spe_evsel[] =
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
{ MASK, ICODE, NAME, ENUM },
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_paired_preds[] =
@@ -14298,11 +14018,9 @@ static const struct builtin_description bdesc_paired_preds[] =
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -14313,11 +14031,9 @@ static const struct builtin_description bdesc_paired_preds[] =
{ MASK, ICODE, NAME, ENUM },
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_abs[] =
@@ -14334,11 +14050,9 @@ static const struct builtin_description bdesc_abs[] =
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -14349,11 +14063,9 @@ static const struct builtin_description bdesc_abs[] =
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_1arg[] =
@@ -14369,11 +14081,9 @@ static const struct builtin_description bdesc_1arg[] =
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
@@ -14384,11 +14094,9 @@ static const struct builtin_description bdesc_1arg[] =
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_0arg[] =
@@ -14403,11 +14111,9 @@ static const struct builtin_description bdesc_0arg[] =
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -14416,13 +14122,11 @@ static const struct builtin_description bdesc_0arg[] =
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
{ MASK, ICODE, NAME, ENUM },
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_htm[] =
@@ -14436,11 +14140,9 @@ static const struct builtin_description bdesc_htm[] =
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
/* Return true if a builtin function is overloaded. */
bool
@@ -14540,9 +14242,7 @@ rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
if (icode == CODE_FOR_altivec_vspltisb
|| icode == CODE_FOR_altivec_vspltish
- || icode == CODE_FOR_altivec_vspltisw
- || icode == CODE_FOR_spe_evsplatfi
- || icode == CODE_FOR_spe_evsplati)
+ || icode == CODE_FOR_altivec_vspltisw)
{
/* Only allow 5-bit *signed* literals. */
if (GET_CODE (op0) != CONST_INT
@@ -14628,24 +14328,7 @@ rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
|| icode == CODE_FOR_altivec_vctuxs
|| icode == CODE_FOR_altivec_vspltb
|| icode == CODE_FOR_altivec_vsplth
- || icode == CODE_FOR_altivec_vspltw
- || icode == CODE_FOR_spe_evaddiw
- || icode == CODE_FOR_spe_evldd
- || icode == CODE_FOR_spe_evldh
- || icode == CODE_FOR_spe_evldw
- || icode == CODE_FOR_spe_evlhhesplat
- || icode == CODE_FOR_spe_evlhhossplat
- || icode == CODE_FOR_spe_evlhhousplat
- || icode == CODE_FOR_spe_evlwhe
- || icode == CODE_FOR_spe_evlwhos
- || icode == CODE_FOR_spe_evlwhou
- || icode == CODE_FOR_spe_evlwhsplat
- || icode == CODE_FOR_spe_evlwwsplat
- || icode == CODE_FOR_spe_evrlwi
- || icode == CODE_FOR_spe_evslwi
- || icode == CODE_FOR_spe_evsrwis
- || icode == CODE_FOR_spe_evsubifw
- || icode == CODE_FOR_spe_evsrwiu)
+ || icode == CODE_FOR_altivec_vspltw)
{
/* Only allow 5-bit unsigned literals. */
STRIP_NOPS (arg1);
@@ -15011,39 +14694,6 @@ altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
}
static rtx
-spe_expand_stv_builtin (enum insn_code icode, tree exp)
-{
- tree arg0 = CALL_EXPR_ARG (exp, 0);
- tree arg1 = CALL_EXPR_ARG (exp, 1);
- tree arg2 = CALL_EXPR_ARG (exp, 2);
- rtx op0 = expand_normal (arg0);
- rtx op1 = expand_normal (arg1);
- rtx op2 = expand_normal (arg2);
- rtx pat;
- machine_mode mode0 = insn_data[icode].operand[0].mode;
- machine_mode mode1 = insn_data[icode].operand[1].mode;
- machine_mode mode2 = insn_data[icode].operand[2].mode;
-
- /* Invalid arguments. Bail before doing anything stoopid! */
- if (arg0 == error_mark_node
- || arg1 == error_mark_node
- || arg2 == error_mark_node)
- return const0_rtx;
-
- if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
- op0 = copy_to_mode_reg (mode2, op0);
- if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
- op1 = copy_to_mode_reg (mode0, op1);
- if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
- op2 = copy_to_mode_reg (mode1, op2);
-
- pat = GEN_FCN (icode) (op1, op2, op0);
- if (pat)
- emit_insn (pat);
- return NULL_RTX;
-}
-
-static rtx
paired_expand_stv_builtin (enum insn_code icode, tree exp)
{
tree arg0 = CALL_EXPR_ARG (exp, 0);
@@ -16459,171 +16109,6 @@ paired_expand_builtin (tree exp, rtx target, bool * expandedp)
return NULL_RTX;
}
-/* Binops that need to be initialized manually, but can be expanded
- automagically by rs6000_expand_binop_builtin. */
-static const struct builtin_description bdesc_2arg_spe[] =
-{
- { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
- { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
- { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
- { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
- { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
- { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
- { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
-};
-
-/* Expand the builtin in EXP and store the result in TARGET. Store
- true in *EXPANDEDP if we found a builtin to expand.
-
- This expands the SPE builtins that are not simple unary and binary
- operations. */
-static rtx
-spe_expand_builtin (tree exp, rtx target, bool *expandedp)
-{
- tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
- tree arg1, arg0;
- enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
- enum insn_code icode;
- machine_mode tmode, mode0;
- rtx pat, op0;
- const struct builtin_description *d;
- size_t i;
-
- *expandedp = true;
-
- /* Syntax check for a 5-bit unsigned immediate. */
- switch (fcode)
- {
- case SPE_BUILTIN_EVSTDD:
- case SPE_BUILTIN_EVSTDH:
- case SPE_BUILTIN_EVSTDW:
- case SPE_BUILTIN_EVSTWHE:
- case SPE_BUILTIN_EVSTWHO:
- case SPE_BUILTIN_EVSTWWE:
- case SPE_BUILTIN_EVSTWWO:
- arg1 = CALL_EXPR_ARG (exp, 2);
- if (TREE_CODE (arg1) != INTEGER_CST
- || TREE_INT_CST_LOW (arg1) & ~0x1f)
- {
- error ("argument 2 must be a 5-bit unsigned literal");
- return const0_rtx;
- }
- break;
- default:
- break;
- }
-
- /* The evsplat*i instructions are not quite generic. */
- switch (fcode)
- {
- case SPE_BUILTIN_EVSPLATFI:
- return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
- exp, target);
- case SPE_BUILTIN_EVSPLATI:
- return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
- exp, target);
- default:
- break;
- }
-
- d = bdesc_2arg_spe;
- for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
- if (d->code == fcode)
- return rs6000_expand_binop_builtin (d->icode, exp, target);
-
- d = bdesc_spe_predicates;
- for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
- if (d->code == fcode)
- return spe_expand_predicate_builtin (d->icode, exp, target);
-
- d = bdesc_spe_evsel;
- for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
- if (d->code == fcode)
- return spe_expand_evsel_builtin (d->icode, exp, target);
-
- switch (fcode)
- {
- case SPE_BUILTIN_EVSTDDX:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
- case SPE_BUILTIN_EVSTDHX:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
- case SPE_BUILTIN_EVSTDWX:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
- case SPE_BUILTIN_EVSTWHEX:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
- case SPE_BUILTIN_EVSTWHOX:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
- case SPE_BUILTIN_EVSTWWEX:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
- case SPE_BUILTIN_EVSTWWOX:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
- case SPE_BUILTIN_EVSTDD:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
- case SPE_BUILTIN_EVSTDH:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
- case SPE_BUILTIN_EVSTDW:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
- case SPE_BUILTIN_EVSTWHE:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
- case SPE_BUILTIN_EVSTWHO:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
- case SPE_BUILTIN_EVSTWWE:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
- case SPE_BUILTIN_EVSTWWO:
- return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
- case SPE_BUILTIN_MFSPEFSCR:
- icode = CODE_FOR_spe_mfspefscr;
- tmode = insn_data[icode].operand[0].mode;
-
- if (target == 0
- || GET_MODE (target) != tmode
- || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
- target = gen_reg_rtx (tmode);
-
- pat = GEN_FCN (icode) (target);
- if (! pat)
- return 0;
- emit_insn (pat);
- return target;
- case SPE_BUILTIN_MTSPEFSCR:
- icode = CODE_FOR_spe_mtspefscr;
- arg0 = CALL_EXPR_ARG (exp, 0);
- op0 = expand_normal (arg0);
- mode0 = insn_data[icode].operand[0].mode;
-
- if (arg0 == error_mark_node)
- return const0_rtx;
-
- if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
- op0 = copy_to_mode_reg (mode0, op0);
-
- pat = GEN_FCN (icode) (op0);
- if (pat)
- emit_insn (pat);
- return NULL_RTX;
- default:
- break;
- }
-
- *expandedp = false;
- return NULL_RTX;
-}
-
static rtx
paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
{
@@ -16696,164 +16181,6 @@ paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
return target;
}
-static rtx
-spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
-{
- rtx pat, scratch, tmp;
- tree form = CALL_EXPR_ARG (exp, 0);
- tree arg0 = CALL_EXPR_ARG (exp, 1);
- tree arg1 = CALL_EXPR_ARG (exp, 2);
- rtx op0 = expand_normal (arg0);
- rtx op1 = expand_normal (arg1);
- machine_mode mode0 = insn_data[icode].operand[1].mode;
- machine_mode mode1 = insn_data[icode].operand[2].mode;
- int form_int;
- enum rtx_code code;
-
- if (TREE_CODE (form) != INTEGER_CST)
- {
- error ("argument 1 of __builtin_spe_predicate must be a constant");
- return const0_rtx;
- }
- else
- form_int = TREE_INT_CST_LOW (form);
-
- gcc_assert (mode0 == mode1);
-
- if (arg0 == error_mark_node || arg1 == error_mark_node)
- return const0_rtx;
-
- if (target == 0
- || GET_MODE (target) != SImode
- || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
- target = gen_reg_rtx (SImode);
-
- if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
- op0 = copy_to_mode_reg (mode0, op0);
- if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
- op1 = copy_to_mode_reg (mode1, op1);
-
- scratch = gen_reg_rtx (CCmode);
-
- pat = GEN_FCN (icode) (scratch, op0, op1);
- if (! pat)
- return const0_rtx;
- emit_insn (pat);
-
- /* There are 4 variants for each predicate: _any_, _all_, _upper_,
- _lower_. We use one compare, but look in different bits of the
- CR for each variant.
-
- There are 2 elements in each SPE simd type (upper/lower). The CR
- bits are set as follows:
-
- BIT0 | BIT 1 | BIT 2 | BIT 3
- U | L | (U | L) | (U & L)
-
- So, for an "all" relationship, BIT 3 would be set.
- For an "any" relationship, BIT 2 would be set. Etc.
-
- Following traditional nomenclature, these bits map to:
-
- BIT0 | BIT 1 | BIT 2 | BIT 3
- LT | GT | EQ | OV
-
- Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
- */
-
- switch (form_int)
- {
- /* All variant. OV bit. */
- case 0:
- /* We need to get to the OV bit, which is the ORDERED bit. We
- could generate (ordered:SI (reg:CC xx) (const_int 0)), but
- that's ugly and will make validate_condition_mode die.
- So let's just use another pattern. */
- emit_insn (gen_move_from_CR_ov_bit (target, scratch));
- return target;
- /* Any variant. EQ bit. */
- case 1:
- code = EQ;
- break;
- /* Upper variant. LT bit. */
- case 2:
- code = LT;
- break;
- /* Lower variant. GT bit. */
- case 3:
- code = GT;
- break;
- default:
- error ("argument 1 of __builtin_spe_predicate is out of range");
- return const0_rtx;
- }
-
- tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
- emit_move_insn (target, tmp);
-
- return target;
-}
-
-/* The evsel builtins look like this:
-
- e = __builtin_spe_evsel_OP (a, b, c, d);
-
- and work like this:
-
- e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
- e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
-*/
-
-static rtx
-spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
-{
- rtx pat, scratch;
- tree arg0 = CALL_EXPR_ARG (exp, 0);
- tree arg1 = CALL_EXPR_ARG (exp, 1);
- tree arg2 = CALL_EXPR_ARG (exp, 2);
- tree arg3 = CALL_EXPR_ARG (exp, 3);
- rtx op0 = expand_normal (arg0);
- rtx op1 = expand_normal (arg1);
- rtx op2 = expand_normal (arg2);
- rtx op3 = expand_normal (arg3);
- machine_mode mode0 = insn_data[icode].operand[1].mode;
- machine_mode mode1 = insn_data[icode].operand[2].mode;
-
- gcc_assert (mode0 == mode1);
-
- if (arg0 == error_mark_node || arg1 == error_mark_node
- || arg2 == error_mark_node || arg3 == error_mark_node)
- return const0_rtx;
-
- if (target == 0
- || GET_MODE (target) != mode0
- || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
- target = gen_reg_rtx (mode0);
-
- if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
- op0 = copy_to_mode_reg (mode0, op0);
- if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
- op1 = copy_to_mode_reg (mode0, op1);
- if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
- op2 = copy_to_mode_reg (mode0, op2);
- if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
- op3 = copy_to_mode_reg (mode0, op3);
-
- /* Generate the compare. */
- scratch = gen_reg_rtx (CCmode);
- pat = GEN_FCN (icode) (scratch, op0, op1);
- if (! pat)
- return const0_rtx;
- emit_insn (pat);
-
- if (mode0 == V2SImode)
- emit_insn (gen_spe_evsel (target, op2, op3, scratch));
- else
- emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
-
- return target;
-}
-
/* Raise an error message for a builtin function that is called without the
appropriate target options being set. */
@@ -16875,8 +16202,6 @@ rs6000_invalid_builtin (enum rs6000_builtins fncode)
error ("Builtin function %s requires the -maltivec option", name);
else if ((fnmask & RS6000_BTM_PAIRED) != 0)
error ("Builtin function %s requires the -mpaired option", name);
- else if ((fnmask & RS6000_BTM_SPE) != 0)
- error ("Builtin function %s requires the -mspe option", name);
else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
== (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
error ("Builtin function %s requires the -mhard-dfp and"
@@ -17344,13 +16669,6 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
if (success)
return ret;
}
- if (TARGET_SPE)
- {
- ret = spe_expand_builtin (exp, target, &success);
-
- if (success)
- return ret;
- }
if (TARGET_PAIRED_FLOAT)
{
ret = paired_expand_builtin (exp, target, &success);
@@ -17424,9 +16742,8 @@ rs6000_init_builtins (void)
machine_mode mode;
if (TARGET_DEBUG_BUILTIN)
- fprintf (stderr, "rs6000_init_builtins%s%s%s%s\n",
+ fprintf (stderr, "rs6000_init_builtins%s%s%s\n",
(TARGET_PAIRED_FLOAT) ? ", paired" : "",
- (TARGET_SPE) ? ", spe" : "",
(TARGET_ALTIVEC) ? ", altivec" : "",
(TARGET_VSX) ? ", vsx" : "");
@@ -17625,14 +16942,12 @@ rs6000_init_builtins (void)
use of the target attribute. */
if (TARGET_PAIRED_FLOAT)
paired_init_builtins ();
- if (TARGET_SPE)
- spe_init_builtins ();
if (TARGET_EXTRA_BUILTINS)
altivec_init_builtins ();
if (TARGET_HTM)
htm_init_builtins ();
- if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
+ if (TARGET_EXTRA_BUILTINS || TARGET_PAIRED_FLOAT)
rs6000_common_init_builtins ();
ftype = build_function_type_list (ieee128_float_type_node,
@@ -17724,214 +17039,6 @@ rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
}
static void
-spe_init_builtins (void)
-{
- tree puint_type_node = build_pointer_type (unsigned_type_node);
- tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
- const struct builtin_description *d;
- size_t i;
- HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
-
- tree v2si_ftype_4_v2si
- = build_function_type_list (opaque_V2SI_type_node,
- opaque_V2SI_type_node,
- opaque_V2SI_type_node,
- opaque_V2SI_type_node,
- opaque_V2SI_type_node,
- NULL_TREE);
-
- tree v2sf_ftype_4_v2sf
- = build_function_type_list (opaque_V2SF_type_node,
- opaque_V2SF_type_node,
- opaque_V2SF_type_node,
- opaque_V2SF_type_node,
- opaque_V2SF_type_node,
- NULL_TREE);
-
- tree int_ftype_int_v2si_v2si
- = build_function_type_list (integer_type_node,
- integer_type_node,
- opaque_V2SI_type_node,
- opaque_V2SI_type_node,
- NULL_TREE);
-
- tree int_ftype_int_v2sf_v2sf
- = build_function_type_list (integer_type_node,
- integer_type_node,
- opaque_V2SF_type_node,
- opaque_V2SF_type_node,
- NULL_TREE);
-
- tree void_ftype_v2si_puint_int
- = build_function_type_list (void_type_node,
- opaque_V2SI_type_node,
- puint_type_node,
- integer_type_node,
- NULL_TREE);
-
- tree void_ftype_v2si_puint_char
- = build_function_type_list (void_type_node,
- opaque_V2SI_type_node,
- puint_type_node,
- char_type_node,
- NULL_TREE);
-
- tree void_ftype_v2si_pv2si_int
- = build_function_type_list (void_type_node,
- opaque_V2SI_type_node,
- opaque_p_V2SI_type_node,
- integer_type_node,
- NULL_TREE);
-
- tree void_ftype_v2si_pv2si_char
- = build_function_type_list (void_type_node,
- opaque_V2SI_type_node,
- opaque_p_V2SI_type_node,
- char_type_node,
- NULL_TREE);
-
- tree void_ftype_int
- = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
-
- tree int_ftype_void
- = build_function_type_list (integer_type_node, NULL_TREE);
-
- tree v2si_ftype_pv2si_int
- = build_function_type_list (opaque_V2SI_type_node,
- opaque_p_V2SI_type_node,
- integer_type_node,
- NULL_TREE);
-
- tree v2si_ftype_puint_int
- = build_function_type_list (opaque_V2SI_type_node,
- puint_type_node,
- integer_type_node,
- NULL_TREE);
-
- tree v2si_ftype_pushort_int
- = build_function_type_list (opaque_V2SI_type_node,
- pushort_type_node,
- integer_type_node,
- NULL_TREE);
-
- tree v2si_ftype_signed_char
- = build_function_type_list (opaque_V2SI_type_node,
- signed_char_type_node,
- NULL_TREE);
-
- add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node);
-
- /* Initialize irregular SPE builtins. */
-
- def_builtin ("__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
- def_builtin ("__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
- def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
- def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
- def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
- def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
- def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
- def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
- def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
- def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
- def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
- def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
- def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
- def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
- def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
- def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
- def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
- def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
-
- /* Loads. */
- def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
- def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
- def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
- def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
- def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
- def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
- def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
- def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
- def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
- def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
- def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
- def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
- def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
- def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
- def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
- def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
- def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
- def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
- def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
- def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
- def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
- def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
-
- /* Predicates. */
- d = bdesc_spe_predicates;
- for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
- {
- tree type;
- HOST_WIDE_INT mask = d->mask;
-
- if ((mask & builtin_mask) != mask)
- {
- if (TARGET_DEBUG_BUILTIN)
- fprintf (stderr, "spe_init_builtins, skip predicate %s\n",
- d->name);
- continue;
- }
-
- /* Cannot define builtin if the instruction is disabled. */
- gcc_assert (d->icode != CODE_FOR_nothing);
- switch (insn_data[d->icode].operand[1].mode)
- {
- case V2SImode:
- type = int_ftype_int_v2si_v2si;
- break;
- case V2SFmode:
- type = int_ftype_int_v2sf_v2sf;
- break;
- default:
- gcc_unreachable ();
- }
-
- def_builtin (d->name, type, d->code);
- }
-
- /* Evsel predicates. */
- d = bdesc_spe_evsel;
- for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
- {
- tree type;
- HOST_WIDE_INT mask = d->mask;
-
- if ((mask & builtin_mask) != mask)
- {
- if (TARGET_DEBUG_BUILTIN)
- fprintf (stderr, "spe_init_builtins, skip evsel %s\n",
- d->name);
- continue;
- }
-
- /* Cannot define builtin if the instruction is disabled. */
- gcc_assert (d->icode != CODE_FOR_nothing);
- switch (insn_data[d->icode].operand[1].mode)
- {
- case V2SImode:
- type = v2si_ftype_4_v2si;
- break;
- case V2SFmode:
- type = v2sf_ftype_4_v2sf;
- break;
- default:
- gcc_unreachable ();
- }
-
- def_builtin (d->name, type, d->code);
- }
-}
-
-static void
paired_init_builtins (void)
{
const struct builtin_description *d;
@@ -19440,8 +18547,6 @@ expand_block_clear (rtx operands[])
clear_step = 16;
else if (TARGET_POWERPC64 && (align >= 64 || !STRICT_ALIGNMENT))
clear_step = 8;
- else if (TARGET_SPE && align >= 64)
- clear_step = 8;
else
clear_step = 4;
@@ -19460,11 +18565,6 @@ expand_block_clear (rtx operands[])
clear_bytes = 16;
mode = V4SImode;
}
- else if (bytes >= 8 && TARGET_SPE && align >= 64)
- {
- clear_bytes = 8;
- mode = V2SImode;
- }
else if (bytes >= 8 && TARGET_POWERPC64
&& (align >= 64 || !STRICT_ALIGNMENT))
{
@@ -20672,12 +19772,6 @@ expand_block_move (rtx operands[])
mode = V4SImode;
gen_func.mov = gen_movv4si;
}
- else if (TARGET_SPE && bytes >= 8 && align >= 64)
- {
- move_bytes = 8;
- mode = V2SImode;
- gen_func.mov = gen_movv2si;
- }
else if (TARGET_STRING
&& bytes > 24 /* move up to 32 bytes at a time */
&& ! fixed_regs[5]
@@ -23105,10 +22199,6 @@ rs6000_cannot_change_mode_class (machine_mode from,
&& (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
return true;
- if (TARGET_SPE && (SPE_VECTOR_MODE (from) + SPE_VECTOR_MODE (to)) == 1
- && reg_classes_intersect_p (GENERAL_REGS, rclass))
- return true;
-
return false;
}
@@ -23944,34 +23034,6 @@ print_operand (FILE *file, rtx x, int code)
tmp = XEXP (x, 0);
- /* Ugly hack because %y is overloaded. */
- if (TARGET_SPE
- && (GET_MODE_SIZE (GET_MODE (x)) == 8
- || FLOAT128_2REG_P (GET_MODE (x))
- || GET_MODE (x) == TImode
- || GET_MODE (x) == PTImode))
- {
- /* Handle [reg]. */
- if (REG_P (tmp))
- {
- fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
- break;
- }
- /* Handle [reg+UIMM]. */
- else if (GET_CODE (tmp) == PLUS &&
- GET_CODE (XEXP (tmp, 1)) == CONST_INT)
- {
- int x;
-
- gcc_assert (REG_P (XEXP (tmp, 0)));
-
- x = INTVAL (XEXP (tmp, 1));
- fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
- break;
- }
-
- /* Fall through. Must be [reg+reg]. */
- }
if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
&& GET_CODE (tmp) == AND
&& GET_CODE (XEXP (tmp, 1)) == CONST_INT
@@ -26804,13 +25866,6 @@ rs6000_savres_strategy (rs6000_stack_t *info,
| SAVE_INLINE_GPRS
| SAVE_INLINE_VRS);
- /* Saving CR interferes with the exit routines used on the SPE, so
- just punt here. */
- if (TARGET_SPE_ABI
- && info->spe_64bit_regs_used
- && info->cr_save_p)
- strategy |= REST_INLINE_GPRS;
-
/* We can only use the out-of-line routines to restore fprs if we've
saved all the registers from first_fp_reg_save in the prologue.
Otherwise, we risk loading garbage. Of course, if we have saved
@@ -26853,7 +25908,6 @@ rs6000_savres_strategy (rs6000_stack_t *info,
if (TARGET_MULTIPLE
&& !TARGET_POWERPC64
- && !(TARGET_SPE_ABI && info->spe_64bit_regs_used)
&& info->first_gp_reg_save < 31
&& !(flag_shrink_wrap
&& flag_shrink_wrap_separate
@@ -27072,15 +26126,6 @@ rs6000_stack_info (void)
memset (info, 0, sizeof (*info));
info->reload_completed = reload_completed;
- if (TARGET_SPE)
- {
- /* Cache value so we don't rescan instruction chain over and over. */
- if (cfun->machine->spe_insn_chain_scanned_p == 0)
- cfun->machine->spe_insn_chain_scanned_p
- = spe_func_has_64bit_regs_p () + 1;
- info->spe_64bit_regs_used = cfun->machine->spe_insn_chain_scanned_p - 1;
- }
-
/* Select which calling sequence. */
info->abi = DEFAULT_ABI;
@@ -27101,21 +26146,6 @@ rs6000_stack_info (void)
info->gp_size = reg_size * (32 - first_gp);
- /* For the SPE, we have an additional upper 32-bits on each GPR.
- Ideally we should save the entire 64-bits only when the upper
- half is used in SIMD instructions. Since we only record
- registers live (not the size they are used in), this proves
- difficult because we'd have to traverse the instruction chain at
- the right time, taking reload into account. This is a real pain,
- so we opt to save the GPRs in 64-bits always if but one register
- gets used in 64-bits. Otherwise, all the registers in the frame
- get saved in 32-bits.
-
- So... since when we save all GPRs (except the SP) in 64-bits, the
- traditional GP save area will be empty. */
- if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
- info->gp_size = 0;
-
info->first_fp_reg_save = first_fp_reg_to_save ();
info->fp_size = 8 * (64 - info->first_fp_reg_save);
@@ -27145,9 +26175,7 @@ rs6000_stack_info (void)
for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
continue;
- /* SPE saves EH registers in 64-bits. */
- ehrd_size = i * (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0
- ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
+ ehrd_size = i * UNITS_PER_WORD;
}
else
ehrd_size = 0;
@@ -27181,9 +26209,6 @@ rs6000_stack_info (void)
ABI_STACK_BOUNDARY / BITS_PER_UNIT)
- (info->fixed_size + info->vars_size + info->parm_size);
- if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
- info->spe_gp_size = 8 * (32 - first_gp);
-
if (TARGET_ALTIVEC_ABI)
info->vrsave_mask = compute_vrsave_mask ();
@@ -27236,23 +26261,7 @@ rs6000_stack_info (void)
info->gp_save_offset = info->fp_save_offset - info->gp_size;
info->cr_save_offset = info->gp_save_offset - info->cr_size;
- if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
- {
- /* Align stack so SPE GPR save area is aligned on a
- double-word boundary. */
- if (info->spe_gp_size != 0 && info->cr_save_offset != 0)
- info->spe_padding_size = 8 - (-info->cr_save_offset % 8);
- else
- info->spe_padding_size = 0;
-
- info->spe_gp_save_offset = info->cr_save_offset
- - info->spe_padding_size
- - info->spe_gp_size;
-
- /* Adjust for SPE case. */
- info->ehrd_offset = info->spe_gp_save_offset;
- }
- else if (TARGET_ALTIVEC_ABI)
+ if (TARGET_ALTIVEC_ABI)
{
info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
@@ -27279,8 +26288,6 @@ rs6000_stack_info (void)
+ info->gp_size
+ info->altivec_size
+ info->altivec_padding_size
- + info->spe_gp_size
- + info->spe_padding_size
+ ehrd_size
+ ehcr_size
+ info->cr_size
@@ -27352,50 +26359,6 @@ rs6000_stack_info (void)
return info;
}
-/* Return true if the current function uses any GPRs in 64-bit SIMD
- mode. */
-
-static bool
-spe_func_has_64bit_regs_p (void)
-{
- rtx_insn *insns, *insn;
-
- /* Functions that save and restore all the call-saved registers will
- need to save/restore the registers in 64-bits. */
- if (crtl->calls_eh_return
- || cfun->calls_setjmp
- || crtl->has_nonlocal_goto)
- return true;
-
- insns = get_insns ();
-
- for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
- {
- if (INSN_P (insn))
- {
- rtx i;
-
- /* FIXME: This should be implemented with attributes...
-
- (set_attr "spe64" "true")....then,
- if (get_spe64(insn)) return true;
-
- It's the only reliable way to do the stuff below. */
-
- i = PATTERN (insn);
- if (GET_CODE (i) == SET)
- {
- machine_mode mode = GET_MODE (SET_SRC (i));
-
- if (SPE_VECTOR_MODE (mode))
- return true;
- }
- }
- }
-
- return false;
-}
-
static void
debug_stack_info (rs6000_stack_t *info)
{
@@ -27424,9 +26387,6 @@ debug_stack_info (rs6000_stack_t *info)
if (TARGET_ALTIVEC_ABI)
fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
- if (TARGET_SPE_ABI)
- fprintf (stderr, "\tSPE ABI extensions enabled.\n");
-
if (info->first_gp_reg_save != 32)
fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
@@ -27462,10 +26422,6 @@ debug_stack_info (rs6000_stack_t *info)
fprintf (stderr, "\taltivec_save_offset = %5d\n",
info->altivec_save_offset);
- if (info->spe_gp_size)
- fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
- info->spe_gp_save_offset);
-
if (info->vrsave_size)
fprintf (stderr, "\tvrsave_save_offset = %5d\n",
info->vrsave_save_offset);
@@ -27496,9 +26452,6 @@ debug_stack_info (rs6000_stack_t *info)
if (info->gp_size)
fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
- if (info->spe_gp_size)
- fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
-
if (info->fp_size)
fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
@@ -27512,10 +26465,6 @@ debug_stack_info (rs6000_stack_t *info)
fprintf (stderr, "\taltivec_padding_size= %5d\n",
info->altivec_padding_size);
- if (info->spe_padding_size)
- fprintf (stderr, "\tspe_padding_size = %5d\n",
- info->spe_padding_size);
-
if (info->cr_size)
fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
@@ -28335,11 +27284,8 @@ emit_frame_save (rtx frame_reg, machine_mode mode,
rtx reg;
/* Some cases that need register indexed addressing. */
- gcc_checking_assert (!((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
- || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
- || (TARGET_SPE_ABI
- && SPE_VECTOR_MODE (mode)
- && !SPE_CONST_OFFSET_OK (offset))));
+ gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
+ || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
reg = gen_rtx_REG (mode, regno);
rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
@@ -28353,19 +27299,7 @@ emit_frame_save (rtx frame_reg, machine_mode mode,
static rtx
gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
{
- rtx int_rtx, offset_rtx;
-
- int_rtx = GEN_INT (offset);
-
- if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode) && !SPE_CONST_OFFSET_OK (offset))
- {
- offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
- emit_move_insn (offset_rtx, int_rtx);
- }
- else
- offset_rtx = int_rtx;
-
- return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
+ return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
}
#ifndef TARGET_FIX_AND_CONTINUE
@@ -28396,7 +27330,7 @@ static char savres_routine_name[30];
We are saving/restoring GPRs if GPR is true. */
static char *
-rs6000_savres_routine_name (rs6000_stack_t *info, int regno, int sel)
+rs6000_savres_routine_name (int regno, int sel)
{
const char *prefix = "";
const char *suffix = "";
@@ -28412,9 +27346,6 @@ rs6000_savres_routine_name (rs6000_stack_t *info, int regno, int sel)
- ELF targets have save/restore routines for GPRs.
- - SPE targets use different prefixes for 32/64-bit registers, and
- neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
-
- PPC64 ELF targets have routines for save/restore of GPRs that
differ in what they do with the link register, so having a set
prefix doesn't work. (We only use one of the save routines at
@@ -28429,20 +27360,7 @@ rs6000_savres_routine_name (rs6000_stack_t *info, int regno, int sel)
We deal with all this by synthesizing our own prefix/suffix and
using that for the simple sprintf call shown above. */
- if (TARGET_SPE)
- {
- /* No floating point saves on the SPE. */
- gcc_assert ((sel & SAVRES_REG) == SAVRES_GPR);
-
- if ((sel & SAVRES_SAVE))
- prefix = info->spe_64bit_regs_used ? "_save64gpr_" : "_save32gpr_";
- else
- prefix = info->spe_64bit_regs_used ? "_rest64gpr_" : "_rest32gpr_";
-
- if ((sel & SAVRES_LR))
- suffix = "_x";
- }
- else if (DEFAULT_ABI == ABI_V4)
+ if (DEFAULT_ABI == ABI_V4)
{
if (TARGET_64BIT)
goto aix_names;
@@ -28532,12 +27450,6 @@ rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
rtx sym;
int select = sel;
- /* On the SPE, we never have any FPRs, but we do have 32/64-bit
- versions of the gpr routines. */
- if (TARGET_SPE_ABI && (sel & SAVRES_REG) == SAVRES_GPR
- && info->spe_64bit_regs_used)
- select ^= SAVRES_FPR ^ SAVRES_GPR;
-
/* Don't generate bogus routine names. */
gcc_assert (FIRST_SAVRES_REGISTER <= regno
&& regno <= LAST_SAVRES_REGISTER
@@ -28549,7 +27461,7 @@ rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
{
char *name;
- name = rs6000_savres_routine_name (info, regno, sel);
+ name = rs6000_savres_routine_name (regno, sel);
sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
= gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
@@ -28565,8 +27477,7 @@ rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
reg UPDT_REGNO for use by out-of-line register restore routines. */
static rtx
-rs6000_emit_stack_reset (rs6000_stack_t *info,
- rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
+rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
unsigned updt_regno)
{
/* If there is nothing to do, don't do anything. */
@@ -28577,10 +27488,7 @@ rs6000_emit_stack_reset (rs6000_stack_t *info,
/* This blockage is needed so that sched doesn't decide to move
the sp change before the register restores. */
- if (DEFAULT_ABI == ABI_V4
- || (TARGET_SPE_ABI
- && info->spe_64bit_regs_used != 0
- && info->first_gp_reg_save != 32))
+ if (DEFAULT_ABI == ABI_V4)
return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
GEN_INT (frame_off)));
@@ -28802,9 +27710,6 @@ rs6000_get_separate_components (void)
if (WORLD_SAVE_P (info))
return NULL;
- if (TARGET_SPE_ABI)
- return NULL;
-
gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
&& !(info->savres_strategy & REST_MULTIPLE));
@@ -29200,12 +28105,6 @@ rs6000_emit_prologue (void)
emit_insn (gen_nop ());
}
- if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
- {
- reg_mode = V2SImode;
- reg_size = 8;
- }
-
/* Handle world saves specially here. */
if (WORLD_SAVE_P (info))
{
@@ -29306,12 +28205,9 @@ rs6000_emit_prologue (void)
&& (DEFAULT_ABI == ABI_V4
|| crtl->calls_eh_return))
{
- bool need_r11 = (TARGET_SPE
- ? (!(strategy & SAVE_INLINE_GPRS)
- && info->spe_64bit_regs_used == 0)
- : (!(strategy & SAVE_INLINE_FPRS)
- || !(strategy & SAVE_INLINE_GPRS)
- || !(strategy & SAVE_INLINE_VRS)));
+ bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
+ || !(strategy & SAVE_INLINE_GPRS)
+ || !(strategy & SAVE_INLINE_VRS));
int ptr_regno = -1;
rtx ptr_reg = NULL_RTX;
int ptr_off = 0;
@@ -29448,94 +28344,7 @@ rs6000_emit_prologue (void)
/* Save GPRs. This is done as a PARALLEL if we are using
the store-multiple instructions. */
- if (!WORLD_SAVE_P (info)
- && TARGET_SPE_ABI
- && info->spe_64bit_regs_used != 0
- && info->first_gp_reg_save != 32)
- {
- int i;
- rtx spe_save_area_ptr;
- HOST_WIDE_INT save_off;
- int ool_adjust = 0;
-
- /* Determine whether we can address all of the registers that need
- to be saved with an offset from frame_reg_rtx that fits in
- the small const field for SPE memory instructions. */
- int spe_regs_addressable
- = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off
- + reg_size * (32 - info->first_gp_reg_save - 1))
- && (strategy & SAVE_INLINE_GPRS));
-
- if (spe_regs_addressable)
- {
- spe_save_area_ptr = frame_reg_rtx;
- save_off = frame_off;
- }
- else
- {
- /* Make r11 point to the start of the SPE save area. We need
- to be careful here if r11 is holding the static chain. If
- it is, then temporarily save it in r0. */
- HOST_WIDE_INT offset;
-
- if (!(strategy & SAVE_INLINE_GPRS))
- ool_adjust = 8 * (info->first_gp_reg_save - FIRST_SAVED_GP_REGNO);
- offset = info->spe_gp_save_offset + frame_off - ool_adjust;
- spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
- save_off = frame_off - offset;
-
- if (using_static_chain_p)
- {
- rtx r0 = gen_rtx_REG (Pmode, 0);
-
- START_USE (0);
- gcc_assert (info->first_gp_reg_save > 11);
-
- emit_move_insn (r0, spe_save_area_ptr);
- }
- else if (REGNO (frame_reg_rtx) != 11)
- START_USE (11);
-
- emit_insn (gen_addsi3 (spe_save_area_ptr,
- frame_reg_rtx, GEN_INT (offset)));
- if (!using_static_chain_p && REGNO (frame_reg_rtx) == 11)
- frame_off = -info->spe_gp_save_offset + ool_adjust;
- }
-
- if ((strategy & SAVE_INLINE_GPRS))
- {
- for (i = 0; i < 32 - info->first_gp_reg_save; i++)
- if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
- emit_frame_save (spe_save_area_ptr, reg_mode,
- info->first_gp_reg_save + i,
- (info->spe_gp_save_offset + save_off
- + reg_size * i),
- sp_off - save_off);
- }
- else
- {
- insn = rs6000_emit_savres_rtx (info, spe_save_area_ptr,
- info->spe_gp_save_offset + save_off,
- 0, reg_mode,
- SAVRES_SAVE | SAVRES_GPR);
-
- rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off,
- NULL_RTX, NULL_RTX);
- }
-
- /* Move the static chain pointer back. */
- if (!spe_regs_addressable)
- {
- if (using_static_chain_p)
- {
- emit_move_insn (spe_save_area_ptr, gen_rtx_REG (Pmode, 0));
- END_USE (0);
- }
- else if (REGNO (frame_reg_rtx) != 11)
- END_USE (11);
- }
- }
- else if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
+ if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
{
bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
@@ -30162,7 +28971,7 @@ rs6000_output_savres_externs (FILE *file)
{
bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
- name = rs6000_savres_routine_name (info, regno, sel);
+ name = rs6000_savres_routine_name (regno, sel);
fprintf (file, "\t.extern %s\n", name);
}
if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
@@ -30170,7 +28979,7 @@ rs6000_output_savres_externs (FILE *file)
bool lr = (info->savres_strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
- name = rs6000_savres_routine_name (info, regno, sel);
+ name = rs6000_savres_routine_name (regno, sel);
fprintf (file, "\t.extern %s\n", name);
}
}
@@ -30501,12 +29310,6 @@ rs6000_emit_epilogue (int sibcall)
info = rs6000_stack_info ();
- if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
- {
- reg_mode = V2SImode;
- reg_size = 8;
- }
-
strategy = info->savres_strategy;
using_load_multiple = strategy & REST_MULTIPLE;
restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
@@ -31061,68 +29864,7 @@ rs6000_emit_epilogue (int sibcall)
/* Restore GPRs. This is done as a PARALLEL if we are using
the load-multiple instructions. */
- if (TARGET_SPE_ABI
- && info->spe_64bit_regs_used
- && info->first_gp_reg_save != 32)
- {
- /* Determine whether we can address all of the registers that need
- to be saved with an offset from frame_reg_rtx that fits in
- the small const field for SPE memory instructions. */
- int spe_regs_addressable
- = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off
- + reg_size * (32 - info->first_gp_reg_save - 1))
- && restoring_GPRs_inline);
-
- if (!spe_regs_addressable)
- {
- int ool_adjust = 0;
- rtx old_frame_reg_rtx = frame_reg_rtx;
- /* Make r11 point to the start of the SPE save area. We worried about
- not clobbering it when we were saving registers in the prologue.
- There's no need to worry here because the static chain is passed
- anew to every function. */
-
- if (!restoring_GPRs_inline)
- ool_adjust = 8 * (info->first_gp_reg_save - FIRST_SAVED_GP_REGNO);
- frame_reg_rtx = gen_rtx_REG (Pmode, 11);
- emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
- GEN_INT (info->spe_gp_save_offset
- + frame_off
- - ool_adjust)));
- /* Keep the invariant that frame_reg_rtx + frame_off points
- at the top of the stack frame. */
- frame_off = -info->spe_gp_save_offset + ool_adjust;
- }
-
- if (restoring_GPRs_inline)
- {
- HOST_WIDE_INT spe_offset = info->spe_gp_save_offset + frame_off;
-
- for (i = 0; i < 32 - info->first_gp_reg_save; i++)
- if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
- {
- rtx offset, addr, mem, reg;
-
- /* We're doing all this to ensure that the immediate offset
- fits into the immediate field of 'evldd'. */
- gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
-
- offset = GEN_INT (spe_offset + reg_size * i);
- addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
- mem = gen_rtx_MEM (V2SImode, addr);
- reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
-
- emit_move_insn (reg, mem);
- }
- }
- else
- rs6000_emit_savres_rtx (info, frame_reg_rtx,
- info->spe_gp_save_offset + frame_off,
- info->lr_save_offset + frame_off,
- reg_mode,
- SAVRES_GPR | SAVRES_LR);
- }
- else if (!restoring_GPRs_inline)
+ if (!restoring_GPRs_inline)
{
/* We are jumping to an out-of-line function. */
rtx ptr_reg;
@@ -31135,7 +29877,7 @@ rs6000_emit_epilogue (int sibcall)
ptr_regno = ptr_regno_for_savres (sel);
ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
if (can_use_exit)
- rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno);
+ rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
else if (end_save + frame_off != 0)
emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
GEN_INT (end_save + frame_off)));
@@ -31273,7 +30015,7 @@ rs6000_emit_epilogue (int sibcall)
ptr_regno = ptr_regno_for_savres (sel);
}
- insn = rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno);
+ insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
if (REGNO (frame_reg_rtx) == ptr_regno)
frame_off = 0;
@@ -36134,9 +34876,7 @@ rs6000_elf_file_end (void)
{
if (rs6000_passes_vector)
fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
- (TARGET_ALTIVEC_ABI ? 2
- : TARGET_SPE_ABI ? 3
- : 1));
+ (TARGET_ALTIVEC_ABI ? 2 : 1));
if (rs6000_returns_struct)
fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
aix_struct_return ? 2 : 1);
@@ -38225,8 +36965,7 @@ rs6000_vectorize_vec_perm_const_ok (machine_mode vmode,
return true;
/* Check for ps_merge* or evmerge* insns. */
- if ((TARGET_PAIRED_FLOAT && vmode == V2SFmode)
- || (TARGET_SPE && vmode == V2SImode))
+ if (TARGET_PAIRED_FLOAT && vmode == V2SFmode)
{
rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
@@ -38586,68 +37325,11 @@ rs6000_initial_elimination_offset (int from, int to)
return offset;
}
-static rtx
-rs6000_dwarf_register_span (rtx reg)
-{
- rtx parts[8];
- int i, words;
- unsigned regno = REGNO (reg);
- machine_mode mode = GET_MODE (reg);
-
- if (TARGET_SPE
- && regno < 32
- && SPE_VECTOR_MODE (GET_MODE (reg)))
- ;
- else
- return NULL_RTX;
-
- regno = REGNO (reg);
-
- /* The duality of the SPE register size wreaks all kinds of havoc.
- This is a way of distinguishing r0 in 32-bits from r0 in
- 64-bits. */
- words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
- gcc_assert (words <= 4);
- for (i = 0; i < words; i++, regno++)
- {
- if (BYTES_BIG_ENDIAN)
- {
- parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
- parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
- }
- else
- {
- parts[2 * i] = gen_rtx_REG (SImode, regno);
- parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
- }
- }
-
- return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
-}
-
/* Fill in sizes for SPE register high parts in table used by unwinder. */
static void
rs6000_init_dwarf_reg_sizes_extra (tree address)
{
- if (TARGET_SPE)
- {
- int i;
- machine_mode mode = TYPE_MODE (char_type_node);
- rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
- rtx mem = gen_rtx_MEM (BLKmode, addr);
- rtx value = gen_int_mode (4, mode);
-
- for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++)
- {
- int column = DWARF_REG_TO_UNWIND_COLUMN
- (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
- HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
-
- emit_move_insn (adjust_address (mem, mode, offset), value);
- }
- }
-
if (TARGET_MACHO && ! TARGET_ALTIVEC)
{
int i;
@@ -38679,11 +37361,6 @@ rs6000_init_dwarf_reg_sizes_extra (tree address)
unsigned int
rs6000_dbx_register_number (unsigned int regno, unsigned int format)
{
- /* We never use the GCC internal number for SPE high registers.
- Those are mapped to the 1200..1231 range for all debug formats. */
- if (SPE_HIGH_REGNO_P (regno))
- return regno - FIRST_SPE_HIGH_REGNO + 1200;
-
/* Except for the above, we use the internal number for non-DWARF
debug information, and also for .eh_frame. */
if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2)
@@ -38757,9 +37434,6 @@ rs6000_vector_mode_supported_p (machine_mode mode)
if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
return true;
- if (TARGET_SPE && SPE_VECTOR_MODE (mode))
- return true;
-
/* There is no vector form for IEEE 128-bit. If we return true for IEEE
128-bit, the compiler might try to widen IEEE 128-bit to IBM
double-double. */
@@ -38965,7 +37639,6 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
{
{ "altivec", RS6000_BTM_ALTIVEC, false, false },
{ "vsx", RS6000_BTM_VSX, false, false },
- { "spe", RS6000_BTM_SPE, false, false },
{ "paired", RS6000_BTM_PAIRED, false, false },
{ "fre", RS6000_BTM_FRE, false, false },
{ "fres", RS6000_BTM_FRES, false, false },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 66f8170..da3b877 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -569,8 +569,6 @@ extern int rs6000_vector_align[];
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
-#define TARGET_SPE_ABI 0
-#define TARGET_SPE 0
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
@@ -704,7 +702,7 @@ extern int rs6000_vector_align[];
the compiler for those builtins, and those machines don't support altivec or
VSX. */
-#define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \
+#define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \
&& ((TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POPCNTB /* ISA 2.02 */ \
@@ -869,7 +867,6 @@ extern unsigned char rs6000_recip_bits[];
#define UNITS_PER_FP_WORD 8
#define UNITS_PER_ALTIVEC_WORD 16
#define UNITS_PER_VSX_WORD 16
-#define UNITS_PER_SPE_WORD 8
#define UNITS_PER_PAIRED_WORD 8
/* Type used for ptrdiff_t, as a string used in a declaration. */
@@ -971,8 +968,7 @@ enum data_align { align_abi, align_opt, align_both };
#define DATA_ALIGNMENT(TYPE, ALIGN) \
rs6000_data_alignment (TYPE, ALIGN, align_opt)
-/* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
- 64 bits. */
+/* Align vectors to 128 bits. */
#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
rs6000_data_alignment (TYPE, ALIGN, align_abi)
@@ -983,9 +979,8 @@ enum data_align { align_abi, align_opt, align_both };
/* Define this macro to be the value 1 if unaligned accesses have a cost
many times greater than aligned accesses, for example if they are
emulated in a trap handler. */
-/* Altivec vector memory instructions simply ignore the low bits; SPE vector
- memory instructions trap on unaligned accesses; VSX memory instructions are
- aligned to 4 or 8 bytes. */
+/* Altivec vector memory instructions simply ignore the low bits; VSX memory
+ instructions are aligned to 4 or 8 bytes. */
#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
(STRICT_ALIGNMENT \
|| (!TARGET_EFFICIENT_UNALIGNED_VSX \
@@ -1027,12 +1022,7 @@ enum data_align { align_abi, align_opt, align_both };
/* This must be included for pre gcc 3.0 glibc compatibility. */
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
-/* True if register is an SPE High register. */
-#define SPE_HIGH_REGNO_P(N) \
- ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO)
-
-/* SPE high registers added as hard regs.
- The sfp register and 3 HTM registers
+/* The sfp register and 3 HTM registers
aren't included in DWARF_FRAME_REGISTERS. */
#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
@@ -1227,9 +1217,6 @@ enum data_align { align_abi, align_opt, align_both };
#define INT_REGNO_P(N) \
((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
-/* SPE SIMD registers are just the GPRs. */
-#define SPE_SIMD_REGNO_P(N) ((N) <= 31)
-
/* PAIRED SIMD registers are just the FPRs. */
#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
@@ -1305,12 +1292,6 @@ enum data_align { align_abi, align_opt, align_both };
(ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
|| (MODE) == V2DImode || (MODE) == V1TImode)
-#define SPE_VECTOR_MODE(MODE) \
- ((MODE) == V4HImode \
- || (MODE) == V2SFmode \
- || (MODE) == V1DImode \
- || (MODE) == V2SImode)
-
#define PAIRED_VECTOR_MODE(MODE) \
((MODE) == V2SFmode)
@@ -1347,9 +1328,9 @@ enum data_align { align_abi, align_opt, align_both };
? GET_MODE_CLASS (MODE2) == MODE_CC \
: GET_MODE_CLASS (MODE2) == MODE_CC \
? 0 \
- : SPE_VECTOR_MODE (MODE1) \
- ? SPE_VECTOR_MODE (MODE2) \
- : SPE_VECTOR_MODE (MODE2) \
+ : PAIRED_VECTOR_MODE (MODE1) \
+ ? PAIRED_VECTOR_MODE (MODE2) \
+ : PAIRED_VECTOR_MODE (MODE2) \
? 0 \
: 1)
@@ -2684,7 +2665,7 @@ extern int frame_pointer_needed;
#define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
/* Builtin targets. For now, we reuse the masks for those options that are in
- target flags, and pick three random bits for SPE, paired and ldbl128 which
+ target flags, and pick two random bits for paired and ldbl128, which
aren't in target_flags. */
#define RS6000_BTM_ALWAYS 0 /* Always enabled. */
#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
@@ -2695,7 +2676,6 @@ extern int frame_pointer_needed;
#define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
-#define RS6000_BTM_SPE MASK_STRING /* E500 */
#define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */
#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
#define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
@@ -2736,11 +2716,9 @@ extern int frame_pointer_needed;
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
@@ -2749,11 +2727,9 @@ extern int frame_pointer_needed;
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
enum rs6000_builtins
@@ -2769,11 +2745,9 @@ enum rs6000_builtins
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
enum rs6000_builtin_type_index
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 997d1fe..3fea231 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -56,8 +56,6 @@ (define_constants
(TFHAR_REGNO 114)
(TFIAR_REGNO 115)
(TEXASR_REGNO 116)
- (FIRST_SPE_HIGH_REGNO 117)
- (LAST_SPE_HIGH_REGNO 148)
])
;;
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index c5c11c5..a1a7753 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -381,14 +381,6 @@ mabi=no-altivec
Target RejectNegative Var(rs6000_altivec_abi, 0)
Do not use the AltiVec ABI extensions.
-mabi=spe
-Target RejectNegative Var(rs6000_spe_abi) Save
-Use the SPE ABI extensions.
-
-mabi=no-spe
-Target RejectNegative Var(rs6000_spe_abi, 0)
-Do not use the SPE ABI extensions.
-
mabi=elfv1
Target RejectNegative Var(rs6000_elf_abi, 1) Save
Use the ELFv1 ABI.
diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md
index 536697b..372e190 100644
--- a/gcc/config/rs6000/spe.md
+++ b/gcc/config/rs6000/spe.md
@@ -26,2770 +26,3 @@ (define_mode_iterator SPE64TF [DF V4HI V2SF V1DI V2SI TF])
;; DImode and TImode.
(define_mode_iterator DITI [DI TI])
-
-;; SPE SIMD instructions
-
-(define_insn "absv2si2"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
- "TARGET_SPE"
- "evabs %0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evandc"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
- "TARGET_SPE"
- "evandc %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "andv2si3"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
- "TARGET_SPE"
- "evand %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-;; Vector compare instructions
-
-(define_insn "spe_evcmpeq"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))]
- "TARGET_SPE"
- "evcmpeq %0,%1,%2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-(define_insn "spe_evcmpgts"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))]
- "TARGET_SPE"
- "evcmpgts %0,%1,%2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-(define_insn "spe_evcmpgtu"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))]
- "TARGET_SPE"
- "evcmpgtu %0,%1,%2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-(define_insn "spe_evcmplts"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))]
- "TARGET_SPE"
- "evcmplts %0,%1,%2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-(define_insn "spe_evcmpltu"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))]
- "TARGET_SPE"
- "evcmpltu %0,%1,%2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-;; Floating point vector compare instructions
-
-(define_insn "spe_evfscmpeq"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
- (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evfscmpeq %0,%1,%2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfscmpgt"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
- (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evfscmpgt %0,%1,%2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfscmplt"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
- (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evfscmplt %0,%1,%2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfststeq"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
- (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))]
- "TARGET_SPE"
- "evfststeq %0,%1,%2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfststgt"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
- (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))]
- "TARGET_SPE"
- "evfststgt %0,%1,%2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfststlt"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
- (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))]
- "TARGET_SPE"
- "evfststlt %0,%1,%2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-;; End of vector compare instructions
-
-(define_insn "spe_evcntlsw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))]
- "TARGET_SPE"
- "evcntlsw %0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evcntlzw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))]
- "TARGET_SPE"
- "evcntlzw %0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_eveqv"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
- "TARGET_SPE"
- "eveqv %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evextsb"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))]
- "TARGET_SPE"
- "evextsb %0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evextsh"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))]
- "TARGET_SPE"
- "evextsh %0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlhhesplat"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:QI 2 "immediate_operand" "i"))))
- (unspec [(const_int 0)] 509)]
- "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
- "evlhhesplat %0,%2*2(%1)"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlhhesplatx"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (unspec [(const_int 0)] 510)]
- "TARGET_SPE"
- "evlhhesplatx %0,%1,%2"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlhhossplat"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:QI 2 "immediate_operand" "i"))))
- (unspec [(const_int 0)] 511)]
- "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
- "evlhhossplat %0,%2*2(%1)"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlhhossplatx"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (unspec [(const_int 0)] 512)]
- "TARGET_SPE"
- "evlhhossplatx %0,%1,%2"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlhhousplat"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:QI 2 "immediate_operand" "i"))))
- (unspec [(const_int 0)] 513)]
- "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
- "evlhhousplat %0,%2*2(%1)"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlhhousplatx"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (unspec [(const_int 0)] 514)]
- "TARGET_SPE"
- "evlhhousplatx %0,%1,%2"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlwhsplat"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:QI 2 "immediate_operand" "i"))))
- (unspec [(const_int 0)] 515)]
- "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
- "evlwhsplat %0,%2*4(%1)"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlwhsplatx"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (unspec [(const_int 0)] 516)]
- "TARGET_SPE"
- "evlwhsplatx %0,%1,%2"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlwwsplat"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:QI 2 "immediate_operand" "i"))))
- (unspec [(const_int 0)] 517)]
- "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
- "evlwwsplat %0,%2*4(%1)"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlwwsplatx"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (unspec [(const_int 0)] 518)]
- "TARGET_SPE"
- "evlwwsplatx %0,%1,%2"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-;; Integer vector permutation instructions. The pairs of digits in the
-;; names of these instructions indicate the indices, in the memory vector
-;; element ordering, of the vector elements permuted to the output vector
-;; from the first and the second input vector respectively.
-
-(define_insn "vec_perm00_v2si"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (vec_select:V2SI
- (vec_concat:V4SI
- (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (parallel [(const_int 0) (const_int 2)])))]
- "TARGET_SPE"
-{
- if (WORDS_BIG_ENDIAN)
- return "evmergehi %0,%1,%2";
- else
- return "evmergelo %0,%2,%1";
-}
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "vec_perm01_v2si"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (vec_select:V2SI
- (vec_concat:V4SI
- (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (parallel [(const_int 0) (const_int 3)])))]
- "TARGET_SPE"
-{
- if (WORDS_BIG_ENDIAN)
- return "evmergehilo %0,%1,%2";
- else
- return "evmergehilo %0,%2,%1";
-}
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "vec_perm11_v2si"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (vec_select:V2SI
- (vec_concat:V4SI
- (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (parallel [(const_int 1) (const_int 3)])))]
- "TARGET_SPE"
-{
- if (WORDS_BIG_ENDIAN)
- return "evmergelo %0,%1,%2";
- else
- return "evmergehi %0,%2,%1";
-}
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "vec_perm10_v2si"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (vec_select:V2SI
- (vec_concat:V4SI
- (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (parallel [(const_int 1) (const_int 2)])))]
- "TARGET_SPE"
-{
- if (WORDS_BIG_ENDIAN)
- return "evmergelohi %0,%1,%2";
- else
- return "evmergelohi %0,%2,%1";
-}
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_expand "vec_perm_constv2si"
- [(match_operand:V2SI 0 "gpc_reg_operand" "")
- (match_operand:V2SI 1 "gpc_reg_operand" "")
- (match_operand:V2SI 2 "gpc_reg_operand" "")
- (match_operand:V2SI 3 "" "")]
- "TARGET_SPE"
-{
- if (rs6000_expand_vec_perm_const (operands))
- DONE;
- else
- FAIL;
-})
-
-(define_expand "spe_evmergehi"
- [(match_operand:V2SI 0 "register_operand" "")
- (match_operand:V2SI 1 "register_operand" "")
- (match_operand:V2SI 2 "register_operand" "")]
- "TARGET_SPE"
-{
- if (BYTES_BIG_ENDIAN)
- emit_insn (gen_vec_perm00_v2si (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_vec_perm11_v2si (operands[0], operands[2], operands[1]));
- DONE;
-})
-
-(define_expand "spe_evmergehilo"
- [(match_operand:V2SI 0 "register_operand" "")
- (match_operand:V2SI 1 "register_operand" "")
- (match_operand:V2SI 2 "register_operand" "")]
- "TARGET_SPE"
-{
- if (BYTES_BIG_ENDIAN)
- emit_insn (gen_vec_perm01_v2si (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_vec_perm01_v2si (operands[0], operands[2], operands[1]));
- DONE;
-})
-
-(define_expand "spe_evmergelo"
- [(match_operand:V2SI 0 "register_operand" "")
- (match_operand:V2SI 1 "register_operand" "")
- (match_operand:V2SI 2 "register_operand" "")]
- "TARGET_SPE"
-{
- if (BYTES_BIG_ENDIAN)
- emit_insn (gen_vec_perm11_v2si (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_vec_perm00_v2si (operands[0], operands[2], operands[1]));
- DONE;
-})
-
-(define_expand "spe_evmergelohi"
- [(match_operand:V2SI 0 "register_operand" "")
- (match_operand:V2SI 1 "register_operand" "")
- (match_operand:V2SI 2 "register_operand" "")]
- "TARGET_SPE"
-{
- if (BYTES_BIG_ENDIAN)
- emit_insn (gen_vec_perm10_v2si (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_vec_perm10_v2si (operands[0], operands[2], operands[1]));
- DONE;
-})
-
-;; End of integer vector permutation instructions.
-
-(define_insn "spe_evnand"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
- "TARGET_SPE"
- "evnand %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "negv2si2"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
- "TARGET_SPE"
- "evneg %0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evnor"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
- "TARGET_SPE"
- "evnor %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evorc"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
- "TARGET_SPE"
- "evorc %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evor"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
- "TARGET_SPE"
- "evor %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evrlwi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:QI 2 "immediate_operand" "i")] 519))]
- "TARGET_SPE"
- "evrlwi %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evrlw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))]
- "TARGET_SPE"
- "evrlw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evrndw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))]
- "TARGET_SPE"
- "evrndw %0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsel"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (match_operand:CC 3 "cc_reg_operand" "y")] 522))]
- "TARGET_SPE"
- "evsel %0,%1,%2,%3"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsel_fs"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")
- (match_operand:V2SF 2 "gpc_reg_operand" "r")
- (match_operand:CC 3 "cc_reg_operand" "y")] 725))]
- "TARGET_SPE"
- "evsel %0,%1,%2,%3"
- [(set_attr "type" "veccmp")
- (set_attr "length" "4")])
-
-(define_insn "spe_evslwi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:QI 2 "immediate_operand" "i")]
- 523))]
- "TARGET_SPE"
- "evslwi %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evslw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))]
- "TARGET_SPE"
- "evslw %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsrwis"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:QI 2 "immediate_operand" "i")]
- 525))]
- "TARGET_SPE"
- "evsrwis %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsrwiu"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:QI 2 "immediate_operand" "i")]
- 526))]
- "TARGET_SPE"
- "evsrwiu %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsrws"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))]
- "TARGET_SPE"
- "evsrws %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsrwu"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))]
- "TARGET_SPE"
- "evsrwu %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-;; vector xors
-
-(define_insn "xorv2si3"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
- "TARGET_SPE"
- "evxor %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "xorv4hi3"
- [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r")
- (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r")
- (match_operand:V4HI 2 "gpc_reg_operand" "r")))]
- "TARGET_SPE"
- "evxor %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "xorv1di3"
- [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r")
- (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r")
- (match_operand:V1DI 2 "gpc_reg_operand" "r")))]
- "TARGET_SPE"
- "evxor %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-;; end of vector xors
-
-(define_insn "spe_evfsabs"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
- "TARGET_SPE"
- "evfsabs %0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfsadd"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
- (match_operand:V2SF 2 "gpc_reg_operand" "r")))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evfsadd %0,%1,%2"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfscfsf"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))]
- "TARGET_SPE"
- "evfscfsf %0,%1"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfscfsi"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
- "TARGET_SPE"
- "evfscfsi %0,%1"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfscfuf"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))]
- "TARGET_SPE"
- "evfscfuf %0,%1"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfscfui"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))]
- "TARGET_SPE"
- "evfscfui %0,%1"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfsctsf"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))]
- "TARGET_SPE"
- "evfsctsf %0,%1"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfsctsi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))]
- "TARGET_SPE"
- "evfsctsi %0,%1"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfsctsiz"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))]
- "TARGET_SPE"
- "evfsctsiz %0,%1"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfsctuf"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))]
- "TARGET_SPE"
- "evfsctuf %0,%1"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfsctui"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))]
- "TARGET_SPE"
- "evfsctui %0,%1"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfsctuiz"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))]
- "TARGET_SPE"
- "evfsctuiz %0,%1"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfsdiv"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
- (match_operand:V2SF 2 "gpc_reg_operand" "r")))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evfsdiv %0,%1,%2"
- [(set_attr "type" "vecfdiv")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfsmul"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
- (match_operand:V2SF 2 "gpc_reg_operand" "r")))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evfsmul %0,%1,%2"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfsnabs"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))]
- "TARGET_SPE"
- "evfsnabs %0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfsneg"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
- "TARGET_SPE"
- "evfsneg %0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evfssub"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
- (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
- (match_operand:V2SF 2 "gpc_reg_operand" "r")))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evfssub %0,%1,%2"
- [(set_attr "type" "vecfloat")
- (set_attr "length" "4")])
-
-;; SPE SIMD load instructions.
-
-;; Only the hardware engineer who designed the SPE understands the
-;; plethora of load and store instructions ;-). We have no way of
-;; differentiating between them with RTL so use an unspec of const_int 0
-;; to avoid identical RTL.
-
-(define_insn "spe_evldd"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:QI 2 "immediate_operand" "i"))))
- (unspec [(const_int 0)] 544)]
- "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
- "evldd %0,%2*8(%1)"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlddx"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (unspec [(const_int 0)] 545)]
- "TARGET_SPE"
- "evlddx %0,%1,%2"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evldh"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:QI 2 "immediate_operand" "i"))))
- (unspec [(const_int 0)] 546)]
- "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
- "evldh %0,%2*8(%1)"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evldhx"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (unspec [(const_int 0)] 547)]
- "TARGET_SPE"
- "evldhx %0,%1,%2"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evldw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:QI 2 "immediate_operand" "i"))))
- (unspec [(const_int 0)] 548)]
- "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
- "evldw %0,%2*8(%1)"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evldwx"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (unspec [(const_int 0)] 549)]
- "TARGET_SPE"
- "evldwx %0,%1,%2"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlwhe"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:QI 2 "immediate_operand" "i"))))
- (unspec [(const_int 0)] 550)]
- "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
- "evlwhe %0,%2*4(%1)"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlwhex"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (unspec [(const_int 0)] 551)]
- "TARGET_SPE"
- "evlwhex %0,%1,%2"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlwhos"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:QI 2 "immediate_operand" "i"))))
- (unspec [(const_int 0)] 552)]
- "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
- "evlwhos %0,%2*4(%1)"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlwhosx"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (unspec [(const_int 0)] 553)]
- "TARGET_SPE"
- "evlwhosx %0,%1,%2"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlwhou"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:QI 2 "immediate_operand" "i"))))
- (unspec [(const_int 0)] 554)]
- "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
- "evlwhou %0,%2*4(%1)"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_evlwhoux"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (unspec [(const_int 0)] 555)]
- "TARGET_SPE"
- "evlwhoux %0,%1,%2"
- [(set_attr "type" "vecload")
- (set_attr "length" "4")])
-
-(define_insn "spe_brinc"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")] 556))]
- "TARGET_SPE"
- "brinc %0,%1,%2"
- [(set_attr "type" "brinc")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhegsmfaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 557))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhegsmfaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhegsmfan"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 558))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhegsmfan %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhegsmiaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 559))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhegsmiaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhegsmian"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 560))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhegsmian %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhegumiaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 561))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhegumiaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhegumian"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 562))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhegumian %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhesmfaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 563))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhesmfaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhesmfanw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 564))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhesmfanw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhesmfa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhesmfa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhesmf"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))]
- "TARGET_SPE"
- "evmhesmf %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhesmiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 567))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhesmiaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhesmianw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 568))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhesmianw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhesmia"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhesmia %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhesmi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))]
- "TARGET_SPE"
- "evmhesmi %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhessfaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 571))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhessfaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhessfanw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 572))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhessfanw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhessfa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhessfa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhessf"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evmhessf %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhessiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 575))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhessiaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhessianw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 576))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhessianw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmheumiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 577))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmheumiaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmheumianw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 578))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmheumianw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmheumia"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmheumia %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmheumi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))]
- "TARGET_SPE"
- "evmheumi %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmheusiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 581))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmheusiaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmheusianw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 582))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmheusianw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhogsmfaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 583))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhogsmfaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhogsmfan"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 584))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhogsmfan %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhogsmiaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 585))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhogsmiaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhogsmian"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 586))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhogsmian %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhogumiaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 587))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhogumiaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhogumian"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 588))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhogumian %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhosmfaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 589))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhosmfaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhosmfanw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 590))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhosmfanw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhosmfa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))]
- "TARGET_SPE"
- "evmhosmfa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhosmf"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhosmf %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhosmiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 593))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhosmiaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhosmianw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 594))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhosmianw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhosmia"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhosmia %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhosmi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))]
- "TARGET_SPE"
- "evmhosmi %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhossfaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 597))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhossfaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhossfanw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 598))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhossfanw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhossfa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 599))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhossfa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhossf"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evmhossf %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhossiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 601))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhossiaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhossianw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 602))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhossianw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhoumiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 603))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhoumiaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhoumianw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 604))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhoumianw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhoumia"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhoumia %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhoumi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))]
- "TARGET_SPE"
- "evmhoumi %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhousiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 607))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhousiaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmhousianw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 608))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmhousianw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmmlssfa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))]
- "TARGET_SPE"
- "evmmlssfa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmmlssf"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))]
- "TARGET_SPE"
- "evmmlssf %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhsmfa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhsmfa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhsmf"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))]
- "TARGET_SPE"
- "evmwhsmf %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhsmia"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhsmia %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhsmi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))]
- "TARGET_SPE"
- "evmwhsmi %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhssfa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhssfa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhusian"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))]
- "TARGET_SPE"
- "evmwhusian %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhssf"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evmwhssf %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhumia"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhumia %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhumi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))]
- "TARGET_SPE"
- "evmwhumi %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwlsmiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 635))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwlsmiaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwlsmianw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 636))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwlsmianw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwlssiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 641))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwlssiaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwlssianw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 642))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwlssianw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwlumiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 643))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwlumiaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwlumianw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 644))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwlumianw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwlumia"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwlumia %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwlumi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))]
- "TARGET_SPE"
- "evmwlumi %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwlusiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 647))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwlusiaaw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwlusianw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 648))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwlusianw %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwsmfaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 649))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwsmfaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwsmfan"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 650))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwsmfan %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwsmfa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwsmfa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwsmf"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))]
- "TARGET_SPE"
- "evmwsmf %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwsmiaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 653))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwsmiaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwsmian"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 654))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwsmian %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwsmia"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwsmia %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwsmi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))]
- "TARGET_SPE"
- "evmwsmi %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwssfaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 657))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwssfaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwssfan"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 658))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwssfan %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwssfa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwssfa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwssf"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evmwssf %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwumiaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 661))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwumiaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwumian"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 662))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwumian %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwumia"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwumia %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwumi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))]
- "TARGET_SPE"
- "evmwumi %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "addv2si3"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
- "TARGET_SPE"
- "evaddw %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evaddusiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 673))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evaddusiaaw %0,%1"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evaddumiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 674))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evaddumiaaw %0,%1"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evaddssiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 675))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evaddssiaaw %0,%1"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evaddsmiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 676))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evaddsmiaaw %0,%1"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evaddiw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:QI 2 "immediate_operand" "i")] 677))]
- "TARGET_SPE"
- "evaddiw %0,%1,%2"
- [(set_attr "type" "vecsimple")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsubifw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:QI 2 "immediate_operand" "i")] 678))]
- "TARGET_SPE"
- "evsubifw %0,%2,%1"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "subv2si3"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
- "TARGET_SPE"
- "evsubfw %0,%2,%1"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsubfusiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 679))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evsubfusiaaw %0,%1"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsubfumiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 680))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evsubfumiaaw %0,%1"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsubfssiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 681))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evsubfssiaaw %0,%1"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsubfsmiaaw"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (reg:V2SI SPE_ACC_REGNO)] 682))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evsubfsmiaaw %0,%1"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmra"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (match_operand:V2SI 1 "gpc_reg_operand" "r"))
- (set (reg:V2SI SPE_ACC_REGNO)
- (unspec:V2SI [(match_dup 1)] 726))]
- "TARGET_SPE"
- "evmra %0,%1"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "divv2si3"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evdivws %0,%1,%2"
- [(set_attr "type" "vecdiv")
- (set_attr "length" "4")])
-
-(define_insn "spe_evdivwu"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")))
- (clobber (reg:SI SPEFSCR_REGNO))]
- "TARGET_SPE"
- "evdivwu %0,%1,%2"
- [(set_attr "type" "vecdiv")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsplatfi"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))]
- "TARGET_SPE"
- "evsplatfi %0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
-
-(define_insn "spe_evsplati"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))]
- "TARGET_SPE"
- "evsplati %0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstdd"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:QI 1 "immediate_operand" "i")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 686)]
- "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
- "evstdd %2,%1*8(%0)"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstddx"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:SI 1 "gpc_reg_operand" "r")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 687)]
- "TARGET_SPE"
- "evstddx %2,%0,%1"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstdh"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:QI 1 "immediate_operand" "i")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 688)]
- "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
- "evstdh %2,%1*8(%0)"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstdhx"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:SI 1 "gpc_reg_operand" "r")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 689)]
- "TARGET_SPE"
- "evstdhx %2,%0,%1"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstdw"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:QI 1 "immediate_operand" "i")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 690)]
- "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
- "evstdw %2,%1*8(%0)"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstdwx"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:SI 1 "gpc_reg_operand" "r")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 691)]
- "TARGET_SPE"
- "evstdwx %2,%0,%1"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstwhe"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:QI 1 "immediate_operand" "i")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 692)]
- "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
- "evstwhe %2,%1*4(%0)"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstwhex"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:SI 1 "gpc_reg_operand" "r")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 693)]
- "TARGET_SPE"
- "evstwhex %2,%0,%1"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstwho"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:QI 1 "immediate_operand" "i")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 694)]
- "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
- "evstwho %2,%1*4(%0)"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstwhox"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:SI 1 "gpc_reg_operand" "r")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 695)]
- "TARGET_SPE"
- "evstwhox %2,%0,%1"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstwwe"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:QI 1 "immediate_operand" "i")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 696)]
- "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
- "evstwwe %2,%1*4(%0)"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstwwex"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:SI 1 "gpc_reg_operand" "r")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 697)]
- "TARGET_SPE"
- "evstwwex %2,%0,%1"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstwwo"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:QI 1 "immediate_operand" "i")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 698)]
- "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
- "evstwwo %2,%1*4(%0)"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-(define_insn "spe_evstwwox"
- [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
- (match_operand:SI 1 "gpc_reg_operand" "r")))
- (match_operand:V2SI 2 "gpc_reg_operand" "r"))
- (unspec [(const_int 0)] 699)]
- "TARGET_SPE"
- "evstwwox %2,%0,%1"
- [(set_attr "type" "vecstore")
- (set_attr "length" "4")])
-
-;; Double-precision floating point instructions.
-
-;; FIXME: Add o=r option.
-(define_insn "*frob_<SPE64:mode>_<DITI:mode>"
- [(set (match_operand:SPE64 0 "nonimmediate_operand" "=r,r")
- (subreg:SPE64 (match_operand:DITI 1 "input_operand" "r,m") 0))]
- "TARGET_SPE && <SPE64:MODE>mode != DFmode"
-{
- switch (which_alternative)
- {
- default:
- gcc_unreachable ();
- case 0:
- if (WORDS_BIG_ENDIAN)
- return "evmergelo %0,%1,%L1";
- else
- return "evmergelo %0,%L1,%1";
- case 1:
- return "evldd%X1 %0,%y1";
- }
-})
-
-(define_insn "*frob_<SPE64:mode>_ti_8"
- [(set (match_operand:SPE64 0 "nonimmediate_operand" "=r")
- (subreg:SPE64 (match_operand:TI 1 "input_operand" "r") 8))]
- "TARGET_SPE && <SPE64:MODE>mode != DFmode"
-{
- if (WORDS_BIG_ENDIAN)
- return "evmergelo %0,%Y1,%Z1";
- else
- return "evmergelo %0,%Z1,%Y1";
-})
-
-(define_insn "*frob_<mode>_di_2"
- [(set (subreg:DI (match_operand:SPE64TF 0 "nonimmediate_operand" "+&r,r") 0)
- (match_operand:DI 1 "input_operand" "r,m"))]
- "TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
-{
- switch (which_alternative)
- {
- default:
- gcc_unreachable ();
- case 0:
- if (WORDS_BIG_ENDIAN)
- return "evmergelo %0,%1,%L1";
- else
- return "evmergelo %0,%L1,%1";
- case 1:
- return "evldd%X1 %0,%y1";
- }
-})
-
-(define_insn "*frob_di_<mode>"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=&r")
- (subreg:DI (match_operand:SPE64TF 1 "input_operand" "r") 0))]
- "TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
-{
- if (WORDS_BIG_ENDIAN)
- return "evmergehi %0,%1,%1\;mr %L0,%1";
- else
- return "evmergehi %L0,%1,%1\;mr %0,%1";
-}
- [(set_attr "length" "8")])
-
-(define_insn "*frob_<DITI:mode>_<SPE64:mode>_2"
- [(set (subreg:SPE64 (match_operand:DITI 0 "register_operand" "+&r,r") 0)
- (match_operand:SPE64 1 "input_operand" "r,m"))]
- "TARGET_SPE && <SPE64:MODE>mode != DFmode"
- "*
-{
- switch (which_alternative)
- {
- default:
- gcc_unreachable ();
- case 0:
- if (WORDS_BIG_ENDIAN)
- return \"evmergehi %0,%1,%1\;mr %L0,%1\";
- else
- return \"evmergehi %L0,%1,%1\;mr %0,%1\";
- case 1:
- /* If the address is not offsettable we need to load the whole
- doubleword into a 64-bit register and then copy the high word
- to form the correct output layout. */
- if (!offsettable_nonstrict_memref_p (operands[1]))
- {
- if (WORDS_BIG_ENDIAN)
- return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\";
- else
- return \"evldd%X1 %0,%y1\;evmergehi %L0,%0,%0\";
- }
- /* If the low-address word is used in the address, we must load
- it last. Otherwise, load it first. Note that we cannot have
- auto-increment in that case since the address register is
- known to be dead. */
- if (refers_to_regno_p (REGNO (operands[0]), operands[1]))
- {
- if (WORDS_BIG_ENDIAN)
- return \"lwz %L0,%L1\;lwz %0,%1\";
- else
- return \"lwz %0,%1\;lwz %L0,%L1\";
- }
- else
- {
- if (WORDS_BIG_ENDIAN)
- return \"lwz%U1%X1 %0,%1\;lwz %L0,%L1\";
- else
- return \"lwz%U1%X1 %L0,%L1\;lwz %0,%1\";
- }
- }
-}"
- [(set_attr "length" "8,8")])
-
-; As the above, but TImode at offset 8.
-(define_insn "*frob_ti_<mode>_8_2"
- [(set (subreg:SPE64 (match_operand:TI 0 "register_operand" "+&r,r") 8)
- (match_operand:SPE64 1 "input_operand" "r,m"))]
- "TARGET_SPE && <MODE>mode != DFmode"
- "*
-{
- switch (which_alternative)
- {
- default:
- gcc_unreachable ();
- case 0:
- if (WORDS_BIG_ENDIAN)
- return \"evmergehi %Y0,%1,%1\;mr %Z0,%1\";
- else
- return \"evmergehi %Z0,%1,%1\;mr %Y0,%1\";
- case 1:
- if (!offsettable_nonstrict_memref_p (operands[1]))
- {
- if (WORDS_BIG_ENDIAN)
- return \"evldd%X1 %Z0,%y1\;evmergehi %Y0,%Z0,%Z0\";
- else
- return \"evldd%X1 %Y0,%y1\;evmergehi %Z0,%Y0,%Y0\";
- }
- if (refers_to_regno_p (REGNO (operands[0]), operands[1]))
- {
- if (WORDS_BIG_ENDIAN)
- return \"lwz %Z0,%L1\;lwz %Y0,%1\";
- else
- return \"lwz %Y0,%1\;lwz %Z0,%L1\";
- }
- else
- {
- if (WORDS_BIG_ENDIAN)
- return \"lwz%U1%X1 %Y0,%1\;lwz %Z0,%L1\";
- else
- return \"lwz%U1%X1 %Z0,%L1\;lwz %Y0,%1\";
- }
- }
-}"
- [(set_attr "length" "8,8")])
-
-(define_insn "mov_si<mode>_e500_subreg0_be"
- [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 0)
- (match_operand:SI 1 "input_operand" "r,m"))]
- "WORDS_BIG_ENDIAN
- && (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
- "@
- evmergelo %0,%1,%0
- evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0"
- [(set_attr "length" "4,12")])
-
-(define_insn "*mov_si<mode>_e500_subreg0_le"
- [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 0)
- (match_operand:SI 1 "input_operand" "r,m"))]
- "!WORDS_BIG_ENDIAN
- && (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
- "@
- mr %0,%1
- lwz%U1%X1 %0,%1")
-
-(define_insn_and_split "*mov_si<mode>_e500_subreg0_elf_low_be"
- [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0)
- (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand 2 "" "")))]
- "WORDS_BIG_ENDIAN
- && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode
- && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(pc)]
-{
- rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_elf_low (tmp, operands[1], operands[2]));
- emit_insn (gen_mov_si<mode>_e500_subreg0_be (operands[0], tmp));
- DONE;
-}
- [(set_attr "length" "8")])
-
-(define_insn "*mov_si<mode>_e500_subreg0_elf_low_le"
- [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0)
- (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand 2 "" "")))]
- "!WORDS_BIG_ENDIAN
- && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode
- && TARGET_ELF && !TARGET_64BIT"
- "addi %0,%1,%K2")
-
-;; ??? Could use evstwwe for memory stores in some cases, depending on
-;; the offset.
-(define_insn "*mov_si<mode>_e500_subreg0_2_be"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
- (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))]
- "WORDS_BIG_ENDIAN
- && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
- "@
- evmergelohi %0,%1,%1
- evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
- [(set_attr "length" "4,8")])
-
-(define_insn "*mov_si<mode>_e500_subreg0_2_le"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
- (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 0))]
- "!WORDS_BIG_ENDIAN
- && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
- "@
- mr %0,%1
- stw%U0%X0 %1,%0")
-
-(define_insn "*mov_si<mode>_e500_subreg4_be"
- [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 4)
- (match_operand:SI 1 "input_operand" "r,m"))]
- "WORDS_BIG_ENDIAN
- && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
- "@
- mr %0,%1
- lwz%U1%X1 %0,%1")
-
-(define_insn "mov_si<mode>_e500_subreg4_le"
- [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 4)
- (match_operand:SI 1 "input_operand" "r,m"))]
- "!WORDS_BIG_ENDIAN
- && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
- "@
- evmergelo %0,%1,%0
- evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0"
- [(set_attr "length" "4,12")])
-
-(define_insn "*mov_si<mode>_e500_subreg4_elf_low_be"
- [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4)
- (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand 2 "" "")))]
- "WORDS_BIG_ENDIAN
- && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode
- && TARGET_ELF && !TARGET_64BIT"
- "addi %0,%1,%K2")
-
-(define_insn_and_split "*mov_si<mode>_e500_subreg4_elf_low_le"
- [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4)
- (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand 2 "" "")))]
- "!WORDS_BIG_ENDIAN
- && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode
- && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(pc)]
-{
- rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_elf_low (tmp, operands[1], operands[2]));
- emit_insn (gen_mov_si<mode>_e500_subreg4_le (operands[0], tmp));
- DONE;
-}
- [(set_attr "length" "8")])
-
-(define_insn "*mov_si<mode>_e500_subreg4_2_be"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
- (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
- "WORDS_BIG_ENDIAN
- && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
- "@
- mr %0,%1
- stw%U0%X0 %1,%0")
-
-(define_insn "*mov_si<mode>_e500_subreg4_2_le"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
- (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 4))]
- "!WORDS_BIG_ENDIAN
- && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
- "@
- evmergelohi %0,%1,%1
- evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
- [(set_attr "length" "4,8")])
-
-;; Vector move instructions.
-
-(define_expand "movv2si"
- [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
- (match_operand:V2SI 1 "any_operand" ""))]
- "TARGET_SPE"
- "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }")
-
-(define_insn "*movv2si_internal"
- [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r")
- (match_operand:V2SI 1 "input_operand" "r,m,r,W"))]
- "TARGET_SPE
- && (gpc_reg_operand (operands[0], V2SImode)
- || gpc_reg_operand (operands[1], V2SImode))"
- "*
-{
- switch (which_alternative)
- {
- case 0: return \"evstdd%X0 %1,%y0\";
- case 1: return \"evldd%X1 %0,%y1\";
- case 2: return \"evor %0,%1,%1\";
- case 3: return output_vec_const_move (operands);
- default: gcc_unreachable ();
- }
-}"
- [(set_attr "type" "vecload,vecstore,*,*")
- (set_attr "length" "*,*,*,12")])
-
-(define_split
- [(set (match_operand:V2SI 0 "register_operand" "")
- (match_operand:V2SI 1 "zero_constant" ""))]
- "TARGET_SPE && reload_completed"
- [(set (match_dup 0)
- (xor:V2SI (match_dup 0) (match_dup 0)))]
- "")
-
-(define_expand "movv1di"
- [(set (match_operand:V1DI 0 "nonimmediate_operand" "")
- (match_operand:V1DI 1 "any_operand" ""))]
- "TARGET_SPE"
- "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }")
-
-(define_insn "*movv1di_internal"
- [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r")
- (match_operand:V1DI 1 "input_operand" "r,m,r,W"))]
- "TARGET_SPE
- && (gpc_reg_operand (operands[0], V1DImode)
- || gpc_reg_operand (operands[1], V1DImode))"
- "@
- evstdd%X0 %1,%y0
- evldd%X1 %0,%y1
- evor %0,%1,%1
- evxor %0,%0,%0"
- [(set_attr "type" "vecload,vecstore,*,*")
- (set_attr "length" "*,*,*,*")])
-
-(define_expand "movv4hi"
- [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
- (match_operand:V4HI 1 "any_operand" ""))]
- "TARGET_SPE"
- "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }")
-
-(define_insn "*movv4hi_internal"
- [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r")
- (match_operand:V4HI 1 "input_operand" "r,m,r,W"))]
- "TARGET_SPE
- && (gpc_reg_operand (operands[0], V4HImode)
- || gpc_reg_operand (operands[1], V4HImode))"
- "@
- evstdd%X0 %1,%y0
- evldd%X1 %0,%y1
- evor %0,%1,%1
- evxor %0,%0,%0"
- [(set_attr "type" "vecload")])
-
-(define_expand "movv2sf"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
- (match_operand:V2SF 1 "any_operand" ""))]
- "TARGET_SPE || TARGET_PAIRED_FLOAT"
- "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }")
-
-(define_insn "*movv2sf_internal"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r")
- (match_operand:V2SF 1 "input_operand" "r,m,r,W"))]
- "TARGET_SPE
- && (gpc_reg_operand (operands[0], V2SFmode)
- || gpc_reg_operand (operands[1], V2SFmode))"
- "@
- evstdd%X0 %1,%y0
- evldd%X1 %0,%y1
- evor %0,%1,%1
- evxor %0,%0,%0"
- [(set_attr "type" "vecload,vecstore,*,*")
- (set_attr "length" "*,*,*,*")])
-
-;; End of vector move instructions.
-
-(define_insn "spe_evmwhssfaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhssfaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhssmaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhssmaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhsmfaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhsmfaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhsmiaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhsmiaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhusiaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhusiaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhumiaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhumiaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhssfan"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhssfan %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhssian"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhssian %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhsmfan"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhsmfan %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhsmian"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhsmian %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhumian"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhumian %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhgssfaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhgssfaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhgsmfaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhgsmfaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhgsmiaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhgsmiaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhgumiaa"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhgumiaa %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhgssfan"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718))
- (clobber (reg:SI SPEFSCR_REGNO))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhgssfan %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhgsmfan"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhgsmfan %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhgsmian"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhgsmian %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_evmwhgumian"
- [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
- (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
- (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721))
- (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
- "TARGET_SPE"
- "evmwhgumian %0,%1,%2"
- [(set_attr "type" "veccomplex")
- (set_attr "length" "4")])
-
-(define_insn "spe_mtspefscr"
- [(set (reg:SI SPEFSCR_REGNO)
- (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
- 722))]
- "TARGET_SPE"
- "mtspefscr %0"
- [(set_attr "type" "vecsimple")])
-
-(define_insn "spe_mfspefscr"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))]
- "TARGET_SPE"
- "mfspefscr %0"
- [(set_attr "type" "vecsimple")])
-
-;; MPC8540 single-precision FP instructions on GPRs.
-;; We have 2 variants for each. One for IEEE compliant math and one
-;; for non IEEE compliant math.
-
-;; Out-of-line prologues and epilogues.
-(define_insn "*save_gpregs_spe"
- [(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P LR_REGNO))
- (use (match_operand:P 1 "symbol_ref_operand" "s"))
- (use (reg:P 11))
- (set (match_operand:V2SI 2 "memory_operand" "=m")
- (match_operand:V2SI 3 "gpc_reg_operand" "r"))])]
- "TARGET_SPE_ABI"
- "bl %z1"
- [(set_attr "type" "branch")
- (set_attr "length" "4")])
-
-(define_insn "*restore_gpregs_spe"
- [(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P LR_REGNO))
- (use (match_operand:P 1 "symbol_ref_operand" "s"))
- (use (reg:P 11))
- (set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
- (match_operand:V2SI 3 "memory_operand" "m"))])]
- "TARGET_SPE_ABI"
- "bl %z1"
- [(set_attr "type" "branch")
- (set_attr "length" "4")])
-
-(define_insn "*return_and_restore_gpregs_spe"
- [(match_parallel 0 "any_parallel_operand"
- [(return)
- (clobber (reg:P LR_REGNO))
- (use (match_operand:P 1 "symbol_ref_operand" "s"))
- (use (reg:P 11))
- (set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
- (match_operand:V2SI 3 "memory_operand" "m"))])]
- "TARGET_SPE_ABI"
- "b %z1"
- [(set_attr "type" "branch")
- (set_attr "length" "4")])
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index ea8169f..a3d53e7 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -1309,98 +1309,3 @@ (define_expand "reduc_<VEC_reduc:VEC_reduc_name>_scal_<VEC_F:mode>"
emit_insn (gen_vsx_extract_<VEC_F:mode> (operand0, vec, elt));
DONE;
})
-
-\f
-;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems.
-
-(define_expand "absv2sf2"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
- (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
- "TARGET_PAIRED_FLOAT || TARGET_SPE"
- "")
-
-(define_expand "negv2sf2"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
- (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
- "TARGET_PAIRED_FLOAT || TARGET_SPE"
- "")
-
-(define_expand "addv2sf3"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
- (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
- (match_operand:V2SF 2 "gpc_reg_operand" "")))]
- "TARGET_PAIRED_FLOAT || TARGET_SPE"
- "
-{
- if (TARGET_SPE)
- {
- /* We need to make a note that we clobber SPEFSCR. */
- rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
-
- XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
- gen_rtx_PLUS (V2SFmode, operands[1], operands[2]));
- XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
- emit_insn (par);
- DONE;
- }
-}")
-
-(define_expand "subv2sf3"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
- (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
- (match_operand:V2SF 2 "gpc_reg_operand" "")))]
- "TARGET_PAIRED_FLOAT || TARGET_SPE"
- "
-{
- if (TARGET_SPE)
- {
- /* We need to make a note that we clobber SPEFSCR. */
- rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
-
- XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
- gen_rtx_MINUS (V2SFmode, operands[1], operands[2]));
- XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
- emit_insn (par);
- DONE;
- }
-}")
-
-(define_expand "mulv2sf3"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
- (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
- (match_operand:V2SF 2 "gpc_reg_operand" "")))]
- "TARGET_PAIRED_FLOAT || TARGET_SPE"
- "
-{
- if (TARGET_SPE)
- {
- /* We need to make a note that we clobber SPEFSCR. */
- rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
-
- XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
- gen_rtx_MULT (V2SFmode, operands[1], operands[2]));
- XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
- emit_insn (par);
- DONE;
- }
-}")
-
-(define_expand "divv2sf3"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
- (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
- (match_operand:V2SF 2 "gpc_reg_operand" "")))]
- "TARGET_PAIRED_FLOAT || TARGET_SPE"
- "
-{
- if (TARGET_SPE)
- {
- /* We need to make a note that we clobber SPEFSCR. */
- rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
-
- XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
- gen_rtx_DIV (V2SFmode, operands[1], operands[2]));
- XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
- emit_insn (par);
- DONE;
- }
-}")
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 06/14] rs6000: Remove UNSPEC_MV_CR_GT
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
` (4 preceding siblings ...)
2017-06-06 15:57 ` [PATCH 01/14] rs6000: Remove TARGET_FPRS Segher Boessenkool
@ 2017-06-06 15:58 ` Segher Boessenkool
2017-06-06 17:02 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 07/14] rs6000: Remove TARGET_SPE and TARGET_SPE_ABI and friends Segher Boessenkool
` (7 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:58 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
config/rs6000/rs6000.md (UNSPEC_MV_CR_GT): Delete.
---
gcc/config/rs6000/rs6000.md | 1 -
1 file changed, 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 108ad8f..997d1fe 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -95,7 +95,6 @@ (define_c_enum "unspec"
UNSPEC_TLSGOTTPREL
UNSPEC_TLSTLS
UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
- UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
UNSPEC_STFIWX
UNSPEC_POPCNTB
UNSPEC_FRES
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 12/14] rs6000: Remove SPE high registers
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
` (8 preceding siblings ...)
2017-06-06 15:58 ` [PATCH 11/14] rs6000: Remove type attribute "brinc" Segher Boessenkool
@ 2017-06-06 15:58 ` Segher Boessenkool
2017-06-06 17:09 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 09/14] rs6000: Remove reg_or_none500mem_operand Segher Boessenkool
` (3 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:58 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
Now we can remove the SPE high registers.
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE high
registers.
* config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Ditto.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Change from 149
to 117.
(DWARF_REG_TO_UNWIND_COLUMN): Do not define.
(FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS):
Delete the SPE high registers.
(REG_ALLOC_ORDER): Ditto.
(enum reg_class): Remove SPE_HIGH_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Delete the SPE high registers.
(REGISTER_NAMES): Ditto.
(rs6000_reg_names): Ditto.
* doc/tm.texi.in: Remove SPE as example.
* doc/tm.texi: Regenerate.
---
gcc/config/rs6000/darwin.h | 6 +--
gcc/config/rs6000/rs6000.c | 14 +-----
gcc/config/rs6000/rs6000.h | 122 ++++++++++-----------------------------------
gcc/doc/tm.texi | 2 -
gcc/doc/tm.texi.in | 2 -
5 files changed, 30 insertions(+), 116 deletions(-)
diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index 61e5e83..2422f25 100644
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -194,11 +194,7 @@ extern int darwin_emit_branch_islands;
"vrsave", "vscr", \
"spe_acc", "spefscr", \
"sfp", \
- "tfhar", "tfiar", "texasr", \
- "rh0", "rh1", "rh2", "rh3", "rh4", "rh5", "rh6", "rh7", \
- "rh8", "rh9", "rh10", "rh11", "rh12", "rh13", "rh14", "rh15", \
- "rh16", "rh17", "rh18", "rh19", "rh20", "rh21", "rh22", "rh23", \
- "rh24", "rh25", "rh26", "rh27", "rh28", "rh29", "rh30", "rh31" \
+ "tfhar", "tfiar", "texasr" \
}
/* This outputs NAME to FILE. */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 89f9fc2..426400c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1478,12 +1478,7 @@ char rs6000_reg_names[][8] =
/* Soft frame pointer. */
"sfp",
/* HTM SPR registers. */
- "tfhar", "tfiar", "texasr",
- /* SPE High registers. */
- "0", "1", "2", "3", "4", "5", "6", "7",
- "8", "9", "10", "11", "12", "13", "14", "15",
- "16", "17", "18", "19", "20", "21", "22", "23",
- "24", "25", "26", "27", "28", "29", "30", "31"
+ "tfhar", "tfiar", "texasr"
};
#ifdef TARGET_REGNAMES
@@ -1511,12 +1506,7 @@ static const char alt_reg_names[][8] =
/* Soft frame pointer. */
"sfp",
/* HTM SPR registers. */
- "tfhar", "tfiar", "texasr",
- /* SPE High registers. */
- "%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7",
- "%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15",
- "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
- "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
+ "tfhar", "tfiar", "texasr"
};
#endif
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index da3b877..a154c5d 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1017,7 +1017,7 @@ enum data_align { align_abi, align_opt, align_both };
The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
-#define FIRST_PSEUDO_REGISTER 149
+#define FIRST_PSEUDO_REGISTER 117
/* This must be included for pre gcc 3.0 glibc compatibility. */
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
@@ -1026,16 +1026,6 @@ enum data_align { align_abi, align_opt, align_both };
aren't included in DWARF_FRAME_REGISTERS. */
#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
-/* The SPE has an additional 32 synthetic registers, with DWARF debug
- info numbering for these registers starting at 1200. While eh_frame
- register numbering need not be the same as the debug info numbering,
- we choose to number these regs for eh_frame at 1200 too.
-
- We must map them here to avoid huge unwinder tables mostly consisting
- of unused space. */
-#define DWARF_REG_TO_UNWIND_COLUMN(r) \
- ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
-
/* Use standard DWARF numbering for DWARF debugging information. */
#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
@@ -1066,10 +1056,7 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \
- , 1, 1, 1, 1, 1, 1, \
- /* SPE High registers. */ \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
+ , 1, 1, 1, 1, 1, 1 \
}
/* 1 for registers not available across function calls.
@@ -1089,10 +1076,7 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \
- , 1, 1, 1, 1, 1, 1, \
- /* SPE High registers. */ \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
+ , 1, 1, 1, 1, 1, 1 \
}
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -1111,10 +1095,7 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0 \
- , 0, 0, 0, 0, 0, 0, \
- /* SPE High registers. */ \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
+ , 0, 0, 0, 0, 0, 0 \
}
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -1198,10 +1179,7 @@ enum data_align { align_abi, align_opt, align_both };
96, 95, 94, 93, 92, 91, \
108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
109, 110, \
- 111, 112, 113, 114, 115, 116, \
- 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \
- 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \
- 141, 142, 143, 144, 145, 146, 147, 148 \
+ 111, 112, 113, 114, 115, 116 \
}
/* True if register is floating-point. */
@@ -1439,7 +1417,6 @@ enum reg_class
CR_REGS,
NON_FLOAT_REGS,
CA_REGS,
- SPE_HIGH_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1471,7 +1448,6 @@ enum reg_class
"CR_REGS", \
"NON_FLOAT_REGS", \
"CA_REGS", \
- "SPE_HIGH_REGS", \
"ALL_REGS" \
}
@@ -1482,51 +1458,49 @@ enum reg_class
#define REG_CLASS_CONTENTS \
{ \
/* NO_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
/* BASE_REGS. */ \
- { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
+ { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, \
/* GENERAL_REGS. */ \
- { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
+ { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, \
/* FLOAT_REGS. */ \
- { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
/* ALTIVEC_REGS. */ \
- { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \
/* VSX_REGS. */ \
- { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \
+ { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, \
/* VRSAVE_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
/* VSCR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \
/* SPE_ACC_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, \
/* SPEFSCR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \
/* SPR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
/* NON_SPECIAL_REGS. */ \
- { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \
+ { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, \
/* LINK_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \
/* CTR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \
/* LINK_OR_CTR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \
/* SPECIAL_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \
/* SPEC_OR_GEN_REGS. */ \
- { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \
+ { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, \
/* CR0_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \
/* CR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \
/* NON_FLOAT_REGS. */ \
- { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \
+ { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, \
/* CA_REGS. */ \
- { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \
- /* SPE_HIGH_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \
+ { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \
/* ALL_REGS. */ \
- { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \
+ { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } \
}
/* The same information, inverted:
@@ -2461,39 +2435,6 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
&rs6000_reg_names[114][0], /* tfhar */ \
&rs6000_reg_names[115][0], /* tfiar */ \
&rs6000_reg_names[116][0], /* texasr */ \
- \
- &rs6000_reg_names[117][0], /* SPE rh0. */ \
- &rs6000_reg_names[118][0], /* SPE rh1. */ \
- &rs6000_reg_names[119][0], /* SPE rh2. */ \
- &rs6000_reg_names[120][0], /* SPE rh3. */ \
- &rs6000_reg_names[121][0], /* SPE rh4. */ \
- &rs6000_reg_names[122][0], /* SPE rh5. */ \
- &rs6000_reg_names[123][0], /* SPE rh6. */ \
- &rs6000_reg_names[124][0], /* SPE rh7. */ \
- &rs6000_reg_names[125][0], /* SPE rh8. */ \
- &rs6000_reg_names[126][0], /* SPE rh9. */ \
- &rs6000_reg_names[127][0], /* SPE rh10. */ \
- &rs6000_reg_names[128][0], /* SPE rh11. */ \
- &rs6000_reg_names[129][0], /* SPE rh12. */ \
- &rs6000_reg_names[130][0], /* SPE rh13. */ \
- &rs6000_reg_names[131][0], /* SPE rh14. */ \
- &rs6000_reg_names[132][0], /* SPE rh15. */ \
- &rs6000_reg_names[133][0], /* SPE rh16. */ \
- &rs6000_reg_names[134][0], /* SPE rh17. */ \
- &rs6000_reg_names[135][0], /* SPE rh18. */ \
- &rs6000_reg_names[136][0], /* SPE rh19. */ \
- &rs6000_reg_names[137][0], /* SPE rh20. */ \
- &rs6000_reg_names[138][0], /* SPE rh21. */ \
- &rs6000_reg_names[139][0], /* SPE rh22. */ \
- &rs6000_reg_names[140][0], /* SPE rh22. */ \
- &rs6000_reg_names[141][0], /* SPE rh24. */ \
- &rs6000_reg_names[142][0], /* SPE rh25. */ \
- &rs6000_reg_names[143][0], /* SPE rh26. */ \
- &rs6000_reg_names[144][0], /* SPE rh27. */ \
- &rs6000_reg_names[145][0], /* SPE rh28. */ \
- &rs6000_reg_names[146][0], /* SPE rh29. */ \
- &rs6000_reg_names[147][0], /* SPE rh30. */ \
- &rs6000_reg_names[148][0], /* SPE rh31. */ \
}
/* Table of additional register names to use in user input. */
@@ -2550,15 +2491,6 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
{"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
/* Transactional Memory Facility (HTM) Registers. */ \
{"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \
- /* SPE high registers. */ \
- {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \
- {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \
- {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \
- {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \
- {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \
- {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \
- {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \
- {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \
}
/* This is how to output an element of a case-vector that is relative. */
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 2790dd6..39302f3 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -3569,8 +3569,6 @@ Define this macro if the target's representation for dwarf registers
is different than the internal representation for unwind column.
Given a dwarf register, this macro should return the internal unwind
column number to use instead.
-
-See the PowerPC's SPE target for an example.
@end defmac
@defmac DWARF_FRAME_REGNUM (@var{regno})
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index dff6cf8..98f2e6b 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -3129,8 +3129,6 @@ Define this macro if the target's representation for dwarf registers
is different than the internal representation for unwind column.
Given a dwarf register, this macro should return the internal unwind
column number to use instead.
-
-See the PowerPC's SPE target for an example.
@end defmac
@defmac DWARF_FRAME_REGNUM (@var{regno})
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 13/14] rs6000: Remove spe_acc and spefscr
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
` (10 preceding siblings ...)
2017-06-06 15:58 ` [PATCH 09/14] rs6000: Remove reg_or_none500mem_operand Segher Boessenkool
@ 2017-06-06 15:58 ` Segher Boessenkool
2017-06-06 17:11 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 10/14] rs6000: Remove spe.md, spe.h, linuxspe.h Segher Boessenkool
2017-06-06 15:59 ` [PATCH 14/14] rs6000: Remove rs6000_nonimmediate_operand Segher Boessenkool
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:58 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
We can also remove the two other SPE registers.
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE_ACC and
SPEFSCR registers.
* config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Ditto.
(enum rs6000_reg_type): Delete SPE_ACC_TYPE and SPEFSCR_REG_TYPE.
(rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
(rs6000_dbx_register_number): Adjust.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Change to 115.
(FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS):
Remove SPE_ACC and SPEFSCR.
(REG_ALLOC_ORDER): Ditto.
(FRAME_POINTER_REGNUM): Change to 111.
(enum reg_class): Remove the SPE_ACC and SPEFSCR registers.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Delete the SPE_ACC and SPEFSCR registers.
(REGISTER_NAMES): Ditto.
(ADDITIONAL_REG_NAMES): Ditto.
(rs6000_reg_names): Ditto.
* config/rs6000/rs6000.md: Renumber some register number
define_constants.
---
gcc/config/rs6000/darwin.h | 1 -
gcc/config/rs6000/rs6000.c | 16 ---------------
gcc/config/rs6000/rs6000.h | 48 +++++++++++++++++----------------------------
gcc/config/rs6000/rs6000.md | 10 ++++------
4 files changed, 22 insertions(+), 53 deletions(-)
diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index 2422f25..90fc757 100644
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -192,7 +192,6 @@ extern int darwin_emit_branch_islands;
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
"vrsave", "vscr", \
- "spe_acc", "spefscr", \
"sfp", \
"tfhar", "tfiar", "texasr" \
}
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 426400c..415ac1b 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -408,8 +408,6 @@ enum rs6000_reg_type {
FPR_REG_TYPE,
SPR_REG_TYPE,
CR_REG_TYPE,
- SPE_ACC_TYPE,
- SPEFSCR_REG_TYPE
};
/* Map register class to register type. */
@@ -1473,8 +1471,6 @@ char rs6000_reg_names[][8] =
"16", "17", "18", "19", "20", "21", "22", "23",
"24", "25", "26", "27", "28", "29", "30", "31",
"vrsave", "vscr",
- /* SPE registers. */
- "spe_acc", "spefscr",
/* Soft frame pointer. */
"sfp",
/* HTM SPR registers. */
@@ -1501,8 +1497,6 @@ static const char alt_reg_names[][8] =
"%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
"%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
"vrsave", "vscr",
- /* SPE registers. */
- "spe_acc", "spefscr",
/* Soft frame pointer. */
"sfp",
/* HTM SPR registers. */
@@ -2470,8 +2464,6 @@ rs6000_debug_reg_global (void)
rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
- rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
- rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
fputs ("\nVirtual/stack/frame registers:\n", stderr);
for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
@@ -2980,8 +2972,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_regno_regclass[CA_REGNO] = NO_REGS;
rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
- rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
- rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
@@ -3004,8 +2994,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
- reg_class_to_reg_type[(int)SPE_ACC_REGS] = SPE_ACC_TYPE;
- reg_class_to_reg_type[(int)SPEFSCR_REGS] = SPEFSCR_REG_TYPE;
if (TARGET_VSX)
{
@@ -37363,10 +37351,6 @@ rs6000_dbx_register_number (unsigned int regno, unsigned int format)
return 356;
if (regno == VSCR_REGNO)
return 67;
- if (regno == SPE_ACC_REGNO)
- return 99;
- if (regno == SPEFSCR_REGNO)
- return 612;
#endif
return regno;
}
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index a154c5d..edfa546 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1017,7 +1017,7 @@ enum data_align { align_abi, align_opt, align_both };
The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
-#define FIRST_PSEUDO_REGISTER 117
+#define FIRST_PSEUDO_REGISTER 115
/* This must be included for pre gcc 3.0 glibc compatibility. */
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
@@ -1056,7 +1056,7 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \
- , 1, 1, 1, 1, 1, 1 \
+ , 1, 1, 1, 1 \
}
/* 1 for registers not available across function calls.
@@ -1076,7 +1076,7 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \
- , 1, 1, 1, 1, 1, 1 \
+ , 1, 1, 1, 1 \
}
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -1095,7 +1095,7 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0 \
- , 0, 0, 0, 0, 0, 0 \
+ , 0, 0, 0, 0 \
}
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -1133,7 +1133,6 @@ enum data_align { align_abi, align_opt, align_both };
v19 - v14 (not saved or used for anything)
v31 - v20 (saved; order given to save least number)
vrsave, vscr (fixed)
- spe_acc, spefscr (fixed)
sfp (fixed)
tfhar (fixed)
tfiar (fixed)
@@ -1179,7 +1178,7 @@ enum data_align { align_abi, align_opt, align_both };
96, 95, 94, 93, 92, 91, \
108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
109, 110, \
- 111, 112, 113, 114, 115, 116 \
+ 111, 112, 113, 114 \
}
/* True if register is floating-point. */
@@ -1351,7 +1350,7 @@ enum data_align { align_abi, align_opt, align_both };
#define HARD_FRAME_POINTER_REGNUM 31
/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 113
+#define FRAME_POINTER_REGNUM 111
/* Base register for access to arguments of the function. */
#define ARG_POINTER_REGNUM 67
@@ -1404,8 +1403,6 @@ enum reg_class
VSX_REGS,
VRSAVE_REGS,
VSCR_REGS,
- SPE_ACC_REGS,
- SPEFSCR_REGS,
SPR_REGS,
NON_SPECIAL_REGS,
LINK_REGS,
@@ -1435,8 +1432,6 @@ enum reg_class
"VSX_REGS", \
"VRSAVE_REGS", \
"VSCR_REGS", \
- "SPE_ACC_REGS", \
- "SPEFSCR_REGS", \
"SPR_REGS", \
"NON_SPECIAL_REGS", \
"LINK_REGS", \
@@ -1460,9 +1455,9 @@ enum reg_class
/* NO_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
/* BASE_REGS. */ \
- { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, \
+ { 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 }, \
/* GENERAL_REGS. */ \
- { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, \
+ { 0xffffffff, 0x00000000, 0x00000008, 0x00008000 }, \
/* FLOAT_REGS. */ \
{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
/* ALTIVEC_REGS. */ \
@@ -1473,14 +1468,10 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
/* VSCR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \
- /* SPE_ACC_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, \
- /* SPEFSCR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \
/* SPR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \
/* NON_SPECIAL_REGS. */ \
- { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, \
+ { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \
/* LINK_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \
/* CTR_REGS. */ \
@@ -1490,17 +1481,17 @@ enum reg_class
/* SPECIAL_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \
/* SPEC_OR_GEN_REGS. */ \
- { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, \
+ { 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 }, \
/* CR0_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \
/* CR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \
/* NON_FLOAT_REGS. */ \
- { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, \
+ { 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 }, \
/* CA_REGS. */ \
{ 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \
/* ALL_REGS. */ \
- { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } \
+ { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff } \
}
/* The same information, inverted:
@@ -2429,12 +2420,10 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
&rs6000_reg_names[108][0], /* v31 */ \
&rs6000_reg_names[109][0], /* vrsave */ \
&rs6000_reg_names[110][0], /* vscr */ \
- &rs6000_reg_names[111][0], /* spe_acc */ \
- &rs6000_reg_names[112][0], /* spefscr */ \
- &rs6000_reg_names[113][0], /* sfp */ \
- &rs6000_reg_names[114][0], /* tfhar */ \
- &rs6000_reg_names[115][0], /* tfiar */ \
- &rs6000_reg_names[116][0], /* texasr */ \
+ &rs6000_reg_names[111][0], /* sfp */ \
+ &rs6000_reg_names[112][0], /* tfhar */ \
+ &rs6000_reg_names[113][0], /* tfiar */ \
+ &rs6000_reg_names[114][0], /* texasr */ \
}
/* Table of additional register names to use in user input. */
@@ -2465,7 +2454,6 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
{"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
{"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
{"vrsave", 109}, {"vscr", 110}, \
- {"spe_acc", 111}, {"spefscr", 112}, \
/* no additional names for: lr, ctr, ap */ \
{"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
{"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
@@ -2490,7 +2478,7 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
{"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
{"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
/* Transactional Memory Facility (HTM) Registers. */ \
- {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \
+ {"tfhar", 112}, {"tfiar", 113}, {"texasr", 114}, \
}
/* This is how to output an element of a case-vector that is relative. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9cf761c..d0120d1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -50,12 +50,10 @@ (define_constants
(LAST_ALTIVEC_REGNO 108)
(VRSAVE_REGNO 109)
(VSCR_REGNO 110)
- (SPE_ACC_REGNO 111)
- (SPEFSCR_REGNO 112)
- (FRAME_POINTER_REGNUM 113)
- (TFHAR_REGNO 114)
- (TFIAR_REGNO 115)
- (TEXASR_REGNO 116)
+ (FRAME_POINTER_REGNUM 111)
+ (TFHAR_REGNO 112)
+ (TFIAR_REGNO 113)
+ (TEXASR_REGNO 114)
])
;;
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 08/14] rs6000: Remove -mspe options
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
` (6 preceding siblings ...)
2017-06-06 15:58 ` [PATCH 07/14] rs6000: Remove TARGET_SPE and TARGET_SPE_ABI and friends Segher Boessenkool
@ 2017-06-06 15:58 ` Segher Boessenkool
2017-06-06 17:05 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 11/14] rs6000: Remove type attribute "brinc" Segher Boessenkool
` (5 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:58 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.c (rs6000_option_override_internal): Delete
handling of SPE flags.
* config/rs6000/rs6000.opt (-mspe, -mspe=no, -mspe=yes): Delete.
---
gcc/config/rs6000/rs6000.c | 18 ------------------
gcc/config/rs6000/rs6000.opt | 12 ------------
2 files changed, 30 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index a2bf968..89f9fc2 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4146,24 +4146,6 @@ rs6000_option_override_internal (bool global_init_p)
gcc_assert (tune_index >= 0);
rs6000_cpu = processor_target_table[tune_index].processor;
- /* Pick defaults for SPE related control flags. Do this early to make sure
- that the TARGET_ macros are representative ASAP. */
- {
- int spe_capable_cpu =
- (rs6000_cpu == PROCESSOR_PPC8540
- || rs6000_cpu == PROCESSOR_PPC8548);
-
- if (!global_options_set.x_rs6000_spe)
- rs6000_spe = spe_capable_cpu;
- }
-
- if (global_options_set.x_rs6000_spe && rs6000_spe)
- error ("not configured for SPE instruction set");
-
- if (main_target_opt != NULL
- && main_target_opt->x_rs6000_spe != rs6000_spe)
- error ("target attribute or pragma changes SPE ABI");
-
if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
|| rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
|| rs6000_cpu == PROCESSOR_PPCE5500)
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index a1a7753..28d8993 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -353,22 +353,10 @@ misel=yes
Target RejectNegative Alias(misel)
Deprecated option. Use -misel instead.
-mspe
-Target Var(rs6000_spe) Save
-Generate SPE SIMD instructions on E500.
-
mpaired
Target Var(rs6000_paired_float) Save
Generate PPC750CL paired-single instructions.
-mspe=no
-Target RejectNegative Alias(mspe) NegativeAlias
-Deprecated option. Use -mno-spe instead.
-
-mspe=yes
-Target RejectNegative Alias(mspe)
-Deprecated option. Use -mspe instead.
-
mdebug=
Target RejectNegative Joined
-mdebug= Enable debug output.
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 11/14] rs6000: Remove type attribute "brinc"
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
` (7 preceding siblings ...)
2017-06-06 15:58 ` [PATCH 08/14] rs6000: Remove -mspe options Segher Boessenkool
@ 2017-06-06 15:58 ` Segher Boessenkool
2017-06-06 17:07 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 12/14] rs6000: Remove SPE high registers Segher Boessenkool
` (4 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:58 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
Nothing uses it anymore.
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/8540.md (ppc8540_brinc): Delete.
* config/rs6000/e500mc.md (e500mc_brinc): Delete.
* config/rs6000/e500mc64.md (e500mc64_brinc): Delete.
* config/rs6000/rs6000.md (type): Remove "brinc".
---
gcc/config/rs6000/8540.md | 6 ------
gcc/config/rs6000/e500mc.md | 6 ------
gcc/config/rs6000/e500mc64.md | 6 ------
gcc/config/rs6000/rs6000.md | 1 -
4 files changed, 19 deletions(-)
diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md
index fae369d..7b91b5b 100644
--- a/gcc/config/rs6000/8540.md
+++ b/gcc/config/rs6000/8540.md
@@ -182,12 +182,6 @@ (define_insn_reservation "ppc8540_float_vector_divide" 29
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
ppc8540_mu_div*28")
-;; Brinc
-(define_insn_reservation "ppc8540_brinc" 1
- (and (eq_attr "type" "brinc")
- (eq_attr "cpu" "ppc8540,ppc8548"))
- "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
-
;; Simple vector
(define_insn_reservation "ppc8540_simple_vector" 1
(and (eq_attr "type" "vecsimple,veclogical,vecmove")
diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md
index 9878aaa..9f7f884 100644
--- a/gcc/config/rs6000/e500mc.md
+++ b/gcc/config/rs6000/e500mc.md
@@ -132,12 +132,6 @@ (define_insn_reservation "e500mc_mtjmpr" 1
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
-;; Brinc.
-(define_insn_reservation "e500mc_brinc" 1
- (and (eq_attr "type" "brinc")
- (eq_attr "cpu" "ppce500mc"))
- "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
-
;; Loads.
(define_insn_reservation "e500mc_load" 3
(and (eq_attr "type" "load,load_l,sync")
diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md
index 366b4c4..6f1ec81 100644
--- a/gcc/config/rs6000/e500mc64.md
+++ b/gcc/config/rs6000/e500mc64.md
@@ -151,12 +151,6 @@ (define_insn_reservation "e500mc64_mtjmpr" 1
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
-;; Brinc.
-(define_insn_reservation "e500mc64_brinc" 1
- (and (eq_attr "type" "brinc")
- (eq_attr "cpu" "ppce500mc64"))
- "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
-
;; Loads.
(define_insn_reservation "e500mc64_load" 3
(and (eq_attr "type" "load,load_l,sync")
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ec25f45..9cf761c 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -179,7 +179,6 @@ (define_attr "type"
branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
- brinc,
vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
veclogical,veccmpfx,vecexts,vecmove,
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 14/14] rs6000: Remove rs6000_nonimmediate_operand
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
` (12 preceding siblings ...)
2017-06-06 15:58 ` [PATCH 10/14] rs6000: Remove spe.md, spe.h, linuxspe.h Segher Boessenkool
@ 2017-06-06 15:59 ` Segher Boessenkool
2017-06-06 17:11 ` David Edelsohn
13 siblings, 1 reply; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-06 15:59 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
Now rs6000_nonimmediate_operand is just nonimmediate_operand.
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/predicates.md (rs6000_nonimmediate_operand): Delete.
* config/rs6000/rs6000.md (*movsi_internal1, movsi_from_sf,
*mov<mode>_softfloat, and an anonymous splitter): Use
nonimmediate_operand instead of rs6000_nonimmediate_operand.
---
gcc/config/rs6000/predicates.md | 7 -------
gcc/config/rs6000/rs6000.md | 14 +++++++-------
2 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 1bf9194..aa1c01b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1150,13 +1150,6 @@ (define_predicate "splat_input_operand"
return gpc_reg_operand (op, mode);
})
-;; Return true if OP is a non-immediate operand.
-(define_predicate "rs6000_nonimmediate_operand"
- (match_code "reg,subreg,mem")
-{
- return nonimmediate_operand (op, mode);
-})
-
;; Return true if operand is an operator used in rotate-and-mask instructions.
(define_predicate "rotate_mask_operator"
(match_code "rotate,ashift,lshiftrt"))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d0120d1..1bb565a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6693,7 +6693,7 @@ (define_insn "movsi_low"
;; XXLXOR 0 XXLORC -1 P9 const MTVSRWZ MFVSRWZ
;; MF%1 MT%0 MT%0 NOP
(define_insn "*movsi_internal1"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand"
+ [(set (match_operand:SI 0 "nonimmediate_operand"
"=r, r, r, ?*wI, ?*wH,
m, ?Z, ?Z, r, r,
r, ?*wIwH, ?*wJwK, ?*wJwK, ?*wu,
@@ -6749,7 +6749,7 @@ (define_insn "*movsi_internal1"
4, 4, 4, 4")])
(define_insn "*movsi_internal1_single"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
(match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
"TARGET_SINGLE_FPU &&
(gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
@@ -6790,7 +6790,7 @@ (define_insn "*movsi_internal1_single"
;; VSX->VSX
(define_insn_and_split "movsi_from_sf"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand"
+ [(set (match_operand:SI 0 "nonimmediate_operand"
"=r, r, ?*wI, ?*wH, m,
m, wY, Z, r, wIwH,
?wK")
@@ -7236,7 +7236,7 @@ (define_insn "*mov<mode>_softfloat"
;; LWZ LFS LXSSP LXSSPX STW STFIWX
;; STXSIWX GPR->VSX VSX->GPR GPR->GPR
(define_insn_and_split "movsf_from_si"
- [(set (match_operand:SF 0 "rs6000_nonimmediate_operand"
+ [(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, wb, wu, m, Z,
Z, wy, ?r, !r")
@@ -7521,7 +7521,7 @@ (define_insn_and_split "*mov<mode>_32bit"
[(set_attr "length" "8,8,8,8,20,20,16")])
(define_insn_and_split "*mov<mode>_softfloat"
- [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
+ [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=Y,r,r")
(match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
"TARGET_SOFT_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
@@ -8463,7 +8463,7 @@ (define_insn "p8_mfvsrd_4_disf"
;; AVX const
(define_insn "*movdi_internal32"
- [(set (match_operand:DI 0 "rs6000_nonimmediate_operand"
+ [(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, ^m, ^d, ^d,
r, ^wY, $Z, ^wb, $wv, ^wi,
*wo, *wo, *wv, *wi, *wi, *wv,
@@ -8525,7 +8525,7 @@ (define_split
}")
(define_split
- [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
+ [(set (match_operand:DIFD 0 "nonimmediate_operand" "")
(match_operand:DIFD 1 "input_operand" ""))]
"reload_completed && !TARGET_POWERPC64
&& gpr_or_gpr_p (operands[0], operands[1])
--
1.9.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 01/14] rs6000: Remove TARGET_FPRS
2017-06-06 15:57 ` [PATCH 01/14] rs6000: Remove TARGET_FPRS Segher Boessenkool
@ 2017-06-06 16:59 ` David Edelsohn
2017-06-12 10:02 ` [BUILDROBOT] No rule to make target '/home/jbglaw/repos/gcc/gcc/config/rs6000/e500.h', needed by 's-gtype' (was: [PATCH 01/14] rs6000: Remove TARGET_FPRS) Jan-Benedict Glaw
1 sibling, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 16:59 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> Since rs6000 no longer supports SPE, TARGET_FPRS now always is true.
>
> This makes TARGET_{SF,DF}_SPE always false. Many patterns in spe.md
> can now be deleted; which makes it possible to merge e.g. negdd2 with
> *negdd2_fpr.
>
> Finally, e500.h is deleted (it isn't used).
>
>
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config/rs6000/darwin.md: Replace TARGET_FPRS by 1 and simplify.
> * config/rs6000/dfp.md: Ditto.
> (negdd2, *negdd2_fpr): Merge.
> (absdd2, *absdd2_fpr): Merge.
> (negtd2, *negtd2_fpr): Merge.
> (abstd2, *abstd2_fpr): Merge.
> * config/rs6000/e500.h: Delete file.
> * config/rs6000/predicates.md (rs6000_cbranch_operator): Replace
> TARGET_FPRS by 1 and simplify.
> * config/rs6000/rs6000-c.c: Ditto.
> * config/rs6000/rs6000.c: Ditto. Also replace TARGET_SF_SPE and
> TARGET_DF_SPE by 0.
> * config/rs6000/rs6000.h: Ditto. Delete TARGET_SF_SPE and
> TARGET_DF_SPE.
> * config/rs6000/rs6000.md: Ditto.
> (floatdidf2, *floatdidf2_fpr): Merge.
> (move_from_CR_gt_bit): Delete.
> * config/rs6000/spe.md: Replace TARGET_FPRS by 1 and simplify.
> (E500_CR_IOR_COMPARE): Delete.
> (All patterns that require !TARGET_FPRS): Delete.
> * config/rs6000/vsx.md: Replace TARGET_FPRS by 1 and simplify.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 02/14] rs6000: Remove TARGET_E500_{SINGLE,DOUBLE}
2017-06-06 15:57 ` [PATCH 02/14] rs6000: Remove TARGET_E500_{SINGLE,DOUBLE} Segher Boessenkool
@ 2017-06-06 17:00 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:00 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> Similarly, TARGET_E500_{SINGLE,DOUBLE} is always false now.
>
>
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config/rs6000/predicates.md: Replace TARGET_E500_DOUBLE and
> TARGET_E500_SINGLE by 0, simplify.
> * config/rs6000/rs6000.c: Ditto.
> (rs6000_option_override_internal): Delete CHECK_E500_OPTIONS.
> (spe_build_register_parallel): Delete.
> * config/rs6000/rs6000.h: Delete TARGET_E500_SINGLE,
> TARGET_E500_DOUBLE, and CHECK_E500_OPTIONS.
> * config/rs6000/rs6000.md: Replace TARGET_E500_DOUBLE,
> TARGET_E500_SINGLE, and <E500_CONVERT> by 0, simplify.
> (E500_CONVERT): Delete.
> * config/rs6000/spe.md: Remove many patterns and all define_constants.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 04/14] rs6000: Remove rs6000_cbranch_operator
2017-06-06 15:57 ` [PATCH 04/14] rs6000: Remove rs6000_cbranch_operator Segher Boessenkool
@ 2017-06-06 17:01 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:01 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> rs6000_cbranch_operator now is just comparison_operator, so just use
> that directly.
>
>
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config/rs6000/predicated.md (rs6000_cbranch_operator): Delete.
> * config/rs6000/rs6000.md: Replace rs6000_cbranch_operator by
> comparison_operator.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 03/14] rs6000: Remove -mfloat-gprs
2017-06-06 15:57 ` [PATCH 03/14] rs6000: Remove -mfloat-gprs Segher Boessenkool
@ 2017-06-06 17:01 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:01 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> This deletes -mfloat-gprs and the variables that go with it.
>
>
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config/rs6000/rs6000.c: Remove everything related to -mfloat-gprs.
> * config/rs6000/rs6000.opt: Ditto.
> * config/rs6000/t-rtems: Ditto.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 05/14] rs6000: Remove output_e500_flip_gt_bit
2017-06-06 15:57 ` [PATCH 05/14] rs6000: Remove output_e500_flip_gt_bit Segher Boessenkool
@ 2017-06-06 17:02 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:02 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config/rs6000/rs6000-protos.h (output_e500_flip_gt_bit): Delete.
> * config/rs6000/rs6000.c: Ditto.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 06/14] rs6000: Remove UNSPEC_MV_CR_GT
2017-06-06 15:58 ` [PATCH 06/14] rs6000: Remove UNSPEC_MV_CR_GT Segher Boessenkool
@ 2017-06-06 17:02 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:02 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> config/rs6000/rs6000.md (UNSPEC_MV_CR_GT): Delete.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 07/14] rs6000: Remove TARGET_SPE and TARGET_SPE_ABI and friends
2017-06-06 15:58 ` [PATCH 07/14] rs6000: Remove TARGET_SPE and TARGET_SPE_ABI and friends Segher Boessenkool
@ 2017-06-06 17:04 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:04 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config/rs6000/rs6000-common.c (rs6000_handle_option): Remove
> SPE ABI handling.
> * config/rs6000/paired.md (paired_negv2sf2): Rename to negv2sf2.
> (paired_absv2sf2, paired_addv2sf3, paired_subv2sf3, paired_mulv2sf3,
> paired_divv2sf3): Similar.
> * config/rs6000/predicates.md: Replace TARGET_SPE, TARGET_SPE_ABI,
> SPE_VECTOR_MODE and SPE_HIGH_REGNO_P by 0; simplify.
> * config/rs6000/rs6000-builtin.def: Delete RS6000_BUILTIN_E and
> RS6000_BUILTIN_S.
> Delete BU_SPE_1, BU_SPE_2, BU_SPE_3, BU_SPE_E, BU_SPE_P, and BU_SPE_X.
> Rename the paired_* instruction patterns.
> * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Do not
> define __SPE__.
> * config/rs6000/rs6000-protos.h (invalid_e500_subreg): Delete.
> * config/rs6000/rs6000.c: Delete RS6000_BUILTIN_E and RS6000_BUILTIN_S.
> (struct rs6000_stack): Delete fields spe_gp_save_offset, spe_gp_size,
> spe_padding_size, and spe_64bit_regs_used. Replace TARGET_SPE and
> TARGET_SPE_ABI with 0, simplify. Replace SPE_VECTOR_MODE with
> PAIRED_VECTOR_MODE.
> (struct machine_function): Delete field spe_insn_chain_scanned_p.
> (spe_func_has_64bit_regs_p): Delete.
> (spe_expand_predicate_builtin): Delete.
> (spe_expand_evsel_builtin): Delete.
> (TARGET_DWARF_REGISTER_SPAN): Do not define.
> (TARGET_MEMBER_TYPE_FORCES_BLK): Do not define.
> (invalid_e500_subreg): Delete.
> (rs6000_legitimize_address): Always force_reg op2 as well, for
> paired single memory accesses.
> (rs6000_member_type_forces_blk): Delete.
> (rs6000_spe_function_arg): Delete.
> (rs6000_expand_unop_builtin): Delete SPE handling.
> (rs6000_expand_binop_builtin): Ditto.
> (spe_expand_stv_builtin): Delete.
> (bdesc_2arg_spe): Delete.
> (spe_expand_builtin): Delete.
> (spe_expand_predicate_builtin): Delete.
> (spe_expand_evsel_builtin): Delete.
> (rs6000_invalid_builtin): Remove RS6000_BTM_SPE handling.
> (spe_init_builtins): Delete.
> (spe_func_has_64bit_regs_p): Delete.
> (savres_routine_name): Delete "info" parameter. Adjust callers.
> (rs6000_emit_stack_reset): Ditto.
> (rs6000_dwarf_register_span): Delete.
> * config/rs6000/rs6000.h (TARGET_SPE_ABI, TARGET_SPE,
> UNITS_PER_SPE_WORD, SPE_HIGH_REGNO_P, SPE_SIMD_REGNO_P,
> SPE_VECTOR_MODE, RS6000_BTM_SPE, RS6000_BUILTIN_E, RS6000_BUILTIN_S):
> Delete.
> * config/rs6000/rs6000.md (FIRST_SPE_HIGH_REGNO, LAST_SPE_HIGH_REGNO):
> Delete.
> * config/rs6000/rs6000.opt (-mabi=spe, -mabi=no-spe): Delete.
> * config/rs6000/spe.md: Delete every pattern that uses TARGET_SPE.
> * config/rs6000/vector.md (absv2sf2, negv2sf2, addv2sf3, subv2sf3,
> mulv2sf3, divv2sf3): Delete expanders.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 08/14] rs6000: Remove -mspe options
2017-06-06 15:58 ` [PATCH 08/14] rs6000: Remove -mspe options Segher Boessenkool
@ 2017-06-06 17:05 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:05 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config/rs6000/rs6000.c (rs6000_option_override_internal): Delete
> handling of SPE flags.
> * config/rs6000/rs6000.opt (-mspe, -mspe=no, -mspe=yes): Delete.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 09/14] rs6000: Remove reg_or_none500mem_operand
2017-06-06 15:58 ` [PATCH 09/14] rs6000: Remove reg_or_none500mem_operand Segher Boessenkool
@ 2017-06-06 17:06 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:06 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config/rs6000/predicates.md (reg_or_mem_operand): Reformat.
> (reg_or_none500mem_operand): Delete.
> * config/rs6000/rs6000.md (extendsfdf2): Use reg_or_mem_operand
> instead of reg_or_none500mem_operand.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 10/14] rs6000: Remove spe.md, spe.h, linuxspe.h
2017-06-06 15:58 ` [PATCH 10/14] rs6000: Remove spe.md, spe.h, linuxspe.h Segher Boessenkool
@ 2017-06-06 17:06 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:06 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config.gcc (powerpc*-*-*): Don't add spe.h to extra_headers.
> (powerpc*-linux*spe*): Use ${cpu_type} instead of rs6000.
> * config/rs6000/linuxspe.h: Delete file.
> * config/rs6000/rs6000.md: Don't include spe.md.
> * config/rs6000/spe.h: Delete file.
> * config/rs6000/spe.md: Delete file.
> * config/rs6000/t-rs6000: Remove spe.md.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 11/14] rs6000: Remove type attribute "brinc"
2017-06-06 15:58 ` [PATCH 11/14] rs6000: Remove type attribute "brinc" Segher Boessenkool
@ 2017-06-06 17:07 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:07 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> Nothing uses it anymore.
>
>
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config/rs6000/8540.md (ppc8540_brinc): Delete.
> * config/rs6000/e500mc.md (e500mc_brinc): Delete.
> * config/rs6000/e500mc64.md (e500mc64_brinc): Delete.
> * config/rs6000/rs6000.md (type): Remove "brinc".
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 12/14] rs6000: Remove SPE high registers
2017-06-06 15:58 ` [PATCH 12/14] rs6000: Remove SPE high registers Segher Boessenkool
@ 2017-06-06 17:09 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:09 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> Now we can remove the SPE high registers.
>
>
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE high
> registers.
> * config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Ditto.
> * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Change from 149
> to 117.
> (DWARF_REG_TO_UNWIND_COLUMN): Do not define.
> (FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS):
> Delete the SPE high registers.
> (REG_ALLOC_ORDER): Ditto.
> (enum reg_class): Remove SPE_HIGH_REGS.
> (REG_CLASS_NAMES): Ditto.
> (REG_CLASS_CONTENTS): Delete the SPE high registers.
> (REGISTER_NAMES): Ditto.
> (rs6000_reg_names): Ditto.
> * doc/tm.texi.in: Remove SPE as example.
> * doc/tm.texi: Regenerate.
Okay.
Thank, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 13/14] rs6000: Remove spe_acc and spefscr
2017-06-06 15:58 ` [PATCH 13/14] rs6000: Remove spe_acc and spefscr Segher Boessenkool
@ 2017-06-06 17:11 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:11 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> We can also remove the two other SPE registers.
>
>
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE_ACC and
> SPEFSCR registers.
> * config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Ditto.
> (enum rs6000_reg_type): Delete SPE_ACC_TYPE and SPEFSCR_REG_TYPE.
> (rs6000_debug_reg_global): Adjust.
> (rs6000_init_hard_regno_mode_ok): Adjust.
> (rs6000_dbx_register_number): Adjust.
> * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Change to 115.
> (FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS):
> Remove SPE_ACC and SPEFSCR.
> (REG_ALLOC_ORDER): Ditto.
> (FRAME_POINTER_REGNUM): Change to 111.
> (enum reg_class): Remove the SPE_ACC and SPEFSCR registers.
> (REG_CLASS_NAMES): Ditto.
> (REG_CLASS_CONTENTS): Delete the SPE_ACC and SPEFSCR registers.
> (REGISTER_NAMES): Ditto.
> (ADDITIONAL_REG_NAMES): Ditto.
> (rs6000_reg_names): Ditto.
> * config/rs6000/rs6000.md: Renumber some register number
> define_constants.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 14/14] rs6000: Remove rs6000_nonimmediate_operand
2017-06-06 15:59 ` [PATCH 14/14] rs6000: Remove rs6000_nonimmediate_operand Segher Boessenkool
@ 2017-06-06 17:11 ` David Edelsohn
0 siblings, 0 replies; 31+ messages in thread
From: David Edelsohn @ 2017-06-06 17:11 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> Now rs6000_nonimmediate_operand is just nonimmediate_operand.
>
>
> 2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
>
> * config/rs6000/predicates.md (rs6000_nonimmediate_operand): Delete.
> * config/rs6000/rs6000.md (*movsi_internal1, movsi_from_sf,
> *mov<mode>_softfloat, and an anonymous splitter): Use
> nonimmediate_operand instead of rs6000_nonimmediate_operand.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 31+ messages in thread
* [BUILDROBOT] No rule to make target '/home/jbglaw/repos/gcc/gcc/config/rs6000/e500.h', needed by 's-gtype' (was: [PATCH 01/14] rs6000: Remove TARGET_FPRS)
2017-06-06 15:57 ` [PATCH 01/14] rs6000: Remove TARGET_FPRS Segher Boessenkool
2017-06-06 16:59 ` David Edelsohn
@ 2017-06-12 10:02 ` Jan-Benedict Glaw
2017-06-12 10:40 ` Segher Boessenkool
1 sibling, 1 reply; 31+ messages in thread
From: Jan-Benedict Glaw @ 2017-06-12 10:02 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: gcc-patches, dje.gcc
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Hi Segher!
On Tue, 2017-06-06 15:56:17 +0000, Segher Boessenkool <segher@kernel.crashing.org> wrote:
> Since rs6000 no longer supports SPE, TARGET_FPRS now always is true.
>
> This makes TARGET_{SF,DF}_SPE always false. Many patterns in spe.md
> can now be deleted; which makes it possible to merge e.g. negdd2 with
> *negdd2_fpr.
>
> Finally, e500.h is deleted (it isn't used).
A Buildrobot build from today for powerpc-rtems still seems to use it,
see build
http://toolchain.lug-owl.de/buildbot/show_build_details.php?id=704903:
g++ -c -g -O2 -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall -Wno-narrowing -Wwrite-strings -Wcast-qual -Wmissing-format-attribute -Woverloaded-virtual -pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fno-common -DHAVE_CONFIG_H -DGENERATOR_FILE -fno-PIE -I. -Ibuild -I/home/jbglaw/repos/gcc/gcc -I/home/jbglaw/repos/gcc/gcc/build -I/home/jbglaw/repos/gcc/gcc/../include -I/home/jbglaw/repos/gcc/gcc/../libcpp/include \
-DBASEVER="\"8.0.0\"" -DDATESTAMP="\" 20170611\"" \
-DREVISION="\"\"" \
-DDEVPHASE="\" (experimental)\"" -DPKGVERSION="\"(GCC) \"" \
-DBUGURL="\"<https://gcc.gnu.org/bugs/>\"" -o build/version.o /home/jbglaw/repos/gcc/gcc/version.c
g++ -g -O2 -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall -Wno-narrowing -Wwrite-strings -Wcast-qual -Wmissing-format-attribute -Woverloaded-virtual -pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fno-common -DHAVE_CONFIG_H -DGENERATOR_FILE -fno-PIE -static-libstdc++ -static-libgcc -o build/gengtype \
build/gengtype.o build/errors.o build/gengtype-lex.o build/gengtype-parse.o build/gengtype-state.o build/version.o ../build-x86_64-pc-linux-gnu/libiberty/libiberty.a
LC_ALL=C ; export LC_ALL ; \
gawk -f /home/jbglaw/repos/gcc/gcc/opt-gather.awk /home/jbglaw/repos/gcc/gcc/ada/gcc-interface/lang.opt /home/jbglaw/repos/gcc/gcc/brig/lang.opt /home/jbglaw/repos/gcc/gcc/fortran/lang.opt /home/jbglaw/repos/gcc/gcc/go/lang.opt /home/jbglaw/repos/gcc/gcc/lto/lang.opt /home/jbglaw/repos/gcc/gcc/c-family/c.opt /home/jbglaw/repos/gcc/gcc/common.opt /home/jbglaw/repos/gcc/gcc/config/g.opt /home/jbglaw/repos/gcc/gcc/config/fused-madd.opt /home/jbglaw/repos/gcc/gcc/config/rs6000/rs6000-tables.opt /home/jbglaw/repos/gcc/gcc/config/rs6000/rs6000.opt /home/jbglaw/repos/gcc/gcc/config/rtems.opt /home/jbglaw/repos/gcc/gcc/config/rs6000/sysv4.opt > tmp-optionlist
/bin/bash /home/jbglaw/repos/gcc/gcc/../move-if-change tmp-optionlist optionlist
echo timestamp > s-options
gawk -f /home/jbglaw/repos/gcc/gcc/opt-functions.awk -f /home/jbglaw/repos/gcc/gcc/opt-read.awk \
-f /home/jbglaw/repos/gcc/gcc/opth-gen.awk \
< optionlist > tmp-options.h
/bin/bash /home/jbglaw/repos/gcc/gcc/../move-if-change tmp-options.h options.h
echo timestamp > s-options-h
make[1]: *** No rule to make target '/home/jbglaw/repos/gcc/gcc/config/rs6000/e500.h', needed by 's-gtype'. Stop.
make[1]: Leaving directory '/home/jbglaw/build/powerpc-rtems/build-gcc/gcc'
Makefile:4223: recipe for target 'all-gcc' failed
make: *** [all-gcc] Error 2
MfG, JBG
--
Jan-Benedict Glaw jbglaw@lug-owl.de +49-172-7608481
Signature of: "really soon now": an unspecified period of time, likly to
the second : be greater than any reasonable definition
of "soon".
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [BUILDROBOT] No rule to make target '/home/jbglaw/repos/gcc/gcc/config/rs6000/e500.h', needed by 's-gtype' (was: [PATCH 01/14] rs6000: Remove TARGET_FPRS)
2017-06-12 10:02 ` [BUILDROBOT] No rule to make target '/home/jbglaw/repos/gcc/gcc/config/rs6000/e500.h', needed by 's-gtype' (was: [PATCH 01/14] rs6000: Remove TARGET_FPRS) Jan-Benedict Glaw
@ 2017-06-12 10:40 ` Segher Boessenkool
0 siblings, 0 replies; 31+ messages in thread
From: Segher Boessenkool @ 2017-06-12 10:40 UTC (permalink / raw)
To: Jan-Benedict Glaw; +Cc: gcc-patches, dje.gcc
Hi!
On Mon, Jun 12, 2017 at 12:01:34PM +0200, Jan-Benedict Glaw wrote:
> On Tue, 2017-06-06 15:56:17 +0000, Segher Boessenkool <segher@kernel.crashing.org> wrote:
> > Since rs6000 no longer supports SPE, TARGET_FPRS now always is true.
> >
> > This makes TARGET_{SF,DF}_SPE always false. Many patterns in spe.md
> > can now be deleted; which makes it possible to merge e.g. negdd2 with
> > *negdd2_fpr.
> >
> > Finally, e500.h is deleted (it isn't used).
>
> A Buildrobot build from today for powerpc-rtems still seems to use it,
> see build
> http://toolchain.lug-owl.de/buildbot/show_build_details.php?id=704903:
Yeah, I forgot to delete it from some targets in config.gcc. Will fix.
Thanks,
Segher
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2017-06-12 10:40 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-06 15:56 [PATCH 00/14] rs6000: Delete SPE things Segher Boessenkool
2017-06-06 15:57 ` [PATCH 03/14] rs6000: Remove -mfloat-gprs Segher Boessenkool
2017-06-06 17:01 ` David Edelsohn
2017-06-06 15:57 ` [PATCH 02/14] rs6000: Remove TARGET_E500_{SINGLE,DOUBLE} Segher Boessenkool
2017-06-06 17:00 ` David Edelsohn
2017-06-06 15:57 ` [PATCH 04/14] rs6000: Remove rs6000_cbranch_operator Segher Boessenkool
2017-06-06 17:01 ` David Edelsohn
2017-06-06 15:57 ` [PATCH 05/14] rs6000: Remove output_e500_flip_gt_bit Segher Boessenkool
2017-06-06 17:02 ` David Edelsohn
2017-06-06 15:57 ` [PATCH 01/14] rs6000: Remove TARGET_FPRS Segher Boessenkool
2017-06-06 16:59 ` David Edelsohn
2017-06-12 10:02 ` [BUILDROBOT] No rule to make target '/home/jbglaw/repos/gcc/gcc/config/rs6000/e500.h', needed by 's-gtype' (was: [PATCH 01/14] rs6000: Remove TARGET_FPRS) Jan-Benedict Glaw
2017-06-12 10:40 ` Segher Boessenkool
2017-06-06 15:58 ` [PATCH 06/14] rs6000: Remove UNSPEC_MV_CR_GT Segher Boessenkool
2017-06-06 17:02 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 07/14] rs6000: Remove TARGET_SPE and TARGET_SPE_ABI and friends Segher Boessenkool
2017-06-06 17:04 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 08/14] rs6000: Remove -mspe options Segher Boessenkool
2017-06-06 17:05 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 11/14] rs6000: Remove type attribute "brinc" Segher Boessenkool
2017-06-06 17:07 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 12/14] rs6000: Remove SPE high registers Segher Boessenkool
2017-06-06 17:09 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 09/14] rs6000: Remove reg_or_none500mem_operand Segher Boessenkool
2017-06-06 17:06 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 13/14] rs6000: Remove spe_acc and spefscr Segher Boessenkool
2017-06-06 17:11 ` David Edelsohn
2017-06-06 15:58 ` [PATCH 10/14] rs6000: Remove spe.md, spe.h, linuxspe.h Segher Boessenkool
2017-06-06 17:06 ` David Edelsohn
2017-06-06 15:59 ` [PATCH 14/14] rs6000: Remove rs6000_nonimmediate_operand Segher Boessenkool
2017-06-06 17:11 ` David Edelsohn
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