From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13872 invoked by alias); 28 Feb 2017 12:29:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 13861 invoked by uid 89); 28 Feb 2017 12:29:56 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=exchange X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 28 Feb 2017 12:29:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3EC972B; Tue, 28 Feb 2017 04:29:53 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6793C3F3E1; Tue, 28 Feb 2017 04:29:52 -0800 (PST) Message-ID: <58B56D3E.3090704@foss.arm.com> Date: Tue, 28 Feb 2017 12:59:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: [PATCH][AArch64] Allow const0_rtx operand for atomic compare-exchange patterns Content-Type: multipart/mixed; boundary="------------010407070304040607080701" X-SW-Source: 2017-02/txt/msg01649.txt.bz2 This is a multi-part message in MIME format. --------------010407070304040607080701 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 1338 Hi all, For the testcase in this patch we currently generate: foo: mov w1, 0 ldaxr w2, [x0] cmp w2, 3 bne .L2 stxr w3, w1, [x0] cmp w3, 0 .L2: cset w0, eq ret Note that the STXR could have been storing the WZR register instead of moving zero into w1. This is due to overly strict predicates and constraints in the store exclusive pattern and the atomic compare exchange expanders and splitters. This simple patch fixes that in the patterns concerned and with it we can generate: foo: ldaxr w1, [x0] cmp w1, 3 bne .L2 stxr w2, wzr, [x0] cmp w2, 0 .L2: cset w0, eq ret Bootstrapped and tested on aarch64-none-linux-gnu. Ok for GCC 8? Thanks, Kyrill 2017-02-28 Kyrylo Tkachov * config/aarch64/atomics.md (atomic_compare_and_swap expander): Use aarch64_reg_or_zero predicate for operand 4. (aarch64_compare_and_swap define_insn_and_split): Use aarch64_reg_or_zero predicate for operand 3. Add 'Z' constraint. (aarch64_store_exclusive): Likewise for operand 2. 2017-02-28 Kyrylo Tkachov * gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: New test. --------------010407070304040607080701 Content-Type: text/x-patch; name="aarch64-cmp-zero.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="aarch64-cmp-zero.patch" Content-length: 2893 diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index 09d441075f0383420d26b7d3ccb62da2a3c44422..27fc1933ce39b6eddde9c092fa849e5f6645bea3 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -25,7 +25,7 @@ (define_expand "atomic_compare_and_swap" (match_operand:ALLI 1 "register_operand" "") ;; val out (match_operand:ALLI 2 "aarch64_sync_memory_operand" "") ;; memory (match_operand:ALLI 3 "general_operand" "") ;; expected - (match_operand:ALLI 4 "register_operand" "") ;; desired + (match_operand:ALLI 4 "aarch64_reg_or_zero" "") ;; desired (match_operand:SI 5 "const_int_operand") ;; is_weak (match_operand:SI 6 "const_int_operand") ;; mod_s (match_operand:SI 7 "const_int_operand")] ;; mod_f @@ -45,7 +45,7 @@ (define_insn_and_split "aarch64_compare_and_swap" (set (match_dup 1) (unspec_volatile:SHORT [(match_operand:SI 2 "aarch64_plus_operand" "rI") ;; expected - (match_operand:SHORT 3 "register_operand" "r") ;; desired + (match_operand:SHORT 3 "aarch64_reg_or_zero" "rZ") ;; desired (match_operand:SI 4 "const_int_operand") ;; is_weak (match_operand:SI 5 "const_int_operand") ;; mod_s (match_operand:SI 6 "const_int_operand")] ;; mod_f @@ -69,7 +69,7 @@ (define_insn_and_split "aarch64_compare_and_swap" (set (match_dup 1) (unspec_volatile:GPI [(match_operand:GPI 2 "aarch64_plus_operand" "rI") ;; expect - (match_operand:GPI 3 "register_operand" "r") ;; desired + (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ") ;; desired (match_operand:SI 4 "const_int_operand") ;; is_weak (match_operand:SI 5 "const_int_operand") ;; mod_s (match_operand:SI 6 "const_int_operand")] ;; mod_f @@ -534,7 +534,7 @@ (define_insn "aarch64_store_exclusive" (unspec_volatile:SI [(const_int 0)] UNSPECV_SX)) (set (match_operand:ALLI 1 "aarch64_sync_memory_operand" "=Q") (unspec_volatile:ALLI - [(match_operand:ALLI 2 "register_operand" "r") + [(match_operand:ALLI 2 "aarch64_reg_or_zero" "rZ") (match_operand:SI 3 "const_int_operand")] UNSPECV_SX))] "" diff --git a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c new file mode 100644 index 0000000000000000000000000000000000000000..15606b6899012dcb6616e0313d343b77249e1b24 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +foo (int *a) +{ + int x = 3; + return __atomic_compare_exchange_n (a, &x, 0, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); +} + +/* { dg-final { scan-assembler "stxr\\tw\[0-9\]+, wzr,.*" } } */ +/* { dg-final { scan-assembler-not "mov\\tw\[0-9\]+, 0" } } */ --------------010407070304040607080701--