From: Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>
To: "Hurugalawadi, Naveen" <Naveen.Hurugalawadi@cavium.com>,
James Greenhalgh <james.greenhalgh@arm.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
"Pinski, Andrew" <Andrew.Pinski@cavium.com>,
Marcus Shawcroft <marcus.shawcroft@arm.com>,
Richard Earnshaw <Richard.Earnshaw@arm.com>,
"nd@arm.com" <nd@arm.com>
Subject: Re: [PATCH][AArch64] Implement ALU_BRANCH fusion
Date: Wed, 15 Mar 2017 09:23:00 -0000 [thread overview]
Message-ID: <58C90822.8030802@foss.arm.com> (raw)
In-Reply-To: <CO2PR07MB2694F153A769D9F2E51D7CEB83270@CO2PR07MB2694.namprd07.prod.outlook.com>
Hi Naveen,
On 15/03/17 05:32, Hurugalawadi, Naveen wrote:
> Hi James,
>
>>> My reason for asking is that the instruction fusion implemented in LLVM
>>> ( lib/Target/AArch64/AArch64MacroFusion.cpp::shouldScheduleAdjacent )
> Sorry. There seems to be some confusion in the branch instructions.
> The branch should be conditional for ALU_BRANCH fusion.
>
> Please find attached the modified patch that fuses ALU instructions and
> conditional branches.
>
> Bootstrapped and Regression tested on aarch64-thunder-linux.
> Please review the patch and let us know if its okay?
>
> Thanks,
> Naveen
>
+ if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH)
+ && any_condjump_p (curr))
+ {
+ /* These types correspond to the reservation "vulcan_alu_basic" for
+ Broadcom Vulcan: these are ALU operations that produce a single uop
+ during instruction decoding. */
The comment here still looks wrong. There is no vulcan_alu_basic reservation in any of the scheduling models.
I suggest you reword the whole comment and not talk about particular CPUs, but rather about the kinds of instructions
you want to fuse. If a reader wants to know which CPUs enable this fusion they should be looking at the CPU tuning structures
rather than reading the comments here.
Kyrill
next prev parent reply other threads:[~2017-03-15 9:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-06 5:12 Hurugalawadi, Naveen
2017-03-08 18:04 ` James Greenhalgh
2017-03-09 6:22 ` Hurugalawadi, Naveen
2017-03-09 10:22 ` James Greenhalgh
2017-03-15 5:33 ` Hurugalawadi, Naveen
2017-03-15 9:23 ` Kyrill Tkachov [this message]
2017-03-15 10:04 ` Hurugalawadi, Naveen
[not found] <VI1PR0802MB26218E2C0940948518A0571783210@VI1PR0802MB2621.eurprd08.prod.outlook.com>
2017-03-15 15:20 ` Wilco Dijkstra
2017-03-21 5:37 ` Andrew Pinski
2017-03-27 7:33 ` Hurugalawadi, Naveen
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