From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 83058 invoked by alias); 15 Mar 2017 09:23:52 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 83042 invoked by uid 89); 15 Mar 2017 09:23:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=Hx-languages-length:1311 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 15 Mar 2017 09:23:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B9868344; Wed, 15 Mar 2017 02:23:48 -0700 (PDT) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8EF963F2E5; Wed, 15 Mar 2017 02:23:47 -0700 (PDT) Message-ID: <58C90822.8030802@foss.arm.com> Date: Wed, 15 Mar 2017 09:23:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "Hurugalawadi, Naveen" , James Greenhalgh CC: "gcc-patches@gcc.gnu.org" , "Pinski, Andrew" , Marcus Shawcroft , Richard Earnshaw , "nd@arm.com" Subject: Re: [PATCH][AArch64] Implement ALU_BRANCH fusion References: <20170308180359.GD25712@arm.com> ,<20170309102200.GA40049@arm.com> In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2017-03/txt/msg00804.txt.bz2 Hi Naveen, On 15/03/17 05:32, Hurugalawadi, Naveen wrote: > Hi James, > >>> My reason for asking is that the instruction fusion implemented in LLVM >>> ( lib/Target/AArch64/AArch64MacroFusion.cpp::shouldScheduleAdjacent ) > Sorry. There seems to be some confusion in the branch instructions. > The branch should be conditional for ALU_BRANCH fusion. > > Please find attached the modified patch that fuses ALU instructions and > conditional branches. > > Bootstrapped and Regression tested on aarch64-thunder-linux. > Please review the patch and let us know if its okay? > > Thanks, > Naveen > + if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH) + && any_condjump_p (curr)) + { + /* These types correspond to the reservation "vulcan_alu_basic" for + Broadcom Vulcan: these are ALU operations that produce a single uop + during instruction decoding. */ The comment here still looks wrong. There is no vulcan_alu_basic reservation in any of the scheduling models. I suggest you reword the whole comment and not talk about particular CPUs, but rather about the kinds of instructions you want to fuse. If a reader wants to know which CPUs enable this fusion they should be looking at the CPU tuning structures rather than reading the comments here. Kyrill